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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/cache-v4wb.S | |
3 | * | |
4 | * Copyright (C) 1997-2002 Russell king | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
1da177e4 LT |
10 | #include <linux/linkage.h> |
11 | #include <linux/init.h> | |
6ebbf2ce | 12 | #include <asm/assembler.h> |
95f3df6b | 13 | #include <asm/memory.h> |
1da177e4 LT |
14 | #include <asm/page.h> |
15 | #include "proc-macros.S" | |
16 | ||
17 | /* | |
18 | * The size of one data cache line. | |
19 | */ | |
20 | #define CACHE_DLINESIZE 32 | |
21 | ||
22 | /* | |
23 | * The total size of the data cache. | |
24 | */ | |
25 | #if defined(CONFIG_CPU_SA110) | |
26 | # define CACHE_DSIZE 16384 | |
27 | #elif defined(CONFIG_CPU_SA1100) | |
28 | # define CACHE_DSIZE 8192 | |
29 | #else | |
30 | # error Unknown cache size | |
31 | #endif | |
32 | ||
33 | /* | |
34 | * This is the size at which it becomes more efficient to | |
35 | * clean the whole cache, rather than using the individual | |
25985edc | 36 | * cache line maintenance instructions. |
1da177e4 LT |
37 | * |
38 | * Size Clean (ticks) Dirty (ticks) | |
39 | * 4096 21 20 21 53 55 54 | |
40 | * 8192 40 41 40 106 100 102 | |
41 | * 16384 77 77 76 140 140 138 | |
42 | * 32768 150 149 150 214 216 212 <--- | |
43 | * 65536 296 297 296 351 358 361 | |
44 | * 131072 591 591 591 656 657 651 | |
45 | * Whole 132 136 132 221 217 207 <--- | |
46 | */ | |
47 | #define CACHE_DLIMIT (CACHE_DSIZE * 4) | |
48 | ||
95f3df6b RK |
49 | .data |
50 | flush_base: | |
51 | .long FLUSH_BASE | |
52 | .text | |
53 | ||
c8c90860 MW |
54 | /* |
55 | * flush_icache_all() | |
56 | * | |
57 | * Unconditionally clean and invalidate the entire icache. | |
58 | */ | |
59 | ENTRY(v4wb_flush_icache_all) | |
60 | mov r0, #0 | |
61 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
6ebbf2ce | 62 | ret lr |
c8c90860 MW |
63 | ENDPROC(v4wb_flush_icache_all) |
64 | ||
1da177e4 LT |
65 | /* |
66 | * flush_user_cache_all() | |
67 | * | |
68 | * Clean and invalidate all cache entries in a particular address | |
69 | * space. | |
70 | */ | |
71 | ENTRY(v4wb_flush_user_cache_all) | |
72 | /* FALLTHROUGH */ | |
73 | /* | |
74 | * flush_kern_cache_all() | |
75 | * | |
76 | * Clean and invalidate the entire cache. | |
77 | */ | |
78 | ENTRY(v4wb_flush_kern_cache_all) | |
79 | mov ip, #0 | |
80 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
81 | __flush_whole_cache: | |
95f3df6b RK |
82 | ldr r3, =flush_base |
83 | ldr r1, [r3, #0] | |
84 | eor r1, r1, #CACHE_DSIZE | |
85 | str r1, [r3, #0] | |
86 | add r2, r1, #CACHE_DSIZE | |
87 | 1: ldr r3, [r1], #32 | |
88 | cmp r1, r2 | |
89 | blo 1b | |
90 | #ifdef FLUSH_BASE_MINICACHE | |
91 | add r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE | |
92 | sub r1, r2, #512 @ only 512 bytes | |
93 | 1: ldr r3, [r1], #32 | |
94 | cmp r1, r2 | |
1da177e4 | 95 | blo 1b |
95f3df6b | 96 | #endif |
1da177e4 | 97 | mcr p15, 0, ip, c7, c10, 4 @ drain write buffer |
6ebbf2ce | 98 | ret lr |
1da177e4 LT |
99 | |
100 | /* | |
101 | * flush_user_cache_range(start, end, flags) | |
102 | * | |
103 | * Invalidate a range of cache entries in the specified | |
104 | * address space. | |
105 | * | |
106 | * - start - start address (inclusive, page aligned) | |
107 | * - end - end address (exclusive, page aligned) | |
108 | * - flags - vma_area_struct flags describing address space | |
109 | */ | |
110 | ENTRY(v4wb_flush_user_cache_range) | |
95f3df6b | 111 | mov ip, #0 |
1da177e4 LT |
112 | sub r3, r1, r0 @ calculate total size |
113 | tst r2, #VM_EXEC @ executable region? | |
114 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
115 | ||
116 | cmp r3, #CACHE_DLIMIT @ total size >= limit? | |
117 | bhs __flush_whole_cache @ flush whole D cache | |
118 | ||
119 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
120 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
121 | add r0, r0, #CACHE_DLINESIZE | |
122 | cmp r0, r1 | |
123 | blo 1b | |
124 | tst r2, #VM_EXEC | |
125 | mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer | |
6ebbf2ce | 126 | ret lr |
1da177e4 LT |
127 | |
128 | /* | |
2c9b9c84 | 129 | * flush_kern_dcache_area(void *addr, size_t size) |
1da177e4 LT |
130 | * |
131 | * Ensure no D cache aliasing occurs, either with itself or | |
132 | * the I cache | |
133 | * | |
2c9b9c84 RK |
134 | * - addr - kernel address |
135 | * - size - region size | |
1da177e4 | 136 | */ |
2c9b9c84 RK |
137 | ENTRY(v4wb_flush_kern_dcache_area) |
138 | add r1, r0, r1 | |
1da177e4 LT |
139 | /* fall through */ |
140 | ||
141 | /* | |
142 | * coherent_kern_range(start, end) | |
143 | * | |
144 | * Ensure coherency between the Icache and the Dcache in the | |
145 | * region described by start. If you have non-snooping | |
146 | * Harvard caches, you need to implement this function. | |
147 | * | |
148 | * - start - virtual start address | |
149 | * - end - virtual end address | |
150 | */ | |
151 | ENTRY(v4wb_coherent_kern_range) | |
152 | /* fall through */ | |
153 | ||
154 | /* | |
155 | * coherent_user_range(start, end) | |
156 | * | |
157 | * Ensure coherency between the Icache and the Dcache in the | |
158 | * region described by start. If you have non-snooping | |
159 | * Harvard caches, you need to implement this function. | |
160 | * | |
161 | * - start - virtual start address | |
162 | * - end - virtual end address | |
163 | */ | |
164 | ENTRY(v4wb_coherent_user_range) | |
165 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
166 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
167 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
168 | add r0, r0, #CACHE_DLINESIZE | |
169 | cmp r0, r1 | |
170 | blo 1b | |
c5102f59 WD |
171 | mov r0, #0 |
172 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
173 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
6ebbf2ce | 174 | ret lr |
1da177e4 LT |
175 | |
176 | ||
177 | /* | |
178 | * dma_inv_range(start, end) | |
179 | * | |
180 | * Invalidate (discard) the specified virtual address range. | |
181 | * May not write back any entries. If 'start' or 'end' | |
182 | * are not cache line aligned, those lines must be written | |
183 | * back. | |
184 | * | |
185 | * - start - virtual start address | |
186 | * - end - virtual end address | |
187 | */ | |
702b94bf | 188 | v4wb_dma_inv_range: |
1da177e4 LT |
189 | tst r0, #CACHE_DLINESIZE - 1 |
190 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
191 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | |
192 | tst r1, #CACHE_DLINESIZE - 1 | |
193 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry | |
194 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
195 | add r0, r0, #CACHE_DLINESIZE | |
196 | cmp r0, r1 | |
197 | blo 1b | |
198 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
6ebbf2ce | 199 | ret lr |
1da177e4 LT |
200 | |
201 | /* | |
202 | * dma_clean_range(start, end) | |
203 | * | |
204 | * Clean (write back) the specified virtual address range. | |
205 | * | |
206 | * - start - virtual start address | |
207 | * - end - virtual end address | |
208 | */ | |
702b94bf | 209 | v4wb_dma_clean_range: |
1da177e4 LT |
210 | bic r0, r0, #CACHE_DLINESIZE - 1 |
211 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
212 | add r0, r0, #CACHE_DLINESIZE | |
213 | cmp r0, r1 | |
214 | blo 1b | |
215 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
6ebbf2ce | 216 | ret lr |
1da177e4 LT |
217 | |
218 | /* | |
219 | * dma_flush_range(start, end) | |
220 | * | |
221 | * Clean and invalidate the specified virtual address range. | |
222 | * | |
223 | * - start - virtual start address | |
224 | * - end - virtual end address | |
225 | * | |
226 | * This is actually the same as v4wb_coherent_kern_range() | |
227 | */ | |
228 | .globl v4wb_dma_flush_range | |
229 | .set v4wb_dma_flush_range, v4wb_coherent_kern_range | |
230 | ||
a9c9147e RK |
231 | /* |
232 | * dma_map_area(start, size, dir) | |
233 | * - start - kernel virtual start address | |
234 | * - size - size of region | |
235 | * - dir - DMA direction | |
236 | */ | |
237 | ENTRY(v4wb_dma_map_area) | |
238 | add r1, r1, r0 | |
239 | cmp r2, #DMA_TO_DEVICE | |
240 | beq v4wb_dma_clean_range | |
241 | bcs v4wb_dma_inv_range | |
242 | b v4wb_dma_flush_range | |
243 | ENDPROC(v4wb_dma_map_area) | |
244 | ||
245 | /* | |
246 | * dma_unmap_area(start, size, dir) | |
247 | * - start - kernel virtual start address | |
248 | * - size - size of region | |
249 | * - dir - DMA direction | |
250 | */ | |
251 | ENTRY(v4wb_dma_unmap_area) | |
6ebbf2ce | 252 | ret lr |
a9c9147e RK |
253 | ENDPROC(v4wb_dma_unmap_area) |
254 | ||
031bd879 LP |
255 | .globl v4wb_flush_kern_cache_louis |
256 | .equ v4wb_flush_kern_cache_louis, v4wb_flush_kern_cache_all | |
257 | ||
1da177e4 LT |
258 | __INITDATA |
259 | ||
eec95e56 DM |
260 | @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) |
261 | define_cache_functions v4wb |