[deliverable/linux.git] / arch / arm / mm / cache-v4wt.S

/*
 *  linux/arch/arm/mm/cache-v4wt.S
 *
 *  Copyright (C) 1997-2002 Russell king
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  ARMv4 write through cache operations support.
 *
 *  We assume that the write buffer is not enabled.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/page.h>
#include "proc-macros.S"

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	8

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintenance instructions.
 *
 * *** This needs benchmarking
 */
#define CACHE_DLIMIT	16384

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(v4wt_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mov	pc, lr
ENDPROC(v4wt_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
ENTRY(v4wt_flush_user_cache_all)
	/* FALLTHROUGH */
/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(v4wt_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start - start address (inclusive, page aligned)
 *	- end	- end address (exclusive, page aligned)
 *	- flags	- vma_area_struct flags describing address space
 */
ENTRY(v4wt_flush_user_cache_range)
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	tst	r2, #VM_EXEC
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4wt_coherent_kern_range)
	/* FALLTRHOUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4wt_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(v4wt_flush_kern_dcache_area)
	mov	r2, #0
	mcr	p15, 0, r2, c7, c5, 0		@ invalidate I cache
	add	r1, r0, r1
	/* fallthrough */

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
v4wt_dma_inv_range:
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
	.globl	v4wt_dma_flush_range
	.equ	v4wt_dma_flush_range, v4wt_dma_inv_range

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(v4wt_dma_unmap_area)
	add	r1, r1, r0
	teq	r2, #DMA_TO_DEVICE
	bne	v4wt_dma_inv_range
	/* FALLTHROUGH */

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(v4wt_dma_map_area)
	mov	pc, lr
ENDPROC(v4wt_dma_unmap_area)
ENDPROC(v4wt_dma_map_area)

	.globl	v4wt_flush_kern_cache_louis
	.equ	v4wt_flush_kern_cache_louis, v4wt_flush_kern_cache_all

	__INITDATA

	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
	define_cache_functions v4wt
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/cache-v4wt.S
	3	*
	4	* Copyright (C) 1997-2002 Russell king
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* ARMv4 write through cache operations support.
	11	*
	12	* We assume that the write buffer is not enabled.
	13	*/
	14	#include <linux/linkage.h>
	15	#include <linux/init.h>
1da177e4 LT	16	#include <asm/page.h>
	17	#include "proc-macros.S"
	18
	19	/*
	20	* The size of one data cache line.
	21	*/
	22	#define CACHE_DLINESIZE 32
	23
	24	/*
	25	* The number of data cache segments.
	26	*/
	27	#define CACHE_DSEGMENTS 8
	28
	29	/*
	30	* The number of lines in a cache segment.
	31	*/
	32	#define CACHE_DENTRIES 64
	33
	34	/*
	35	* This is the size at which it becomes more efficient to
	36	* clean the whole cache, rather than using the individual
25985edc	37	* cache line maintenance instructions.
1da177e4 LT	38	*
	39	* *** This needs benchmarking
	40	*/
	41	#define CACHE_DLIMIT 16384
	42
c8c90860 MW	43	/*
	44	* flush_icache_all()
	45	*
	46	* Unconditionally clean and invalidate the entire icache.
	47	*/
	48	ENTRY(v4wt_flush_icache_all)
	49	mov r0, #0
	50	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	51	mov pc, lr
	52	ENDPROC(v4wt_flush_icache_all)
	53
1da177e4 LT	54	/*
	55	* flush_user_cache_all()
	56	*
	57	* Invalidate all cache entries in a particular address
	58	* space.
	59	*/
	60	ENTRY(v4wt_flush_user_cache_all)
	61	/* FALLTHROUGH */
	62	/*
	63	* flush_kern_cache_all()
	64	*
	65	* Clean and invalidate the entire cache.
	66	*/
	67	ENTRY(v4wt_flush_kern_cache_all)
	68	mov r2, #VM_EXEC
	69	mov ip, #0
	70	__flush_whole_cache:
	71	tst r2, #VM_EXEC
	72	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	73	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	74	mov pc, lr
	75
	76	/*
	77	* flush_user_cache_range(start, end, flags)
	78	*
	79	* Clean and invalidate a range of cache entries in the specified
	80	* address space.
	81	*
	82	* - start - start address (inclusive, page aligned)
	83	* - end - end address (exclusive, page aligned)
	84	* - flags - vma_area_struct flags describing address space
	85	*/
	86	ENTRY(v4wt_flush_user_cache_range)
	87	sub r3, r1, r0 @ calculate total size
	88	cmp r3, #CACHE_DLIMIT
	89	bhs __flush_whole_cache
	90
	91	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	92	tst r2, #VM_EXEC
	93	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	94	add r0, r0, #CACHE_DLINESIZE
	95	cmp r0, r1
	96	blo 1b
	97	mov pc, lr
	98
	99	/*
	100	* coherent_kern_range(start, end)
	101	*
	102	* Ensure coherency between the Icache and the Dcache in the
	103	* region described by start. If you have non-snooping
	104	* Harvard caches, you need to implement this function.
	105	*
	106	* - start - virtual start address
	107	* - end - virtual end address
	108	*/
	109	ENTRY(v4wt_coherent_kern_range)
	110	/* FALLTRHOUGH */
	111
	112	/*
	113	* coherent_user_range(start, end)
	114	*
	115	* Ensure coherency between the Icache and the Dcache in the
	116	* region described by start. If you have non-snooping
	117	* Harvard caches, you need to implement this function.
118	*
119	* - start - virtual start address
120	* - end - virtual end address
121	*/
122	ENTRY(v4wt_coherent_user_range)
123	bic r0, r0, #CACHE_DLINESIZE - 1
124	1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
125	add r0, r0, #CACHE_DLINESIZE
126	cmp r0, r1
127	blo 1b
c5102f59	128	mov r0, #0
1da177e4 LT	129	mov pc, lr
	130
	131	/*
2c9b9c84	132	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	133	*
	134	* Ensure no D cache aliasing occurs, either with itself or
	135	* the I cache
	136	*
2c9b9c84 RK	137	* - addr - kernel address
2c9b9c84 RK	138	* - size - region size
1da177e4	139	*/
2c9b9c84	140	ENTRY(v4wt_flush_kern_dcache_area)
1da177e4 LT	141	mov r2, #0
1da177e4 LT	142	mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
2c9b9c84	143	add r1, r0, r1
1da177e4 LT	144	/* fallthrough */
	145
	146	/*
	147	* dma_inv_range(start, end)
	148	*
	149	* Invalidate (discard) the specified virtual address range.
	150	* May not write back any entries. If 'start' or 'end'
	151	* are not cache line aligned, those lines must be written
	152	* back.
	153	*
	154	* - start - virtual start address
	155	* - end - virtual end address
	156	*/
702b94bf	157	v4wt_dma_inv_range:
1da177e4 LT	158	bic r0, r0, #CACHE_DLINESIZE - 1
	159	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	160	add r0, r0, #CACHE_DLINESIZE
	161	cmp r0, r1
	162	blo 1b
1da177e4 LT	163	mov pc, lr
	164
	165	/*
	166	* dma_flush_range(start, end)
	167	*
	168	* Clean and invalidate the specified virtual address range.
	169	*
	170	* - start - virtual start address
	171	* - end - virtual end address
	172	*/
	173	.globl v4wt_dma_flush_range
	174	.equ v4wt_dma_flush_range, v4wt_dma_inv_range
	175
a9c9147e RK	176	/*
	177	* dma_unmap_area(start, size, dir)
	178	* - start - kernel virtual start address
	179	* - size - size of region
	180	* - dir - DMA direction
	181	*/
	182	ENTRY(v4wt_dma_unmap_area)
	183	add r1, r1, r0
	184	teq r2, #DMA_TO_DEVICE
	185	bne v4wt_dma_inv_range
	186	/* FALLTHROUGH */
	187
	188	/*
	189	* dma_map_area(start, size, dir)
	190	* - start - kernel virtual start address
	191	* - size - size of region
	192	* - dir - DMA direction
	193	*/
	194	ENTRY(v4wt_dma_map_area)
	195	mov pc, lr
	196	ENDPROC(v4wt_dma_unmap_area)
	197	ENDPROC(v4wt_dma_map_area)
	198
031bd879 LP	199	.globl v4wt_flush_kern_cache_louis
	200	.equ v4wt_flush_kern_cache_louis, v4wt_flush_kern_cache_all
	201
1da177e4 LT	202	__INITDATA
1da177e4 LT	203
d5b5b2e2 DM	204	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
d5b5b2e2 DM	205	define_cache_functions v4wt