[deliverable/linux.git] / arch / arm / mm / cache-v7.S

/*
 *  linux/arch/arm/mm/cache-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *  Copyright (C) 2005 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/unwind.h>

#include "proc-macros.S"

/*
 *	v7_flush_dcache_all()
 *
 *	Flush the whole D-cache.
 *
 *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
 *
 *	- mm    - mm_struct describing address space
 */
ENTRY(v7_flush_dcache_all)
	dmb					@ ensure ordering with previous memory accesses
	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
	ands	r3, r0, #0x7000000		@ extract loc from clidr
	mov	r3, r3, lsr #23			@ left align loc bit field
	beq	finished			@ if loc is 0, then no need to clean
	mov	r10, #0				@ start clean at cache level 0
loop1:
	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
	and	r1, r1, #7			@ mask of the bits for current cache only
	cmp	r1, #2				@ see what cache we have at this level
	blt	skip				@ skip if no cache, or just i-cache
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
	isb					@ isb to sych the new cssr&csidr
	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
	and	r2, r1, #7			@ extract the length of the cache lines
	add	r2, r2, #4			@ add 4 (line length offset)
	ldr	r4, =0x3ff
	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
	clz	r5, r4				@ find bit position of way size increment
	ldr	r7, =0x7fff
	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
loop2:
	mov	r9, r4				@ create working copy of max way size
loop3:
 ARM(	orr	r11, r10, r9, lsl r5	)	@ factor way and cache number into r11
 THUMB(	lsl	r6, r9, r5		)
 THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
 ARM(	orr	r11, r11, r7, lsl r2	)	@ factor index number into r11
 THUMB(	lsl	r6, r7, r2		)
 THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
	subs	r9, r9, #1			@ decrement the way
	bge	loop3
	subs	r7, r7, #1			@ decrement the index
	bge	loop2
skip:
	add	r10, r10, #2			@ increment cache number
	cmp	r3, r10
	bgt	loop1
finished:
	mov	r10, #0				@ swith back to cache level 0
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
	dsb
	isb
	mov	pc, lr
ENDPROC(v7_flush_dcache_all)

/*
 *	v7_flush_cache_all()
 *
 *	Flush the entire cache system.
 *  The data cache flush is now achieved using atomic clean / invalidates
 *  working outwards from L1 cache. This is done using Set/Way based cache
 *  maintainance instructions.
 *  The instruction cache can still be invalidated back to the point of
 *  unification in a single instruction.
 *
 */
ENTRY(v7_flush_kern_cache_all)
 ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
 THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
	bl	v7_flush_dcache_all
	mov	r0, #0
#ifdef CONFIG_SMP
	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
#else
	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
#endif
 ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
 THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
	mov	pc, lr
ENDPROC(v7_flush_kern_cache_all)

/*
 *	v7_flush_cache_all()
 *
 *	Flush all TLB entries in a particular address space
 *
 *	- mm    - mm_struct describing address space
 */
ENTRY(v7_flush_user_cache_all)
	/*FALLTHROUGH*/

/*
 *	v7_flush_cache_range(start, end, flags)
 *
 *	Flush a range of TLB entries in the specified address space.
 *
 *	- start - start address (may not be aligned)
 *	- end   - end address (exclusive, may not be aligned)
 *	- flags	- vm_area_struct flags describing address space
 *
 *	It is assumed that:
 *	- we have a VIPT cache.
 */
ENTRY(v7_flush_user_cache_range)
	mov	pc, lr
ENDPROC(v7_flush_user_cache_all)
ENDPROC(v7_flush_user_cache_range)

/*
 *	v7_coherent_kern_range(start,end)
 *
 *	Ensure that the I and D caches are coherent within specified
 *	region.  This is typically used when code has been written to
 *	a memory region, and will be executed.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 *
 *	It is assumed that:
 *	- the Icache does not read data from the write buffer
 */
ENTRY(v7_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	v7_coherent_user_range(start,end)
 *
 *	Ensure that the I and D caches are coherent within specified
 *	region.  This is typically used when code has been written to
 *	a memory region, and will be executed.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 *
 *	It is assumed that:
 *	- the Icache does not read data from the write buffer
 */
ENTRY(v7_coherent_user_range)
 UNWIND(.fnstart		)
	dcache_line_size r2, r3
	sub	r3, r2, #1
	bic	r0, r0, r3
1:
 USER(	mcr	p15, 0, r0, c7, c11, 1	)	@ clean D line to the point of unification
	dsb
 USER(	mcr	p15, 0, r0, c7, c5, 1	)	@ invalidate I line
	add	r0, r0, r2
2:
	cmp	r0, r1
	blo	1b
	mov	r0, #0
#ifdef CONFIG_SMP
	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
#else
	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
#endif
	dsb
	isb
	mov	pc, lr

/*
 * Fault handling for the cache operation above. If the virtual address in r0
 * isn't mapped, just try the next page.
 */
9001:
	mov	r0, r0, lsr #12
	mov	r0, r0, lsl #12
	add	r0, r0, #4096
	b	2b
 UNWIND(.fnend		)
ENDPROC(v7_coherent_kern_range)
ENDPROC(v7_coherent_user_range)

/*
 *	v7_flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure that the data held in the page kaddr is written back
 *	to the page in question.
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(v7_flush_kern_dcache_area)
	dcache_line_size r2, r3
	add	r1, r0, r1
1:
	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line / unified line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_flush_kern_dcache_area)

/*
 *	v7_dma_inv_range(start,end)
 *
 *	Invalidate the data cache within the specified region; we will
 *	be performing a DMA operation in this region and we want to
 *	purge old data in the cache.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
v7_dma_inv_range:
	dcache_line_size r2, r3
	sub	r3, r2, #1
	tst	r0, r3
	bic	r0, r0, r3
	mcrne	p15, 0, r0, c7, c14, 1		@ clean & invalidate D / U line

	tst	r1, r3
	bic	r1, r1, r3
	mcrne	p15, 0, r1, c7, c14, 1		@ clean & invalidate D / U line
1:
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D / U line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_dma_inv_range)

/*
 *	v7_dma_clean_range(start,end)
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
v7_dma_clean_range:
	dcache_line_size r2, r3
	sub	r3, r2, #1
	bic	r0, r0, r3
1:
	mcr	p15, 0, r0, c7, c10, 1		@ clean D / U line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_dma_clean_range)

/*
 *	v7_dma_flush_range(start,end)
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
ENTRY(v7_dma_flush_range)
	dcache_line_size r2, r3
	sub	r3, r2, #1
	bic	r0, r0, r3
1:
	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D / U line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_dma_flush_range)

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(v7_dma_map_area)
	add	r1, r1, r0
	teq	r2, #DMA_FROM_DEVICE
	beq	v7_dma_inv_range
	b	v7_dma_clean_range
ENDPROC(v7_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(v7_dma_unmap_area)
	add	r1, r1, r0
	teq	r2, #DMA_TO_DEVICE
	bne	v7_dma_inv_range
	mov	pc, lr
ENDPROC(v7_dma_unmap_area)

	__INITDATA

	.type	v7_cache_fns, #object
ENTRY(v7_cache_fns)
	.long	v7_flush_kern_cache_all
	.long	v7_flush_user_cache_all
	.long	v7_flush_user_cache_range
	.long	v7_coherent_kern_range
	.long	v7_coherent_user_range
	.long	v7_flush_kern_dcache_area
	.long	v7_dma_map_area
	.long	v7_dma_unmap_area
	.long	v7_dma_flush_range
	.size	v7_cache_fns, . - v7_cache_fns
Commit	Line	Data
bbe88886 CM	1	/*
	2	* linux/arch/arm/mm/cache-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	* Copyright (C) 2005 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This is the "shell" of the ARMv7 processor support.
	12	*/
	13	#include <linux/linkage.h>
	14	#include <linux/init.h>
	15	#include <asm/assembler.h>
32cfb1b1	16	#include <asm/unwind.h>
bbe88886 CM	17
	18	#include "proc-macros.S"
	19
	20	/*
	21	* v7_flush_dcache_all()
	22	*
	23	* Flush the whole D-cache.
	24	*
347c8b70	25	* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
bbe88886 CM	26	*
	27	* - mm - mm_struct describing address space
	28	*/
	29	ENTRY(v7_flush_dcache_all)
c30c2f99	30	dmb @ ensure ordering with previous memory accesses
bbe88886 CM	31	mrc p15, 1, r0, c0, c0, 1 @ read clidr
	32	ands r3, r0, #0x7000000 @ extract loc from clidr
	33	mov r3, r3, lsr #23 @ left align loc bit field
	34	beq finished @ if loc is 0, then no need to clean
	35	mov r10, #0 @ start clean at cache level 0
	36	loop1:
	37	add r2, r10, r10, lsr #1 @ work out 3x current cache level
	38	mov r1, r0, lsr r2 @ extract cache type bits from clidr
	39	and r1, r1, #7 @ mask of the bits for current cache only
	40	cmp r1, #2 @ see what cache we have at this level
	41	blt skip @ skip if no cache, or just i-cache
	42	mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
	43	isb @ isb to sych the new cssr&csidr
	44	mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
	45	and r2, r1, #7 @ extract the length of the cache lines
	46	add r2, r2, #4 @ add 4 (line length offset)
	47	ldr r4, =0x3ff
	48	ands r4, r4, r1, lsr #3 @ find maximum number on the way size
	49	clz r5, r4 @ find bit position of way size increment
	50	ldr r7, =0x7fff
	51	ands r7, r7, r1, lsr #13 @ extract max number of the index size
	52	loop2:
	53	mov r9, r4 @ create working copy of max way size
	54	loop3:
347c8b70 CM	55	ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
	56	THUMB( lsl r6, r9, r5 )
	57	THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
	58	ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
	59	THUMB( lsl r6, r7, r2 )
	60	THUMB( orr r11, r11, r6 ) @ factor index number into r11
bbe88886 CM	61	mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
	62	subs r9, r9, #1 @ decrement the way
	63	bge loop3
	64	subs r7, r7, #1 @ decrement the index
	65	bge loop2
	66	skip:
	67	add r10, r10, #2 @ increment cache number
	68	cmp r3, r10
	69	bgt loop1
	70	finished:
	71	mov r10, #0 @ swith back to cache level 0
	72	mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
c30c2f99	73	dsb
bbe88886 CM	74	isb
bbe88886 CM	75	mov pc, lr
93ed3970	76	ENDPROC(v7_flush_dcache_all)
bbe88886 CM	77
	78	/*
	79	* v7_flush_cache_all()
	80	*
	81	* Flush the entire cache system.
	82	* The data cache flush is now achieved using atomic clean / invalidates
	83	* working outwards from L1 cache. This is done using Set/Way based cache
	84	* maintainance instructions.
	85	* The instruction cache can still be invalidated back to the point of
	86	* unification in a single instruction.
	87	*
	88	*/
	89	ENTRY(v7_flush_kern_cache_all)
347c8b70 CM	90	ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
347c8b70 CM	91	THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
bbe88886 CM	92	bl v7_flush_dcache_all
bbe88886 CM	93	mov r0, #0
a901ff71 SS	94	#ifdef CONFIG_SMP
	95	mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable
	96	#else
bbe88886	97	mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
a901ff71	98	#endif
347c8b70 CM	99	ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
347c8b70 CM	100	THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
bbe88886	101	mov pc, lr
93ed3970	102	ENDPROC(v7_flush_kern_cache_all)
bbe88886 CM	103
	104	/*
	105	* v7_flush_cache_all()
	106	*
	107	* Flush all TLB entries in a particular address space
	108	*
	109	* - mm - mm_struct describing address space
	110	*/
	111	ENTRY(v7_flush_user_cache_all)
	112	/FALLTHROUGH/
	113
	114	/*
	115	* v7_flush_cache_range(start, end, flags)
	116	*
	117	* Flush a range of TLB entries in the specified address space.
	118	*
	119	* - start - start address (may not be aligned)
	120	* - end - end address (exclusive, may not be aligned)
	121	* - flags - vm_area_struct flags describing address space
	122	*
	123	* It is assumed that:
	124	* - we have a VIPT cache.
	125	*/
	126	ENTRY(v7_flush_user_cache_range)
	127	mov pc, lr
93ed3970 CM	128	ENDPROC(v7_flush_user_cache_all)
93ed3970 CM	129	ENDPROC(v7_flush_user_cache_range)
bbe88886 CM	130
	131	/*
	132	* v7_coherent_kern_range(start,end)
	133	*
	134	* Ensure that the I and D caches are coherent within specified
	135	* region. This is typically used when code has been written to
	136	* a memory region, and will be executed.
	137	*
	138	* - start - virtual start address of region
	139	* - end - virtual end address of region
	140	*
	141	* It is assumed that:
	142	* - the Icache does not read data from the write buffer
	143	*/
	144	ENTRY(v7_coherent_kern_range)
	145	/* FALLTHROUGH */
	146
	147	/*
	148	* v7_coherent_user_range(start,end)
	149	*
	150	* Ensure that the I and D caches are coherent within specified
	151	* region. This is typically used when code has been written to
	152	* a memory region, and will be executed.
	153	*
	154	* - start - virtual start address of region
	155	* - end - virtual end address of region
	156	*
	157	* It is assumed that:
	158	* - the Icache does not read data from the write buffer
	159	*/
	160	ENTRY(v7_coherent_user_range)
32cfb1b1	161	UNWIND(.fnstart )
bbe88886 CM	162	dcache_line_size r2, r3
	163	sub r3, r2, #1
	164	bic r0, r0, r3
32cfb1b1 CM	165	1:
32cfb1b1 CM	166	USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification
bbe88886	167	dsb
32cfb1b1	168	USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line
bbe88886	169	add r0, r0, r2
32cfb1b1	170	2:
bbe88886 CM	171	cmp r0, r1
	172	blo 1b
	173	mov r0, #0
b8349b56 CM	174	#ifdef CONFIG_SMP
	175	mcr p15, 0, r0, c7, c1, 6 @ invalidate BTB Inner Shareable
	176	#else
bbe88886	177	mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
b8349b56	178	#endif
bbe88886 CM	179	dsb
	180	isb
	181	mov pc, lr
32cfb1b1 CM	182
	183	/*
	184	* Fault handling for the cache operation above. If the virtual address in r0
	185	* isn't mapped, just try the next page.
	186	*/
	187	9001:
	188	mov r0, r0, lsr #12
	189	mov r0, r0, lsl #12
	190	add r0, r0, #4096
	191	b 2b
	192	UNWIND(.fnend )
93ed3970 CM	193	ENDPROC(v7_coherent_kern_range)
93ed3970 CM	194	ENDPROC(v7_coherent_user_range)
bbe88886 CM	195
bbe88886 CM	196	/*
2c9b9c84	197	* v7_flush_kern_dcache_area(void *addr, size_t size)
bbe88886 CM	198	*
	199	* Ensure that the data held in the page kaddr is written back
	200	* to the page in question.
	201	*
2c9b9c84 RK	202	* - addr - kernel address
2c9b9c84 RK	203	* - size - region size
bbe88886	204	*/
2c9b9c84	205	ENTRY(v7_flush_kern_dcache_area)
bbe88886	206	dcache_line_size r2, r3
2c9b9c84	207	add r1, r0, r1
bbe88886 CM	208	1:
	209	mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
	210	add r0, r0, r2
	211	cmp r0, r1
	212	blo 1b
	213	dsb
	214	mov pc, lr
2c9b9c84	215	ENDPROC(v7_flush_kern_dcache_area)
bbe88886 CM	216
	217	/*
	218	* v7_dma_inv_range(start,end)
	219	*
	220	* Invalidate the data cache within the specified region; we will
	221	* be performing a DMA operation in this region and we want to
	222	* purge old data in the cache.
	223	*
	224	* - start - virtual start address of region
	225	* - end - virtual end address of region
	226	*/
702b94bf	227	v7_dma_inv_range:
bbe88886 CM	228	dcache_line_size r2, r3
	229	sub r3, r2, #1
	230	tst r0, r3
	231	bic r0, r0, r3
	232	mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
	233
	234	tst r1, r3
	235	bic r1, r1, r3
	236	mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
	237	1:
	238	mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line
	239	add r0, r0, r2
	240	cmp r0, r1
	241	blo 1b
	242	dsb
	243	mov pc, lr
93ed3970	244	ENDPROC(v7_dma_inv_range)
bbe88886 CM	245
	246	/*
	247	* v7_dma_clean_range(start,end)
	248	* - start - virtual start address of region
	249	* - end - virtual end address of region
	250	*/
702b94bf	251	v7_dma_clean_range:
bbe88886 CM	252	dcache_line_size r2, r3
	253	sub r3, r2, #1
	254	bic r0, r0, r3
	255	1:
	256	mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
	257	add r0, r0, r2
	258	cmp r0, r1
	259	blo 1b
	260	dsb
	261	mov pc, lr
93ed3970	262	ENDPROC(v7_dma_clean_range)
bbe88886 CM	263
	264	/*
	265	* v7_dma_flush_range(start,end)
	266	* - start - virtual start address of region
	267	* - end - virtual end address of region
	268	*/
	269	ENTRY(v7_dma_flush_range)
	270	dcache_line_size r2, r3
	271	sub r3, r2, #1
	272	bic r0, r0, r3
	273	1:
	274	mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
	275	add r0, r0, r2
	276	cmp r0, r1
	277	blo 1b
	278	dsb
	279	mov pc, lr
93ed3970	280	ENDPROC(v7_dma_flush_range)
bbe88886	281
a9c9147e RK	282	/*
	283	* dma_map_area(start, size, dir)
	284	* - start - kernel virtual start address
	285	* - size - size of region
	286	* - dir - DMA direction
	287	*/
	288	ENTRY(v7_dma_map_area)
	289	add r1, r1, r0
2ffe2da3 RK	290	teq r2, #DMA_FROM_DEVICE
	291	beq v7_dma_inv_range
	292	b v7_dma_clean_range
a9c9147e RK	293	ENDPROC(v7_dma_map_area)
	294
	295	/*
	296	* dma_unmap_area(start, size, dir)
	297	* - start - kernel virtual start address
	298	* - size - size of region
	299	* - dir - DMA direction
	300	*/
	301	ENTRY(v7_dma_unmap_area)
2ffe2da3 RK	302	add r1, r1, r0
	303	teq r2, #DMA_TO_DEVICE
	304	bne v7_dma_inv_range
a9c9147e RK	305	mov pc, lr
	306	ENDPROC(v7_dma_unmap_area)
	307
bbe88886 CM	308	__INITDATA
	309
	310	.type v7_cache_fns, #object
	311	ENTRY(v7_cache_fns)
	312	.long v7_flush_kern_cache_all
	313	.long v7_flush_user_cache_all
	314	.long v7_flush_user_cache_range
	315	.long v7_coherent_kern_range
	316	.long v7_coherent_user_range
2c9b9c84	317	.long v7_flush_kern_dcache_area
a9c9147e RK	318	.long v7_dma_map_area
a9c9147e RK	319	.long v7_dma_unmap_area
bbe88886 CM	320	.long v7_dma_flush_range
bbe88886 CM	321	.size v7_cache_fns, . - v7_cache_fns