[deliverable/linux.git] / arch / arm / mm / copypage-xscale.c

/*
 *  linux/arch/arm/lib/copypage-xscale.S
 *
 *  Copyright (C) 1995-2005 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This handles the mini data cache, as found on SA11x0 and XScale
 * processors.  When we copy a user page page, we map it in such a way
 * that accesses to this page will not touch the main data cache, but
 * will be cached in the mini data cache.  This prevents us thrashing
 * the main data cache on page faults.
 */
#include <linux/init.h>
#include <linux/mm.h>

#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>

#include "mm.h"

/*
 * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
 * specific hacks for copying pages efficiently.
 */
#define COPYPAGE_MINICACHE	0xffff8000

#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
				  L_PTE_CACHEABLE)

static DEFINE_SPINLOCK(minicache_lock);

/*
 * XScale mini-dcache optimised copy_user_page
 *
 * We flush the destination cache lines just before we write the data into the
 * corresponding address.  Since the Dcache is read-allocate, this removes the
 * Dcache aliasing issue.  The writes will be forwarded to the write buffer,
 * and merged as appropriate.
 */
static void __attribute__((naked))
mc_copy_user_page(void *from, void *to)
{
	/*
	 * Strangely enough, best performance is achieved
	 * when prefetching destination as well.  (NP)
	 */
	asm volatile(
	"stmfd	sp!, {r4, r5, lr}		\n\
	mov	lr, %2				\n\
	pld	[r0, #0]			\n\
	pld	[r0, #32]			\n\
	pld	[r1, #0]			\n\
	pld	[r1, #32]			\n\
1:	pld	[r0, #64]			\n\
	pld	[r0, #96]			\n\
	pld	[r1, #64]			\n\
	pld	[r1, #96]			\n\
2:	ldrd	r2, [r0], #8			\n\
	ldrd	r4, [r0], #8			\n\
	mov	ip, r1				\n\
	strd	r2, [r1], #8			\n\
	ldrd	r2, [r0], #8			\n\
	strd	r4, [r1], #8			\n\
	ldrd	r4, [r0], #8			\n\
	strd	r2, [r1], #8			\n\
	strd	r4, [r1], #8			\n\
	mcr	p15, 0, ip, c7, c10, 1		@ clean D line\n\
	ldrd	r2, [r0], #8			\n\
	mcr	p15, 0, ip, c7, c6, 1		@ invalidate D line\n\
	ldrd	r4, [r0], #8			\n\
	mov	ip, r1				\n\
	strd	r2, [r1], #8			\n\
	ldrd	r2, [r0], #8			\n\
	strd	r4, [r1], #8			\n\
	ldrd	r4, [r0], #8			\n\
	strd	r2, [r1], #8			\n\
	strd	r4, [r1], #8			\n\
	mcr	p15, 0, ip, c7, c10, 1		@ clean D line\n\
	subs	lr, lr, #1			\n\
	mcr	p15, 0, ip, c7, c6, 1		@ invalidate D line\n\
	bgt	1b				\n\
	beq	2b				\n\
	ldmfd	sp!, {r4, r5, pc}		"
	:
	: "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1));
}

void xscale_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
{
	struct page *page = virt_to_page(kfrom);

	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
		__flush_dcache_page(page_mapping(page), page);

	spin_lock(&minicache_lock);

	set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0);
	flush_tlb_kernel_page(COPYPAGE_MINICACHE);

	mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);

	spin_unlock(&minicache_lock);
}

/*
 * XScale optimised clear_user_page
 */
void __attribute__((naked))
xscale_mc_clear_user_page(void *kaddr, unsigned long vaddr)
{
	asm volatile(
	"mov	r1, %0				\n\
	mov	r2, #0				\n\
	mov	r3, #0				\n\
1:	mov	ip, r0				\n\
	strd	r2, [r0], #8			\n\
	strd	r2, [r0], #8			\n\
	strd	r2, [r0], #8			\n\
	strd	r2, [r0], #8			\n\
	mcr	p15, 0, ip, c7, c10, 1		@ clean D line\n\
	subs	r1, r1, #1			\n\
	mcr	p15, 0, ip, c7, c6, 1		@ invalidate D line\n\
	bne	1b				\n\
	mov	pc, lr"
	:
	: "I" (PAGE_SIZE / 32));
}

struct cpu_user_fns xscale_mc_user_fns __initdata = {
	.cpu_clear_user_page	= xscale_mc_clear_user_page, 
	.cpu_copy_user_page	= xscale_mc_copy_user_page,
};
Commit	Line	Data
f8f98a93 RK	1	/*
	2	* linux/arch/arm/lib/copypage-xscale.S
	3	*
	4	* Copyright (C) 1995-2005 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This handles the mini data cache, as found on SA11x0 and XScale
	11	* processors. When we copy a user page page, we map it in such a way
	12	* that accesses to this page will not touch the main data cache, but
	13	* will be cached in the mini data cache. This prevents us thrashing
	14	* the main data cache on page faults.
	15	*/
	16	#include <linux/init.h>
	17	#include <linux/mm.h>
	18
	19	#include <asm/page.h>
	20	#include <asm/pgtable.h>
	21	#include <asm/tlbflush.h>
1c9d3df5	22	#include <asm/cacheflush.h>
f8f98a93	23
1b2e2b73 RK	24	#include "mm.h"
1b2e2b73 RK	25
f8f98a93 RK	26	/*
	27	* 0xffff8000 to 0xffffffff is reserved for any ARM architecture
	28	* specific hacks for copying pages efficiently.
	29	*/
	30	#define COPYPAGE_MINICACHE 0xffff8000
	31
	32	#define minicache_pgprot __pgprot(L_PTE_PRESENT \| L_PTE_YOUNG \| \
	33	L_PTE_CACHEABLE)
	34
f8f98a93 RK	35	static DEFINE_SPINLOCK(minicache_lock);
	36
	37	/*
	38	* XScale mini-dcache optimised copy_user_page
	39	*
	40	* We flush the destination cache lines just before we write the data into the
	41	* corresponding address. Since the Dcache is read-allocate, this removes the
	42	* Dcache aliasing issue. The writes will be forwarded to the write buffer,
	43	* and merged as appropriate.
	44	*/
	45	static void __attribute__((naked))
	46	mc_copy_user_page(void from, void to)
	47	{
	48	/*
	49	* Strangely enough, best performance is achieved
	50	* when prefetching destination as well. (NP)
	51	*/
	52	asm volatile(
	53	"stmfd sp!, {r4, r5, lr} \n\
	54	mov lr, %2 \n\
	55	pld [r0, #0] \n\
	56	pld [r0, #32] \n\
	57	pld [r1, #0] \n\
	58	pld [r1, #32] \n\
	59	1: pld [r0, #64] \n\
	60	pld [r0, #96] \n\
	61	pld [r1, #64] \n\
	62	pld [r1, #96] \n\
	63	2: ldrd r2, [r0], #8 \n\
	64	ldrd r4, [r0], #8 \n\
	65	mov ip, r1 \n\
	66	strd r2, [r1], #8 \n\
	67	ldrd r2, [r0], #8 \n\
	68	strd r4, [r1], #8 \n\
	69	ldrd r4, [r0], #8 \n\
	70	strd r2, [r1], #8 \n\
	71	strd r4, [r1], #8 \n\
	72	mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
	73	ldrd r2, [r0], #8 \n\
	74	mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
	75	ldrd r4, [r0], #8 \n\
	76	mov ip, r1 \n\
	77	strd r2, [r1], #8 \n\
	78	ldrd r2, [r0], #8 \n\
	79	strd r4, [r1], #8 \n\
	80	ldrd r4, [r0], #8 \n\
	81	strd r2, [r1], #8 \n\
	82	strd r4, [r1], #8 \n\
	83	mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
	84	subs lr, lr, #1 \n\
	85	mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
	86	bgt 1b \n\
	87	beq 2b \n\
	88	ldmfd sp!, {r4, r5, pc} "
	89	:
	90	: "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1));
	91	}
	92
	93	void xscale_mc_copy_user_page(void kto, const void kfrom, unsigned long vaddr)
	94	{
1c9d3df5 RP	95	struct page *page = virt_to_page(kfrom);
	96
	97	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
	98	__flush_dcache_page(page_mapping(page), page);
	99
f8f98a93 RK	100	spin_lock(&minicache_lock);
f8f98a93 RK	101
ad1ae2fe	102	set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0);
f8f98a93 RK	103	flush_tlb_kernel_page(COPYPAGE_MINICACHE);
	104
	105	mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
	106
	107	spin_unlock(&minicache_lock);
	108	}
	109
	110	/*
	111	* XScale optimised clear_user_page
	112	*/
	113	void __attribute__((naked))
	114	xscale_mc_clear_user_page(void *kaddr, unsigned long vaddr)
	115	{
	116	asm volatile(
	117	"mov r1, %0 \n\
	118	mov r2, #0 \n\
	119	mov r3, #0 \n\
	120	1: mov ip, r0 \n\
	121	strd r2, [r0], #8 \n\
	122	strd r2, [r0], #8 \n\
	123	strd r2, [r0], #8 \n\
	124	strd r2, [r0], #8 \n\
	125	mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
	126	subs r1, r1, #1 \n\
	127	mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
	128	bne 1b \n\
	129	mov pc, lr"
	130	:
	131	: "I" (PAGE_SIZE / 32));
	132	}
	133
	134	struct cpu_user_fns xscale_mc_user_fns __initdata = {
	135	.cpu_clear_user_page = xscale_mc_clear_user_page,
	136	.cpu_copy_user_page = xscale_mc_copy_user_page,
	137	};