Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
11a5aa32 | 12 | #include <linux/bootmem.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/mm.h> | |
36d0fd21 | 15 | #include <linux/genalloc.h> |
5a0e3ad6 | 16 | #include <linux/gfp.h> |
1da177e4 LT |
17 | #include <linux/errno.h> |
18 | #include <linux/list.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/dma-mapping.h> | |
c7909509 | 22 | #include <linux/dma-contiguous.h> |
39af22a7 | 23 | #include <linux/highmem.h> |
c7909509 | 24 | #include <linux/memblock.h> |
99d1717d | 25 | #include <linux/slab.h> |
4ce63fcd | 26 | #include <linux/iommu.h> |
e9da6e99 | 27 | #include <linux/io.h> |
4ce63fcd | 28 | #include <linux/vmalloc.h> |
158e8bfe | 29 | #include <linux/sizes.h> |
a254129e | 30 | #include <linux/cma.h> |
1da177e4 | 31 | |
23759dc6 | 32 | #include <asm/memory.h> |
43377453 | 33 | #include <asm/highmem.h> |
1da177e4 | 34 | #include <asm/cacheflush.h> |
1da177e4 | 35 | #include <asm/tlbflush.h> |
99d1717d | 36 | #include <asm/mach/arch.h> |
4ce63fcd | 37 | #include <asm/dma-iommu.h> |
c7909509 MS |
38 | #include <asm/mach/map.h> |
39 | #include <asm/system_info.h> | |
40 | #include <asm/dma-contiguous.h> | |
37134cd5 | 41 | |
1234e3fd | 42 | #include "dma.h" |
022ae537 RK |
43 | #include "mm.h" |
44 | ||
15237e1f MS |
45 | /* |
46 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
47 | * is either exclusively owned by the CPU (and therefore may be accessed | |
48 | * by it) or exclusively owned by the DMA device. These helper functions | |
49 | * represent the transitions between these two ownership states. | |
50 | * | |
51 | * Note, however, that on later ARMs, this notion does not work due to | |
52 | * speculative prefetches. We model our approach on the assumption that | |
53 | * the CPU does do speculative prefetches, which means we clean caches | |
54 | * before transfers and delay cache invalidation until transfer completion. | |
55 | * | |
15237e1f | 56 | */ |
51fde349 | 57 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 58 | size_t, enum dma_data_direction); |
51fde349 | 59 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
60 | size_t, enum dma_data_direction); |
61 | ||
2dc6a016 MS |
62 | /** |
63 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
64 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
65 | * @page: page that buffer resides in | |
66 | * @offset: offset into page for start of buffer | |
67 | * @size: size of buffer to map | |
68 | * @dir: DMA transfer direction | |
69 | * | |
70 | * Ensure that any data held in the cache is appropriately discarded | |
71 | * or written back. | |
72 | * | |
73 | * The device owns this memory once this call has completed. The CPU | |
74 | * can regain ownership by calling dma_unmap_page(). | |
75 | */ | |
51fde349 | 76 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
77 | unsigned long offset, size_t size, enum dma_data_direction dir, |
78 | struct dma_attrs *attrs) | |
79 | { | |
dd37e940 | 80 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
81 | __dma_page_cpu_to_dev(page, offset, size, dir); |
82 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
83 | } |
84 | ||
dd37e940 RH |
85 | static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page, |
86 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
87 | struct dma_attrs *attrs) | |
88 | { | |
89 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
90 | } | |
91 | ||
2dc6a016 MS |
92 | /** |
93 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
94 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
95 | * @handle: DMA address of buffer | |
96 | * @size: size of buffer (same as passed to dma_map_page) | |
97 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
98 | * | |
99 | * Unmap a page streaming mode DMA translation. The handle and size | |
100 | * must match what was provided in the previous dma_map_page() call. | |
101 | * All other usages are undefined. | |
102 | * | |
103 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
104 | * whatever the device wrote there. | |
105 | */ | |
51fde349 | 106 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
107 | size_t size, enum dma_data_direction dir, |
108 | struct dma_attrs *attrs) | |
109 | { | |
dd37e940 | 110 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
111 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
112 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
113 | } |
114 | ||
51fde349 | 115 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
116 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
117 | { | |
118 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
119 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 120 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2dc6a016 MS |
121 | } |
122 | ||
51fde349 | 123 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
124 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
125 | { | |
126 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
127 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 128 | __dma_page_cpu_to_dev(page, offset, size, dir); |
2dc6a016 MS |
129 | } |
130 | ||
2dc6a016 | 131 | struct dma_map_ops arm_dma_ops = { |
f99d6034 MS |
132 | .alloc = arm_dma_alloc, |
133 | .free = arm_dma_free, | |
134 | .mmap = arm_dma_mmap, | |
dc2832e1 | 135 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
136 | .map_page = arm_dma_map_page, |
137 | .unmap_page = arm_dma_unmap_page, | |
138 | .map_sg = arm_dma_map_sg, | |
139 | .unmap_sg = arm_dma_unmap_sg, | |
140 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
141 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
142 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
143 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
144 | .set_dma_mask = arm_dma_set_mask, | |
145 | }; | |
146 | EXPORT_SYMBOL(arm_dma_ops); | |
147 | ||
dd37e940 RH |
148 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, |
149 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs); | |
150 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
151 | dma_addr_t handle, struct dma_attrs *attrs); | |
55af8a91 ML |
152 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
153 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
154 | struct dma_attrs *attrs); | |
dd37e940 RH |
155 | |
156 | struct dma_map_ops arm_coherent_dma_ops = { | |
157 | .alloc = arm_coherent_dma_alloc, | |
158 | .free = arm_coherent_dma_free, | |
55af8a91 | 159 | .mmap = arm_coherent_dma_mmap, |
dd37e940 RH |
160 | .get_sgtable = arm_dma_get_sgtable, |
161 | .map_page = arm_coherent_dma_map_page, | |
162 | .map_sg = arm_dma_map_sg, | |
163 | .set_dma_mask = arm_dma_set_mask, | |
164 | }; | |
165 | EXPORT_SYMBOL(arm_coherent_dma_ops); | |
166 | ||
9f28cde0 RK |
167 | static int __dma_supported(struct device *dev, u64 mask, bool warn) |
168 | { | |
169 | unsigned long max_dma_pfn; | |
170 | ||
171 | /* | |
172 | * If the mask allows for more memory than we can address, | |
173 | * and we actually have that much memory, then we must | |
174 | * indicate that DMA to this device is not supported. | |
175 | */ | |
176 | if (sizeof(mask) != sizeof(dma_addr_t) && | |
177 | mask > (dma_addr_t)~0 && | |
8bf1268f | 178 | dma_to_pfn(dev, ~0) < max_pfn - 1) { |
9f28cde0 RK |
179 | if (warn) { |
180 | dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", | |
181 | mask); | |
182 | dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); | |
183 | } | |
184 | return 0; | |
185 | } | |
186 | ||
187 | max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); | |
188 | ||
189 | /* | |
190 | * Translate the device's DMA mask to a PFN limit. This | |
191 | * PFN number includes the page which we can DMA to. | |
192 | */ | |
193 | if (dma_to_pfn(dev, mask) < max_dma_pfn) { | |
194 | if (warn) | |
195 | dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", | |
196 | mask, | |
197 | dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, | |
198 | max_dma_pfn + 1); | |
199 | return 0; | |
200 | } | |
201 | ||
202 | return 1; | |
203 | } | |
204 | ||
ab6494f0 CM |
205 | static u64 get_coherent_dma_mask(struct device *dev) |
206 | { | |
4dcfa600 | 207 | u64 mask = (u64)DMA_BIT_MASK(32); |
ab6494f0 CM |
208 | |
209 | if (dev) { | |
210 | mask = dev->coherent_dma_mask; | |
211 | ||
212 | /* | |
213 | * Sanity check the DMA mask - it must be non-zero, and | |
214 | * must be able to be satisfied by a DMA allocation. | |
215 | */ | |
216 | if (mask == 0) { | |
217 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
218 | return 0; | |
219 | } | |
220 | ||
9f28cde0 | 221 | if (!__dma_supported(dev, mask, true)) |
ab6494f0 | 222 | return 0; |
ab6494f0 | 223 | } |
1da177e4 | 224 | |
ab6494f0 CM |
225 | return mask; |
226 | } | |
227 | ||
c7909509 MS |
228 | static void __dma_clear_buffer(struct page *page, size_t size) |
229 | { | |
c7909509 MS |
230 | /* |
231 | * Ensure that the allocated pages are zeroed, and that any data | |
232 | * lurking in the kernel direct-mapped region is invalidated. | |
233 | */ | |
9848e48f MS |
234 | if (PageHighMem(page)) { |
235 | phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); | |
236 | phys_addr_t end = base + size; | |
237 | while (size > 0) { | |
238 | void *ptr = kmap_atomic(page); | |
239 | memset(ptr, 0, PAGE_SIZE); | |
240 | dmac_flush_range(ptr, ptr + PAGE_SIZE); | |
241 | kunmap_atomic(ptr); | |
242 | page++; | |
243 | size -= PAGE_SIZE; | |
244 | } | |
245 | outer_flush_range(base, end); | |
246 | } else { | |
247 | void *ptr = page_address(page); | |
4ce63fcd MS |
248 | memset(ptr, 0, size); |
249 | dmac_flush_range(ptr, ptr + size); | |
250 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
251 | } | |
c7909509 MS |
252 | } |
253 | ||
7a9a32a9 RK |
254 | /* |
255 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
256 | * specified gfp mask. Note that 'size' must be page aligned. | |
257 | */ | |
258 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
259 | { | |
260 | unsigned long order = get_order(size); | |
261 | struct page *page, *p, *e; | |
7a9a32a9 RK |
262 | |
263 | page = alloc_pages(gfp, order); | |
264 | if (!page) | |
265 | return NULL; | |
266 | ||
267 | /* | |
268 | * Now split the huge page and free the excess pages | |
269 | */ | |
270 | split_page(page, order); | |
271 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
272 | __free_page(p); | |
273 | ||
c7909509 | 274 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
275 | |
276 | return page; | |
277 | } | |
278 | ||
279 | /* | |
280 | * Free a DMA buffer. 'size' must be page aligned. | |
281 | */ | |
282 | static void __dma_free_buffer(struct page *page, size_t size) | |
283 | { | |
284 | struct page *e = page + (size >> PAGE_SHIFT); | |
285 | ||
286 | while (page < e) { | |
287 | __free_page(page); | |
288 | page++; | |
289 | } | |
290 | } | |
291 | ||
ab6494f0 | 292 | #ifdef CONFIG_MMU |
a5e9d38b | 293 | |
e9da6e99 | 294 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
9848e48f | 295 | pgprot_t prot, struct page **ret_page, |
6e8266e3 | 296 | const void *caller, bool want_vaddr); |
99d1717d | 297 | |
e9da6e99 MS |
298 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
299 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 300 | const void *caller, bool want_vaddr); |
99d1717d | 301 | |
e9da6e99 MS |
302 | static void * |
303 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
304 | const void *caller) | |
99d1717d | 305 | { |
e9da6e99 MS |
306 | /* |
307 | * DMA allocation can be mapped to user space, so lets | |
308 | * set VM_USERMAP flags too. | |
309 | */ | |
513510dd LA |
310 | return dma_common_contiguous_remap(page, size, |
311 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
312 | prot, caller); | |
99d1717d | 313 | } |
1da177e4 | 314 | |
e9da6e99 | 315 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 316 | { |
513510dd LA |
317 | dma_common_free_remap(cpu_addr, size, |
318 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
88c58f3b | 319 | } |
88c58f3b | 320 | |
6e5267aa | 321 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
36d0fd21 | 322 | static struct gen_pool *atomic_pool; |
6e5267aa | 323 | |
36d0fd21 | 324 | static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE; |
c7909509 MS |
325 | |
326 | static int __init early_coherent_pool(char *p) | |
327 | { | |
36d0fd21 | 328 | atomic_pool_size = memparse(p, &p); |
c7909509 MS |
329 | return 0; |
330 | } | |
331 | early_param("coherent_pool", early_coherent_pool); | |
332 | ||
6e5267aa MS |
333 | void __init init_dma_coherent_pool_size(unsigned long size) |
334 | { | |
335 | /* | |
336 | * Catch any attempt to set the pool size too late. | |
337 | */ | |
36d0fd21 | 338 | BUG_ON(atomic_pool); |
6e5267aa MS |
339 | |
340 | /* | |
341 | * Set architecture specific coherent pool size only if | |
342 | * it has not been changed by kernel command line parameter. | |
343 | */ | |
36d0fd21 LA |
344 | if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE) |
345 | atomic_pool_size = size; | |
6e5267aa MS |
346 | } |
347 | ||
c7909509 MS |
348 | /* |
349 | * Initialise the coherent pool for atomic allocations. | |
350 | */ | |
e9da6e99 | 351 | static int __init atomic_pool_init(void) |
c7909509 | 352 | { |
71b55663 | 353 | pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); |
9d1400cf | 354 | gfp_t gfp = GFP_KERNEL | GFP_DMA; |
c7909509 MS |
355 | struct page *page; |
356 | void *ptr; | |
c7909509 | 357 | |
36d0fd21 LA |
358 | atomic_pool = gen_pool_create(PAGE_SHIFT, -1); |
359 | if (!atomic_pool) | |
360 | goto out; | |
6b3fe472 | 361 | |
e464ef16 | 362 | if (dev_get_cma_area(NULL)) |
36d0fd21 | 363 | ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot, |
6e8266e3 | 364 | &page, atomic_pool_init, true); |
e9da6e99 | 365 | else |
36d0fd21 | 366 | ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot, |
6e8266e3 | 367 | &page, atomic_pool_init, true); |
c7909509 | 368 | if (ptr) { |
36d0fd21 LA |
369 | int ret; |
370 | ||
371 | ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr, | |
372 | page_to_phys(page), | |
373 | atomic_pool_size, -1); | |
374 | if (ret) | |
375 | goto destroy_genpool; | |
376 | ||
377 | gen_pool_set_algo(atomic_pool, | |
378 | gen_pool_first_fit_order_align, | |
379 | (void *)PAGE_SHIFT); | |
380 | pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n", | |
381 | atomic_pool_size / 1024); | |
c7909509 MS |
382 | return 0; |
383 | } | |
ec10665c | 384 | |
36d0fd21 LA |
385 | destroy_genpool: |
386 | gen_pool_destroy(atomic_pool); | |
387 | atomic_pool = NULL; | |
388 | out: | |
389 | pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n", | |
390 | atomic_pool_size / 1024); | |
c7909509 MS |
391 | return -ENOMEM; |
392 | } | |
393 | /* | |
394 | * CMA is activated by core_initcall, so we must be called after it. | |
395 | */ | |
e9da6e99 | 396 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
397 | |
398 | struct dma_contig_early_reserve { | |
399 | phys_addr_t base; | |
400 | unsigned long size; | |
401 | }; | |
402 | ||
403 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
404 | ||
405 | static int dma_mmu_remap_num __initdata; | |
406 | ||
407 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
408 | { | |
409 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
410 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
411 | dma_mmu_remap_num++; | |
412 | } | |
413 | ||
414 | void __init dma_contiguous_remap(void) | |
415 | { | |
416 | int i; | |
417 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
418 | phys_addr_t start = dma_mmu_remap[i].base; | |
419 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
420 | struct map_desc map; | |
421 | unsigned long addr; | |
422 | ||
423 | if (end > arm_lowmem_limit) | |
424 | end = arm_lowmem_limit; | |
425 | if (start >= end) | |
39f78e70 | 426 | continue; |
c7909509 MS |
427 | |
428 | map.pfn = __phys_to_pfn(start); | |
429 | map.virtual = __phys_to_virt(start); | |
430 | map.length = end - start; | |
431 | map.type = MT_MEMORY_DMA_READY; | |
432 | ||
433 | /* | |
6b076991 RK |
434 | * Clear previous low-memory mapping to ensure that the |
435 | * TLB does not see any conflicting entries, then flush | |
436 | * the TLB of the old entries before creating new mappings. | |
437 | * | |
438 | * This ensures that any speculatively loaded TLB entries | |
439 | * (even though they may be rare) can not cause any problems, | |
440 | * and ensures that this code is architecturally compliant. | |
c7909509 MS |
441 | */ |
442 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 443 | addr += PMD_SIZE) |
c7909509 MS |
444 | pmd_clear(pmd_off_k(addr)); |
445 | ||
6b076991 RK |
446 | flush_tlb_kernel_range(__phys_to_virt(start), |
447 | __phys_to_virt(end)); | |
448 | ||
c7909509 MS |
449 | iotable_init(&map, 1); |
450 | } | |
451 | } | |
452 | ||
c7909509 MS |
453 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
454 | void *data) | |
455 | { | |
456 | struct page *page = virt_to_page(addr); | |
457 | pgprot_t prot = *(pgprot_t *)data; | |
458 | ||
459 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
460 | return 0; | |
461 | } | |
462 | ||
463 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
464 | { | |
465 | unsigned long start = (unsigned long) page_address(page); | |
466 | unsigned end = start + size; | |
467 | ||
468 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
c7909509 MS |
469 | flush_tlb_kernel_range(start, end); |
470 | } | |
471 | ||
472 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
473 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 474 | const void *caller, bool want_vaddr) |
c7909509 MS |
475 | { |
476 | struct page *page; | |
6e8266e3 | 477 | void *ptr = NULL; |
c7909509 MS |
478 | page = __dma_alloc_buffer(dev, size, gfp); |
479 | if (!page) | |
480 | return NULL; | |
6e8266e3 CC |
481 | if (!want_vaddr) |
482 | goto out; | |
c7909509 MS |
483 | |
484 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
485 | if (!ptr) { | |
486 | __dma_free_buffer(page, size); | |
487 | return NULL; | |
488 | } | |
489 | ||
6e8266e3 | 490 | out: |
c7909509 MS |
491 | *ret_page = page; |
492 | return ptr; | |
493 | } | |
494 | ||
e9da6e99 | 495 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 496 | { |
36d0fd21 | 497 | unsigned long val; |
e9da6e99 | 498 | void *ptr = NULL; |
c7909509 | 499 | |
36d0fd21 | 500 | if (!atomic_pool) { |
e9da6e99 | 501 | WARN(1, "coherent pool not initialised!\n"); |
c7909509 MS |
502 | return NULL; |
503 | } | |
504 | ||
36d0fd21 LA |
505 | val = gen_pool_alloc(atomic_pool, size); |
506 | if (val) { | |
507 | phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val); | |
508 | ||
509 | *ret_page = phys_to_page(phys); | |
510 | ptr = (void *)val; | |
c7909509 | 511 | } |
e9da6e99 MS |
512 | |
513 | return ptr; | |
c7909509 MS |
514 | } |
515 | ||
21d0a759 HD |
516 | static bool __in_atomic_pool(void *start, size_t size) |
517 | { | |
36d0fd21 | 518 | return addr_in_gen_pool(atomic_pool, (unsigned long)start, size); |
21d0a759 HD |
519 | } |
520 | ||
e9da6e99 | 521 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 522 | { |
21d0a759 | 523 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
524 | return 0; |
525 | ||
36d0fd21 | 526 | gen_pool_free(atomic_pool, (unsigned long)start, size); |
e9da6e99 | 527 | |
c7909509 MS |
528 | return 1; |
529 | } | |
530 | ||
531 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
9848e48f | 532 | pgprot_t prot, struct page **ret_page, |
6e8266e3 | 533 | const void *caller, bool want_vaddr) |
c7909509 MS |
534 | { |
535 | unsigned long order = get_order(size); | |
536 | size_t count = size >> PAGE_SHIFT; | |
537 | struct page *page; | |
6e8266e3 | 538 | void *ptr = NULL; |
c7909509 MS |
539 | |
540 | page = dma_alloc_from_contiguous(dev, count, order); | |
541 | if (!page) | |
542 | return NULL; | |
543 | ||
544 | __dma_clear_buffer(page, size); | |
c7909509 | 545 | |
6e8266e3 CC |
546 | if (!want_vaddr) |
547 | goto out; | |
548 | ||
9848e48f MS |
549 | if (PageHighMem(page)) { |
550 | ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller); | |
551 | if (!ptr) { | |
552 | dma_release_from_contiguous(dev, page, count); | |
553 | return NULL; | |
554 | } | |
555 | } else { | |
556 | __dma_remap(page, size, prot); | |
557 | ptr = page_address(page); | |
558 | } | |
6e8266e3 CC |
559 | |
560 | out: | |
c7909509 | 561 | *ret_page = page; |
9848e48f | 562 | return ptr; |
c7909509 MS |
563 | } |
564 | ||
565 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
6e8266e3 | 566 | void *cpu_addr, size_t size, bool want_vaddr) |
c7909509 | 567 | { |
6e8266e3 CC |
568 | if (want_vaddr) { |
569 | if (PageHighMem(page)) | |
570 | __dma_free_remap(cpu_addr, size); | |
571 | else | |
572 | __dma_remap(page, size, PAGE_KERNEL); | |
573 | } | |
c7909509 MS |
574 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); |
575 | } | |
576 | ||
f99d6034 MS |
577 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
578 | { | |
579 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
580 | pgprot_writecombine(prot) : | |
581 | pgprot_dmacoherent(prot); | |
582 | return prot; | |
583 | } | |
584 | ||
c7909509 MS |
585 | #define nommu() 0 |
586 | ||
ab6494f0 | 587 | #else /* !CONFIG_MMU */ |
695ae0af | 588 | |
c7909509 MS |
589 | #define nommu() 1 |
590 | ||
6e8266e3 CC |
591 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
592 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL | |
e9da6e99 | 593 | #define __alloc_from_pool(size, ret_page) NULL |
6e8266e3 | 594 | #define __alloc_from_contiguous(dev, size, prot, ret, c, wv) NULL |
c7909509 | 595 | #define __free_from_pool(cpu_addr, size) 0 |
6e8266e3 | 596 | #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0) |
c7909509 | 597 | #define __dma_free_remap(cpu_addr, size) do { } while (0) |
31ebf944 RK |
598 | |
599 | #endif /* CONFIG_MMU */ | |
600 | ||
c7909509 MS |
601 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
602 | struct page **ret_page) | |
ab6494f0 | 603 | { |
c7909509 MS |
604 | struct page *page; |
605 | page = __dma_alloc_buffer(dev, size, gfp); | |
606 | if (!page) | |
607 | return NULL; | |
608 | ||
609 | *ret_page = page; | |
610 | return page_address(page); | |
611 | } | |
612 | ||
613 | ||
614 | ||
615 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
6e8266e3 CC |
616 | gfp_t gfp, pgprot_t prot, bool is_coherent, |
617 | struct dma_attrs *attrs, const void *caller) | |
c7909509 MS |
618 | { |
619 | u64 mask = get_coherent_dma_mask(dev); | |
3dd7ea92 | 620 | struct page *page = NULL; |
31ebf944 | 621 | void *addr; |
6e8266e3 | 622 | bool want_vaddr; |
ab6494f0 | 623 | |
c7909509 MS |
624 | #ifdef CONFIG_DMA_API_DEBUG |
625 | u64 limit = (mask + 1) & ~mask; | |
626 | if (limit && size >= limit) { | |
627 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
628 | size, mask); | |
629 | return NULL; | |
630 | } | |
631 | #endif | |
632 | ||
633 | if (!mask) | |
634 | return NULL; | |
635 | ||
636 | if (mask < 0xffffffffULL) | |
637 | gfp |= GFP_DMA; | |
638 | ||
ea2e7057 SB |
639 | /* |
640 | * Following is a work-around (a.k.a. hack) to prevent pages | |
641 | * with __GFP_COMP being passed to split_page() which cannot | |
642 | * handle them. The real problem is that this flag probably | |
643 | * should be 0 on ARM as it is not supported on this | |
644 | * platform; see CONFIG_HUGETLBFS. | |
645 | */ | |
646 | gfp &= ~(__GFP_COMP); | |
647 | ||
553ac788 | 648 | *handle = DMA_ERROR_CODE; |
04da5694 | 649 | size = PAGE_ALIGN(size); |
6e8266e3 | 650 | want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs); |
ab6494f0 | 651 | |
21caf3a7 LN |
652 | if (nommu()) |
653 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
d0164adc | 654 | else if (dev_get_cma_area(dev) && (gfp & __GFP_DIRECT_RECLAIM)) |
21caf3a7 LN |
655 | addr = __alloc_from_contiguous(dev, size, prot, &page, |
656 | caller, want_vaddr); | |
657 | else if (is_coherent) | |
c7909509 | 658 | addr = __alloc_simple_buffer(dev, size, gfp, &page); |
d0164adc | 659 | else if (!gfpflags_allow_blocking(gfp)) |
e9da6e99 | 660 | addr = __alloc_from_pool(size, &page); |
31ebf944 | 661 | else |
21caf3a7 LN |
662 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, |
663 | caller, want_vaddr); | |
695ae0af | 664 | |
6e8266e3 | 665 | if (page) |
9eedd963 | 666 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 667 | |
6e8266e3 | 668 | return want_vaddr ? addr : page; |
31ebf944 | 669 | } |
1da177e4 LT |
670 | |
671 | /* | |
672 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
673 | * virtual and bus address for that space. | |
674 | */ | |
f99d6034 MS |
675 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
676 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 677 | { |
0ea1ec71 | 678 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
1fe53268 | 679 | |
dd37e940 | 680 | return __dma_alloc(dev, size, handle, gfp, prot, false, |
6e8266e3 | 681 | attrs, __builtin_return_address(0)); |
dd37e940 RH |
682 | } |
683 | ||
684 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
685 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
686 | { | |
21caf3a7 | 687 | return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true, |
6e8266e3 | 688 | attrs, __builtin_return_address(0)); |
1da177e4 | 689 | } |
1da177e4 | 690 | |
55af8a91 | 691 | static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
f99d6034 MS |
692 | void *cpu_addr, dma_addr_t dma_addr, size_t size, |
693 | struct dma_attrs *attrs) | |
1da177e4 | 694 | { |
ab6494f0 CM |
695 | int ret = -ENXIO; |
696 | #ifdef CONFIG_MMU | |
50262a4b MS |
697 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
698 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 699 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
700 | unsigned long off = vma->vm_pgoff; |
701 | ||
47142f07 MS |
702 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
703 | return ret; | |
704 | ||
50262a4b MS |
705 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
706 | ret = remap_pfn_range(vma, vma->vm_start, | |
707 | pfn + off, | |
708 | vma->vm_end - vma->vm_start, | |
709 | vma->vm_page_prot); | |
710 | } | |
ab6494f0 | 711 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
712 | |
713 | return ret; | |
714 | } | |
715 | ||
55af8a91 ML |
716 | /* |
717 | * Create userspace mapping for the DMA-coherent memory. | |
718 | */ | |
719 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
720 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
721 | struct dma_attrs *attrs) | |
722 | { | |
723 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
724 | } | |
725 | ||
726 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
727 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
728 | struct dma_attrs *attrs) | |
729 | { | |
730 | #ifdef CONFIG_MMU | |
731 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
732 | #endif /* CONFIG_MMU */ | |
733 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
734 | } | |
735 | ||
1da177e4 | 736 | /* |
c7909509 | 737 | * Free a buffer as defined by the above mapping. |
1da177e4 | 738 | */ |
dd37e940 RH |
739 | static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
740 | dma_addr_t handle, struct dma_attrs *attrs, | |
741 | bool is_coherent) | |
1da177e4 | 742 | { |
c7909509 | 743 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
6e8266e3 | 744 | bool want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs); |
5edf71ae | 745 | |
3e82d012 RK |
746 | size = PAGE_ALIGN(size); |
747 | ||
21caf3a7 | 748 | if (nommu()) { |
c7909509 | 749 | __dma_free_buffer(page, size); |
21caf3a7 | 750 | } else if (!is_coherent && __free_from_pool(cpu_addr, size)) { |
d9e0d149 | 751 | return; |
e464ef16 | 752 | } else if (!dev_get_cma_area(dev)) { |
21caf3a7 | 753 | if (want_vaddr && !is_coherent) |
6e8266e3 | 754 | __dma_free_remap(cpu_addr, size); |
c7909509 MS |
755 | __dma_free_buffer(page, size); |
756 | } else { | |
c7909509 MS |
757 | /* |
758 | * Non-atomic allocations cannot be freed with IRQs disabled | |
759 | */ | |
760 | WARN_ON(irqs_disabled()); | |
6e8266e3 | 761 | __free_from_contiguous(dev, page, cpu_addr, size, want_vaddr); |
c7909509 | 762 | } |
1da177e4 | 763 | } |
afd1a321 | 764 | |
dd37e940 RH |
765 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
766 | dma_addr_t handle, struct dma_attrs *attrs) | |
767 | { | |
768 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, false); | |
769 | } | |
770 | ||
771 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
772 | dma_addr_t handle, struct dma_attrs *attrs) | |
773 | { | |
774 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, true); | |
775 | } | |
776 | ||
dc2832e1 MS |
777 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
778 | void *cpu_addr, dma_addr_t handle, size_t size, | |
779 | struct dma_attrs *attrs) | |
780 | { | |
781 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
782 | int ret; | |
783 | ||
784 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
785 | if (unlikely(ret)) | |
786 | return ret; | |
787 | ||
788 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
789 | return 0; | |
790 | } | |
791 | ||
4ea0d737 | 792 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
793 | size_t size, enum dma_data_direction dir, |
794 | void (*op)(const void *, size_t, int)) | |
43377453 | 795 | { |
15653371 RK |
796 | unsigned long pfn; |
797 | size_t left = size; | |
798 | ||
799 | pfn = page_to_pfn(page) + offset / PAGE_SIZE; | |
800 | offset %= PAGE_SIZE; | |
801 | ||
43377453 NP |
802 | /* |
803 | * A single sg entry may refer to multiple physically contiguous | |
804 | * pages. But we still need to process highmem pages individually. | |
805 | * If highmem is not configured then the bulk of this loop gets | |
806 | * optimized out. | |
807 | */ | |
43377453 NP |
808 | do { |
809 | size_t len = left; | |
93f1d629 RK |
810 | void *vaddr; |
811 | ||
15653371 RK |
812 | page = pfn_to_page(pfn); |
813 | ||
93f1d629 | 814 | if (PageHighMem(page)) { |
15653371 | 815 | if (len + offset > PAGE_SIZE) |
93f1d629 | 816 | len = PAGE_SIZE - offset; |
dd0f67f4 JK |
817 | |
818 | if (cache_is_vipt_nonaliasing()) { | |
39af22a7 | 819 | vaddr = kmap_atomic(page); |
7e5a69e8 | 820 | op(vaddr + offset, len, dir); |
39af22a7 | 821 | kunmap_atomic(vaddr); |
dd0f67f4 JK |
822 | } else { |
823 | vaddr = kmap_high_get(page); | |
824 | if (vaddr) { | |
825 | op(vaddr + offset, len, dir); | |
826 | kunmap_high(page); | |
827 | } | |
43377453 | 828 | } |
93f1d629 RK |
829 | } else { |
830 | vaddr = page_address(page) + offset; | |
a9c9147e | 831 | op(vaddr, len, dir); |
43377453 | 832 | } |
43377453 | 833 | offset = 0; |
15653371 | 834 | pfn++; |
43377453 NP |
835 | left -= len; |
836 | } while (left); | |
837 | } | |
4ea0d737 | 838 | |
51fde349 MS |
839 | /* |
840 | * Make an area consistent for devices. | |
841 | * Note: Drivers should NOT use this function directly, as it will break | |
842 | * platforms with CONFIG_DMABOUNCE. | |
843 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
844 | */ | |
845 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
846 | size_t size, enum dma_data_direction dir) |
847 | { | |
2161c248 | 848 | phys_addr_t paddr; |
65af191a | 849 | |
a9c9147e | 850 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
851 | |
852 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
853 | if (dir == DMA_FROM_DEVICE) { |
854 | outer_inv_range(paddr, paddr + size); | |
855 | } else { | |
856 | outer_clean_range(paddr, paddr + size); | |
857 | } | |
858 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 859 | } |
4ea0d737 | 860 | |
51fde349 | 861 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
862 | size_t size, enum dma_data_direction dir) |
863 | { | |
2161c248 | 864 | phys_addr_t paddr = page_to_phys(page) + off; |
2ffe2da3 RK |
865 | |
866 | /* FIXME: non-speculating: not required */ | |
deace4a6 RK |
867 | /* in any case, don't bother invalidating if DMA to device */ |
868 | if (dir != DMA_TO_DEVICE) { | |
2ffe2da3 RK |
869 | outer_inv_range(paddr, paddr + size); |
870 | ||
deace4a6 RK |
871 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
872 | } | |
c0177800 CM |
873 | |
874 | /* | |
b2a234ed | 875 | * Mark the D-cache clean for these pages to avoid extra flushing. |
c0177800 | 876 | */ |
b2a234ed ML |
877 | if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) { |
878 | unsigned long pfn; | |
879 | size_t left = size; | |
880 | ||
881 | pfn = page_to_pfn(page) + off / PAGE_SIZE; | |
882 | off %= PAGE_SIZE; | |
883 | if (off) { | |
884 | pfn++; | |
885 | left -= PAGE_SIZE - off; | |
886 | } | |
887 | while (left >= PAGE_SIZE) { | |
888 | page = pfn_to_page(pfn++); | |
889 | set_bit(PG_dcache_clean, &page->flags); | |
890 | left -= PAGE_SIZE; | |
891 | } | |
892 | } | |
4ea0d737 | 893 | } |
43377453 | 894 | |
afd1a321 | 895 | /** |
2a550e73 | 896 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
897 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
898 | * @sg: list of buffers | |
899 | * @nents: number of buffers to map | |
900 | * @dir: DMA transfer direction | |
901 | * | |
902 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
903 | * This is the scatter-gather version of the dma_map_single interface. | |
904 | * Here the scatter gather list elements are each tagged with the | |
905 | * appropriate dma address and length. They are obtained via | |
906 | * sg_dma_{address,length}. | |
907 | * | |
908 | * Device ownership issues as mentioned for dma_map_single are the same | |
909 | * here. | |
910 | */ | |
2dc6a016 MS |
911 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
912 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 913 | { |
2a550e73 | 914 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 915 | struct scatterlist *s; |
01135d92 | 916 | int i, j; |
afd1a321 RK |
917 | |
918 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
919 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
920 | s->dma_length = s->length; | |
921 | #endif | |
2a550e73 MS |
922 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
923 | s->length, dir, attrs); | |
01135d92 RK |
924 | if (dma_mapping_error(dev, s->dma_address)) |
925 | goto bad_mapping; | |
afd1a321 | 926 | } |
afd1a321 | 927 | return nents; |
01135d92 RK |
928 | |
929 | bad_mapping: | |
930 | for_each_sg(sg, s, i, j) | |
2a550e73 | 931 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 932 | return 0; |
afd1a321 | 933 | } |
afd1a321 RK |
934 | |
935 | /** | |
2a550e73 | 936 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
937 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
938 | * @sg: list of buffers | |
0adfca6f | 939 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
940 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
941 | * | |
942 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
943 | * rules concerning calls here are the same as for dma_unmap_single(). | |
944 | */ | |
2dc6a016 MS |
945 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
946 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 947 | { |
2a550e73 | 948 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 949 | struct scatterlist *s; |
01135d92 | 950 | |
01135d92 | 951 | int i; |
24056f52 | 952 | |
01135d92 | 953 | for_each_sg(sg, s, nents, i) |
2a550e73 | 954 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 955 | } |
afd1a321 RK |
956 | |
957 | /** | |
2a550e73 | 958 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
959 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
960 | * @sg: list of buffers | |
961 | * @nents: number of buffers to map (returned from dma_map_sg) | |
962 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
963 | */ | |
2dc6a016 | 964 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
965 | int nents, enum dma_data_direction dir) |
966 | { | |
2a550e73 | 967 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
968 | struct scatterlist *s; |
969 | int i; | |
970 | ||
2a550e73 MS |
971 | for_each_sg(sg, s, nents, i) |
972 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
973 | dir); | |
afd1a321 | 974 | } |
afd1a321 RK |
975 | |
976 | /** | |
2a550e73 | 977 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
978 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
979 | * @sg: list of buffers | |
980 | * @nents: number of buffers to map (returned from dma_map_sg) | |
981 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
982 | */ | |
2dc6a016 | 983 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
984 | int nents, enum dma_data_direction dir) |
985 | { | |
2a550e73 | 986 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
987 | struct scatterlist *s; |
988 | int i; | |
989 | ||
2a550e73 MS |
990 | for_each_sg(sg, s, nents, i) |
991 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
992 | dir); | |
afd1a321 | 993 | } |
24056f52 | 994 | |
022ae537 RK |
995 | /* |
996 | * Return whether the given device DMA address mask can be supported | |
997 | * properly. For example, if your device can only drive the low 24-bits | |
998 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
999 | * to this function. | |
1000 | */ | |
1001 | int dma_supported(struct device *dev, u64 mask) | |
1002 | { | |
9f28cde0 | 1003 | return __dma_supported(dev, mask, false); |
022ae537 RK |
1004 | } |
1005 | EXPORT_SYMBOL(dma_supported); | |
1006 | ||
87b54e78 | 1007 | int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
1008 | { |
1009 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
1010 | return -EIO; | |
1011 | ||
022ae537 | 1012 | *dev->dma_mask = dma_mask; |
022ae537 RK |
1013 | |
1014 | return 0; | |
1015 | } | |
022ae537 | 1016 | |
24056f52 RK |
1017 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
1018 | ||
1019 | static int __init dma_debug_do_init(void) | |
1020 | { | |
1021 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
1022 | return 0; | |
1023 | } | |
1024 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
1025 | |
1026 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
1027 | ||
1028 | /* IOMMU */ | |
1029 | ||
4d852ef8 AH |
1030 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping); |
1031 | ||
4ce63fcd MS |
1032 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, |
1033 | size_t size) | |
1034 | { | |
1035 | unsigned int order = get_order(size); | |
1036 | unsigned int align = 0; | |
1037 | unsigned int count, start; | |
006f841d | 1038 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1039 | unsigned long flags; |
4d852ef8 AH |
1040 | dma_addr_t iova; |
1041 | int i; | |
4ce63fcd | 1042 | |
60460abf SWK |
1043 | if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT) |
1044 | order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT; | |
1045 | ||
68efd7d2 MS |
1046 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1047 | align = (1 << order) - 1; | |
4ce63fcd MS |
1048 | |
1049 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 AH |
1050 | for (i = 0; i < mapping->nr_bitmaps; i++) { |
1051 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1052 | mapping->bits, 0, count, align); | |
1053 | ||
1054 | if (start > mapping->bits) | |
1055 | continue; | |
1056 | ||
1057 | bitmap_set(mapping->bitmaps[i], start, count); | |
1058 | break; | |
4ce63fcd MS |
1059 | } |
1060 | ||
4d852ef8 AH |
1061 | /* |
1062 | * No unused range found. Try to extend the existing mapping | |
1063 | * and perform a second attempt to reserve an IO virtual | |
1064 | * address range of size bytes. | |
1065 | */ | |
1066 | if (i == mapping->nr_bitmaps) { | |
1067 | if (extend_iommu_mapping(mapping)) { | |
1068 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1069 | return DMA_ERROR_CODE; | |
1070 | } | |
1071 | ||
1072 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1073 | mapping->bits, 0, count, align); | |
1074 | ||
1075 | if (start > mapping->bits) { | |
1076 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1077 | return DMA_ERROR_CODE; | |
1078 | } | |
1079 | ||
1080 | bitmap_set(mapping->bitmaps[i], start, count); | |
1081 | } | |
4ce63fcd MS |
1082 | spin_unlock_irqrestore(&mapping->lock, flags); |
1083 | ||
006f841d | 1084 | iova = mapping->base + (mapping_size * i); |
68efd7d2 | 1085 | iova += start << PAGE_SHIFT; |
4d852ef8 AH |
1086 | |
1087 | return iova; | |
4ce63fcd MS |
1088 | } |
1089 | ||
1090 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
1091 | dma_addr_t addr, size_t size) | |
1092 | { | |
4d852ef8 | 1093 | unsigned int start, count; |
006f841d | 1094 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1095 | unsigned long flags; |
4d852ef8 AH |
1096 | dma_addr_t bitmap_base; |
1097 | u32 bitmap_index; | |
1098 | ||
1099 | if (!size) | |
1100 | return; | |
1101 | ||
006f841d | 1102 | bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size; |
4d852ef8 AH |
1103 | BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); |
1104 | ||
006f841d | 1105 | bitmap_base = mapping->base + mapping_size * bitmap_index; |
4d852ef8 | 1106 | |
68efd7d2 | 1107 | start = (addr - bitmap_base) >> PAGE_SHIFT; |
4d852ef8 | 1108 | |
006f841d | 1109 | if (addr + size > bitmap_base + mapping_size) { |
4d852ef8 AH |
1110 | /* |
1111 | * The address range to be freed reaches into the iova | |
1112 | * range of the next bitmap. This should not happen as | |
1113 | * we don't allow this in __alloc_iova (at the | |
1114 | * moment). | |
1115 | */ | |
1116 | BUG(); | |
1117 | } else | |
68efd7d2 | 1118 | count = size >> PAGE_SHIFT; |
4ce63fcd MS |
1119 | |
1120 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 | 1121 | bitmap_clear(mapping->bitmaps[bitmap_index], start, count); |
4ce63fcd MS |
1122 | spin_unlock_irqrestore(&mapping->lock, flags); |
1123 | } | |
1124 | ||
549a17e4 MS |
1125 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, |
1126 | gfp_t gfp, struct dma_attrs *attrs) | |
4ce63fcd MS |
1127 | { |
1128 | struct page **pages; | |
1129 | int count = size >> PAGE_SHIFT; | |
1130 | int array_size = count * sizeof(struct page *); | |
1131 | int i = 0; | |
1132 | ||
1133 | if (array_size <= PAGE_SIZE) | |
23be7fda | 1134 | pages = kzalloc(array_size, GFP_KERNEL); |
4ce63fcd MS |
1135 | else |
1136 | pages = vzalloc(array_size); | |
1137 | if (!pages) | |
1138 | return NULL; | |
1139 | ||
549a17e4 MS |
1140 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) |
1141 | { | |
1142 | unsigned long order = get_order(size); | |
1143 | struct page *page; | |
1144 | ||
1145 | page = dma_alloc_from_contiguous(dev, count, order); | |
1146 | if (!page) | |
1147 | goto error; | |
1148 | ||
1149 | __dma_clear_buffer(page, size); | |
1150 | ||
1151 | for (i = 0; i < count; i++) | |
1152 | pages[i] = page + i; | |
1153 | ||
1154 | return pages; | |
1155 | } | |
1156 | ||
f8669bef MS |
1157 | /* |
1158 | * IOMMU can map any pages, so himem can also be used here | |
1159 | */ | |
1160 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
1161 | ||
4ce63fcd | 1162 | while (count) { |
49f28aa6 TF |
1163 | int j, order; |
1164 | ||
1165 | for (order = __fls(count); order > 0; --order) { | |
1166 | /* | |
1167 | * We do not want OOM killer to be invoked as long | |
1168 | * as we can fall back to single pages, so we force | |
1169 | * __GFP_NORETRY for orders higher than zero. | |
1170 | */ | |
1171 | pages[i] = alloc_pages(gfp | __GFP_NORETRY, order); | |
1172 | if (pages[i]) | |
1173 | break; | |
1174 | } | |
4ce63fcd | 1175 | |
49f28aa6 TF |
1176 | if (!pages[i]) { |
1177 | /* | |
1178 | * Fall back to single page allocation. | |
1179 | * Might invoke OOM killer as last resort. | |
1180 | */ | |
1181 | pages[i] = alloc_pages(gfp, 0); | |
1182 | if (!pages[i]) | |
1183 | goto error; | |
1184 | } | |
4ce63fcd | 1185 | |
5a796eeb | 1186 | if (order) { |
4ce63fcd | 1187 | split_page(pages[i], order); |
5a796eeb HD |
1188 | j = 1 << order; |
1189 | while (--j) | |
1190 | pages[i + j] = pages[i] + j; | |
1191 | } | |
4ce63fcd MS |
1192 | |
1193 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
1194 | i += 1 << order; | |
1195 | count -= 1 << order; | |
1196 | } | |
1197 | ||
1198 | return pages; | |
1199 | error: | |
9fa8af91 | 1200 | while (i--) |
4ce63fcd MS |
1201 | if (pages[i]) |
1202 | __free_pages(pages[i], 0); | |
1d5cfdb0 | 1203 | kvfree(pages); |
4ce63fcd MS |
1204 | return NULL; |
1205 | } | |
1206 | ||
549a17e4 MS |
1207 | static int __iommu_free_buffer(struct device *dev, struct page **pages, |
1208 | size_t size, struct dma_attrs *attrs) | |
4ce63fcd MS |
1209 | { |
1210 | int count = size >> PAGE_SHIFT; | |
4ce63fcd | 1211 | int i; |
549a17e4 MS |
1212 | |
1213 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) { | |
1214 | dma_release_from_contiguous(dev, pages[0], count); | |
1215 | } else { | |
1216 | for (i = 0; i < count; i++) | |
1217 | if (pages[i]) | |
1218 | __free_pages(pages[i], 0); | |
1219 | } | |
1220 | ||
1d5cfdb0 | 1221 | kvfree(pages); |
4ce63fcd MS |
1222 | return 0; |
1223 | } | |
1224 | ||
1225 | /* | |
1226 | * Create a CPU mapping for a specified pages | |
1227 | */ | |
1228 | static void * | |
e9da6e99 MS |
1229 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1230 | const void *caller) | |
4ce63fcd | 1231 | { |
513510dd LA |
1232 | return dma_common_pages_remap(pages, size, |
1233 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller); | |
4ce63fcd MS |
1234 | } |
1235 | ||
1236 | /* | |
1237 | * Create a mapping in device IO address space for specified pages | |
1238 | */ | |
1239 | static dma_addr_t | |
1240 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1241 | { | |
89cfdb19 | 1242 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1243 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1244 | dma_addr_t dma_addr, iova; | |
90cde558 | 1245 | int i; |
4ce63fcd MS |
1246 | |
1247 | dma_addr = __alloc_iova(mapping, size); | |
1248 | if (dma_addr == DMA_ERROR_CODE) | |
1249 | return dma_addr; | |
1250 | ||
1251 | iova = dma_addr; | |
1252 | for (i = 0; i < count; ) { | |
90cde558 AP |
1253 | int ret; |
1254 | ||
4ce63fcd MS |
1255 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; |
1256 | phys_addr_t phys = page_to_phys(pages[i]); | |
1257 | unsigned int len, j; | |
1258 | ||
1259 | for (j = i + 1; j < count; j++, next_pfn++) | |
1260 | if (page_to_pfn(pages[j]) != next_pfn) | |
1261 | break; | |
1262 | ||
1263 | len = (j - i) << PAGE_SHIFT; | |
c9b24996 AH |
1264 | ret = iommu_map(mapping->domain, iova, phys, len, |
1265 | IOMMU_READ|IOMMU_WRITE); | |
4ce63fcd MS |
1266 | if (ret < 0) |
1267 | goto fail; | |
1268 | iova += len; | |
1269 | i = j; | |
1270 | } | |
1271 | return dma_addr; | |
1272 | fail: | |
1273 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1274 | __free_iova(mapping, dma_addr, size); | |
1275 | return DMA_ERROR_CODE; | |
1276 | } | |
1277 | ||
1278 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1279 | { | |
89cfdb19 | 1280 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1281 | |
1282 | /* | |
1283 | * add optional in-page offset from iova to size and align | |
1284 | * result to page size | |
1285 | */ | |
1286 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1287 | iova &= PAGE_MASK; | |
1288 | ||
1289 | iommu_unmap(mapping->domain, iova, size); | |
1290 | __free_iova(mapping, iova, size); | |
1291 | return 0; | |
1292 | } | |
1293 | ||
665bad7b HD |
1294 | static struct page **__atomic_get_pages(void *addr) |
1295 | { | |
36d0fd21 LA |
1296 | struct page *page; |
1297 | phys_addr_t phys; | |
1298 | ||
1299 | phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr); | |
1300 | page = phys_to_page(phys); | |
665bad7b | 1301 | |
36d0fd21 | 1302 | return (struct page **)page; |
665bad7b HD |
1303 | } |
1304 | ||
955c757e | 1305 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) |
e9da6e99 MS |
1306 | { |
1307 | struct vm_struct *area; | |
1308 | ||
665bad7b HD |
1309 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) |
1310 | return __atomic_get_pages(cpu_addr); | |
1311 | ||
955c757e MS |
1312 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1313 | return cpu_addr; | |
1314 | ||
e9da6e99 MS |
1315 | area = find_vm_area(cpu_addr); |
1316 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1317 | return area->pages; | |
1318 | return NULL; | |
1319 | } | |
1320 | ||
479ed93a HD |
1321 | static void *__iommu_alloc_atomic(struct device *dev, size_t size, |
1322 | dma_addr_t *handle) | |
1323 | { | |
1324 | struct page *page; | |
1325 | void *addr; | |
1326 | ||
1327 | addr = __alloc_from_pool(size, &page); | |
1328 | if (!addr) | |
1329 | return NULL; | |
1330 | ||
1331 | *handle = __iommu_create_mapping(dev, &page, size); | |
1332 | if (*handle == DMA_ERROR_CODE) | |
1333 | goto err_mapping; | |
1334 | ||
1335 | return addr; | |
1336 | ||
1337 | err_mapping: | |
1338 | __free_from_pool(addr, size); | |
1339 | return NULL; | |
1340 | } | |
1341 | ||
d5898291 | 1342 | static void __iommu_free_atomic(struct device *dev, void *cpu_addr, |
479ed93a HD |
1343 | dma_addr_t handle, size_t size) |
1344 | { | |
1345 | __iommu_remove_mapping(dev, handle, size); | |
d5898291 | 1346 | __free_from_pool(cpu_addr, size); |
479ed93a HD |
1347 | } |
1348 | ||
4ce63fcd MS |
1349 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1350 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1351 | { | |
71b55663 | 1352 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
4ce63fcd MS |
1353 | struct page **pages; |
1354 | void *addr = NULL; | |
1355 | ||
1356 | *handle = DMA_ERROR_CODE; | |
1357 | size = PAGE_ALIGN(size); | |
1358 | ||
d0164adc | 1359 | if (!gfpflags_allow_blocking(gfp)) |
479ed93a HD |
1360 | return __iommu_alloc_atomic(dev, size, handle); |
1361 | ||
5b91a98c RZ |
1362 | /* |
1363 | * Following is a work-around (a.k.a. hack) to prevent pages | |
1364 | * with __GFP_COMP being passed to split_page() which cannot | |
1365 | * handle them. The real problem is that this flag probably | |
1366 | * should be 0 on ARM as it is not supported on this | |
1367 | * platform; see CONFIG_HUGETLBFS. | |
1368 | */ | |
1369 | gfp &= ~(__GFP_COMP); | |
1370 | ||
549a17e4 | 1371 | pages = __iommu_alloc_buffer(dev, size, gfp, attrs); |
4ce63fcd MS |
1372 | if (!pages) |
1373 | return NULL; | |
1374 | ||
1375 | *handle = __iommu_create_mapping(dev, pages, size); | |
1376 | if (*handle == DMA_ERROR_CODE) | |
1377 | goto err_buffer; | |
1378 | ||
955c757e MS |
1379 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1380 | return pages; | |
1381 | ||
e9da6e99 MS |
1382 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1383 | __builtin_return_address(0)); | |
4ce63fcd MS |
1384 | if (!addr) |
1385 | goto err_mapping; | |
1386 | ||
1387 | return addr; | |
1388 | ||
1389 | err_mapping: | |
1390 | __iommu_remove_mapping(dev, *handle, size); | |
1391 | err_buffer: | |
549a17e4 | 1392 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1393 | return NULL; |
1394 | } | |
1395 | ||
1396 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1397 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1398 | struct dma_attrs *attrs) | |
1399 | { | |
e9da6e99 MS |
1400 | unsigned long uaddr = vma->vm_start; |
1401 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1402 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
371f0f08 MS |
1403 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1404 | unsigned long off = vma->vm_pgoff; | |
4ce63fcd MS |
1405 | |
1406 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1407 | |
e9da6e99 MS |
1408 | if (!pages) |
1409 | return -ENXIO; | |
4ce63fcd | 1410 | |
371f0f08 MS |
1411 | if (off >= nr_pages || (usize >> PAGE_SHIFT) > nr_pages - off) |
1412 | return -ENXIO; | |
1413 | ||
7e312103 MS |
1414 | pages += off; |
1415 | ||
e9da6e99 MS |
1416 | do { |
1417 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1418 | if (ret) { | |
1419 | pr_err("Remapping memory failed: %d\n", ret); | |
1420 | return ret; | |
1421 | } | |
1422 | uaddr += PAGE_SIZE; | |
1423 | usize -= PAGE_SIZE; | |
1424 | } while (usize > 0); | |
4ce63fcd | 1425 | |
4ce63fcd MS |
1426 | return 0; |
1427 | } | |
1428 | ||
1429 | /* | |
1430 | * free a page as defined by the above mapping. | |
1431 | * Must not be called with IRQs disabled. | |
1432 | */ | |
1433 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1434 | dma_addr_t handle, struct dma_attrs *attrs) | |
1435 | { | |
836bfa0d | 1436 | struct page **pages; |
4ce63fcd MS |
1437 | size = PAGE_ALIGN(size); |
1438 | ||
836bfa0d YC |
1439 | if (__in_atomic_pool(cpu_addr, size)) { |
1440 | __iommu_free_atomic(dev, cpu_addr, handle, size); | |
e9da6e99 | 1441 | return; |
4ce63fcd | 1442 | } |
e9da6e99 | 1443 | |
836bfa0d YC |
1444 | pages = __iommu_get_pages(cpu_addr, attrs); |
1445 | if (!pages) { | |
1446 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
479ed93a HD |
1447 | return; |
1448 | } | |
1449 | ||
955c757e | 1450 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { |
513510dd LA |
1451 | dma_common_free_remap(cpu_addr, size, |
1452 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
955c757e | 1453 | } |
e9da6e99 MS |
1454 | |
1455 | __iommu_remove_mapping(dev, handle, size); | |
549a17e4 | 1456 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1457 | } |
1458 | ||
dc2832e1 MS |
1459 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1460 | void *cpu_addr, dma_addr_t dma_addr, | |
1461 | size_t size, struct dma_attrs *attrs) | |
1462 | { | |
1463 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1464 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1465 | ||
1466 | if (!pages) | |
1467 | return -ENXIO; | |
1468 | ||
1469 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1470 | GFP_KERNEL); | |
4ce63fcd MS |
1471 | } |
1472 | ||
c9b24996 AH |
1473 | static int __dma_direction_to_prot(enum dma_data_direction dir) |
1474 | { | |
1475 | int prot; | |
1476 | ||
1477 | switch (dir) { | |
1478 | case DMA_BIDIRECTIONAL: | |
1479 | prot = IOMMU_READ | IOMMU_WRITE; | |
1480 | break; | |
1481 | case DMA_TO_DEVICE: | |
1482 | prot = IOMMU_READ; | |
1483 | break; | |
1484 | case DMA_FROM_DEVICE: | |
1485 | prot = IOMMU_WRITE; | |
1486 | break; | |
1487 | default: | |
1488 | prot = 0; | |
1489 | } | |
1490 | ||
1491 | return prot; | |
1492 | } | |
1493 | ||
4ce63fcd MS |
1494 | /* |
1495 | * Map a part of the scatter-gather list into contiguous io address space | |
1496 | */ | |
1497 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1498 | size_t size, dma_addr_t *handle, | |
0fa478df RH |
1499 | enum dma_data_direction dir, struct dma_attrs *attrs, |
1500 | bool is_coherent) | |
4ce63fcd | 1501 | { |
89cfdb19 | 1502 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1503 | dma_addr_t iova, iova_base; |
1504 | int ret = 0; | |
1505 | unsigned int count; | |
1506 | struct scatterlist *s; | |
c9b24996 | 1507 | int prot; |
4ce63fcd MS |
1508 | |
1509 | size = PAGE_ALIGN(size); | |
1510 | *handle = DMA_ERROR_CODE; | |
1511 | ||
1512 | iova_base = iova = __alloc_iova(mapping, size); | |
1513 | if (iova == DMA_ERROR_CODE) | |
1514 | return -ENOMEM; | |
1515 | ||
1516 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
3e6110fd | 1517 | phys_addr_t phys = page_to_phys(sg_page(s)); |
4ce63fcd MS |
1518 | unsigned int len = PAGE_ALIGN(s->offset + s->length); |
1519 | ||
0fa478df RH |
1520 | if (!is_coherent && |
1521 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1522 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1523 | ||
c9b24996 AH |
1524 | prot = __dma_direction_to_prot(dir); |
1525 | ||
1526 | ret = iommu_map(mapping->domain, iova, phys, len, prot); | |
4ce63fcd MS |
1527 | if (ret < 0) |
1528 | goto fail; | |
1529 | count += len >> PAGE_SHIFT; | |
1530 | iova += len; | |
1531 | } | |
1532 | *handle = iova_base; | |
1533 | ||
1534 | return 0; | |
1535 | fail: | |
1536 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1537 | __free_iova(mapping, iova_base, size); | |
1538 | return ret; | |
1539 | } | |
1540 | ||
0fa478df RH |
1541 | static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
1542 | enum dma_data_direction dir, struct dma_attrs *attrs, | |
1543 | bool is_coherent) | |
4ce63fcd MS |
1544 | { |
1545 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1546 | int i, count = 0; | |
1547 | unsigned int offset = s->offset; | |
1548 | unsigned int size = s->offset + s->length; | |
1549 | unsigned int max = dma_get_max_seg_size(dev); | |
1550 | ||
1551 | for (i = 1; i < nents; i++) { | |
1552 | s = sg_next(s); | |
1553 | ||
1554 | s->dma_address = DMA_ERROR_CODE; | |
1555 | s->dma_length = 0; | |
1556 | ||
1557 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1558 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
0fa478df | 1559 | dir, attrs, is_coherent) < 0) |
4ce63fcd MS |
1560 | goto bad_mapping; |
1561 | ||
1562 | dma->dma_address += offset; | |
1563 | dma->dma_length = size - offset; | |
1564 | ||
1565 | size = offset = s->offset; | |
1566 | start = s; | |
1567 | dma = sg_next(dma); | |
1568 | count += 1; | |
1569 | } | |
1570 | size += s->length; | |
1571 | } | |
0fa478df RH |
1572 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs, |
1573 | is_coherent) < 0) | |
4ce63fcd MS |
1574 | goto bad_mapping; |
1575 | ||
1576 | dma->dma_address += offset; | |
1577 | dma->dma_length = size - offset; | |
1578 | ||
1579 | return count+1; | |
1580 | ||
1581 | bad_mapping: | |
1582 | for_each_sg(sg, s, count, i) | |
1583 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | /** | |
0fa478df | 1588 | * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA |
4ce63fcd MS |
1589 | * @dev: valid struct device pointer |
1590 | * @sg: list of buffers | |
0fa478df RH |
1591 | * @nents: number of buffers to map |
1592 | * @dir: DMA transfer direction | |
4ce63fcd | 1593 | * |
0fa478df RH |
1594 | * Map a set of i/o coherent buffers described by scatterlist in streaming |
1595 | * mode for DMA. The scatter gather list elements are merged together (if | |
1596 | * possible) and tagged with the appropriate dma address and length. They are | |
1597 | * obtained via sg_dma_{address,length}. | |
4ce63fcd | 1598 | */ |
0fa478df RH |
1599 | int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg, |
1600 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1601 | { | |
1602 | return __iommu_map_sg(dev, sg, nents, dir, attrs, true); | |
1603 | } | |
1604 | ||
1605 | /** | |
1606 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1607 | * @dev: valid struct device pointer | |
1608 | * @sg: list of buffers | |
1609 | * @nents: number of buffers to map | |
1610 | * @dir: DMA transfer direction | |
1611 | * | |
1612 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1613 | * The scatter gather list elements are merged together (if possible) and | |
1614 | * tagged with the appropriate dma address and length. They are obtained via | |
1615 | * sg_dma_{address,length}. | |
1616 | */ | |
1617 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, | |
1618 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1619 | { | |
1620 | return __iommu_map_sg(dev, sg, nents, dir, attrs, false); | |
1621 | } | |
1622 | ||
1623 | static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1624 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs, | |
1625 | bool is_coherent) | |
4ce63fcd MS |
1626 | { |
1627 | struct scatterlist *s; | |
1628 | int i; | |
1629 | ||
1630 | for_each_sg(sg, s, nents, i) { | |
1631 | if (sg_dma_len(s)) | |
1632 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1633 | sg_dma_len(s)); | |
0fa478df | 1634 | if (!is_coherent && |
97ef952a | 1635 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1636 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1637 | s->length, dir); | |
1638 | } | |
1639 | } | |
1640 | ||
0fa478df RH |
1641 | /** |
1642 | * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1643 | * @dev: valid struct device pointer | |
1644 | * @sg: list of buffers | |
1645 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1646 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1647 | * | |
1648 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1649 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1650 | */ | |
1651 | void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1652 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1653 | { | |
1654 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, true); | |
1655 | } | |
1656 | ||
1657 | /** | |
1658 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1659 | * @dev: valid struct device pointer | |
1660 | * @sg: list of buffers | |
1661 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1662 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1663 | * | |
1664 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1665 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1666 | */ | |
1667 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1668 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1669 | { | |
1670 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); | |
1671 | } | |
1672 | ||
4ce63fcd MS |
1673 | /** |
1674 | * arm_iommu_sync_sg_for_cpu | |
1675 | * @dev: valid struct device pointer | |
1676 | * @sg: list of buffers | |
1677 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1678 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1679 | */ | |
1680 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1681 | int nents, enum dma_data_direction dir) | |
1682 | { | |
1683 | struct scatterlist *s; | |
1684 | int i; | |
1685 | ||
1686 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1687 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1688 | |
1689 | } | |
1690 | ||
1691 | /** | |
1692 | * arm_iommu_sync_sg_for_device | |
1693 | * @dev: valid struct device pointer | |
1694 | * @sg: list of buffers | |
1695 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1696 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1697 | */ | |
1698 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1699 | int nents, enum dma_data_direction dir) | |
1700 | { | |
1701 | struct scatterlist *s; | |
1702 | int i; | |
1703 | ||
1704 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1705 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1706 | } |
1707 | ||
1708 | ||
1709 | /** | |
0fa478df | 1710 | * arm_coherent_iommu_map_page |
4ce63fcd MS |
1711 | * @dev: valid struct device pointer |
1712 | * @page: page that buffer resides in | |
1713 | * @offset: offset into page for start of buffer | |
1714 | * @size: size of buffer to map | |
1715 | * @dir: DMA transfer direction | |
1716 | * | |
0fa478df | 1717 | * Coherent IOMMU aware version of arm_dma_map_page() |
4ce63fcd | 1718 | */ |
0fa478df | 1719 | static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page, |
4ce63fcd MS |
1720 | unsigned long offset, size_t size, enum dma_data_direction dir, |
1721 | struct dma_attrs *attrs) | |
1722 | { | |
89cfdb19 | 1723 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd | 1724 | dma_addr_t dma_addr; |
13987d68 | 1725 | int ret, prot, len = PAGE_ALIGN(size + offset); |
4ce63fcd | 1726 | |
4ce63fcd MS |
1727 | dma_addr = __alloc_iova(mapping, len); |
1728 | if (dma_addr == DMA_ERROR_CODE) | |
1729 | return dma_addr; | |
1730 | ||
c9b24996 | 1731 | prot = __dma_direction_to_prot(dir); |
13987d68 WD |
1732 | |
1733 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot); | |
4ce63fcd MS |
1734 | if (ret < 0) |
1735 | goto fail; | |
1736 | ||
1737 | return dma_addr + offset; | |
1738 | fail: | |
1739 | __free_iova(mapping, dma_addr, len); | |
1740 | return DMA_ERROR_CODE; | |
1741 | } | |
1742 | ||
0fa478df RH |
1743 | /** |
1744 | * arm_iommu_map_page | |
1745 | * @dev: valid struct device pointer | |
1746 | * @page: page that buffer resides in | |
1747 | * @offset: offset into page for start of buffer | |
1748 | * @size: size of buffer to map | |
1749 | * @dir: DMA transfer direction | |
1750 | * | |
1751 | * IOMMU aware version of arm_dma_map_page() | |
1752 | */ | |
1753 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1754 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1755 | struct dma_attrs *attrs) | |
1756 | { | |
1757 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
1758 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1759 | ||
1760 | return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); | |
1761 | } | |
1762 | ||
1763 | /** | |
1764 | * arm_coherent_iommu_unmap_page | |
1765 | * @dev: valid struct device pointer | |
1766 | * @handle: DMA address of buffer | |
1767 | * @size: size of buffer (same as passed to dma_map_page) | |
1768 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1769 | * | |
1770 | * Coherent IOMMU aware version of arm_dma_unmap_page() | |
1771 | */ | |
1772 | static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1773 | size_t size, enum dma_data_direction dir, | |
1774 | struct dma_attrs *attrs) | |
1775 | { | |
89cfdb19 | 1776 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
0fa478df | 1777 | dma_addr_t iova = handle & PAGE_MASK; |
0fa478df RH |
1778 | int offset = handle & ~PAGE_MASK; |
1779 | int len = PAGE_ALIGN(size + offset); | |
1780 | ||
1781 | if (!iova) | |
1782 | return; | |
1783 | ||
1784 | iommu_unmap(mapping->domain, iova, len); | |
1785 | __free_iova(mapping, iova, len); | |
1786 | } | |
1787 | ||
4ce63fcd MS |
1788 | /** |
1789 | * arm_iommu_unmap_page | |
1790 | * @dev: valid struct device pointer | |
1791 | * @handle: DMA address of buffer | |
1792 | * @size: size of buffer (same as passed to dma_map_page) | |
1793 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1794 | * | |
1795 | * IOMMU aware version of arm_dma_unmap_page() | |
1796 | */ | |
1797 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1798 | size_t size, enum dma_data_direction dir, | |
1799 | struct dma_attrs *attrs) | |
1800 | { | |
89cfdb19 | 1801 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1802 | dma_addr_t iova = handle & PAGE_MASK; |
1803 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1804 | int offset = handle & ~PAGE_MASK; | |
1805 | int len = PAGE_ALIGN(size + offset); | |
1806 | ||
1807 | if (!iova) | |
1808 | return; | |
1809 | ||
0fa478df | 1810 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1811 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1812 | ||
1813 | iommu_unmap(mapping->domain, iova, len); | |
1814 | __free_iova(mapping, iova, len); | |
1815 | } | |
1816 | ||
1817 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1818 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1819 | { | |
89cfdb19 | 1820 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1821 | dma_addr_t iova = handle & PAGE_MASK; |
1822 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1823 | unsigned int offset = handle & ~PAGE_MASK; | |
1824 | ||
1825 | if (!iova) | |
1826 | return; | |
1827 | ||
0fa478df | 1828 | __dma_page_dev_to_cpu(page, offset, size, dir); |
4ce63fcd MS |
1829 | } |
1830 | ||
1831 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1832 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1833 | { | |
89cfdb19 | 1834 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1835 | dma_addr_t iova = handle & PAGE_MASK; |
1836 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1837 | unsigned int offset = handle & ~PAGE_MASK; | |
1838 | ||
1839 | if (!iova) | |
1840 | return; | |
1841 | ||
1842 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1843 | } | |
1844 | ||
1845 | struct dma_map_ops iommu_ops = { | |
1846 | .alloc = arm_iommu_alloc_attrs, | |
1847 | .free = arm_iommu_free_attrs, | |
1848 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 1849 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
1850 | |
1851 | .map_page = arm_iommu_map_page, | |
1852 | .unmap_page = arm_iommu_unmap_page, | |
1853 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1854 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1855 | ||
1856 | .map_sg = arm_iommu_map_sg, | |
1857 | .unmap_sg = arm_iommu_unmap_sg, | |
1858 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1859 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
d09e1333 HD |
1860 | |
1861 | .set_dma_mask = arm_dma_set_mask, | |
4ce63fcd MS |
1862 | }; |
1863 | ||
0fa478df RH |
1864 | struct dma_map_ops iommu_coherent_ops = { |
1865 | .alloc = arm_iommu_alloc_attrs, | |
1866 | .free = arm_iommu_free_attrs, | |
1867 | .mmap = arm_iommu_mmap_attrs, | |
1868 | .get_sgtable = arm_iommu_get_sgtable, | |
1869 | ||
1870 | .map_page = arm_coherent_iommu_map_page, | |
1871 | .unmap_page = arm_coherent_iommu_unmap_page, | |
1872 | ||
1873 | .map_sg = arm_coherent_iommu_map_sg, | |
1874 | .unmap_sg = arm_coherent_iommu_unmap_sg, | |
d09e1333 HD |
1875 | |
1876 | .set_dma_mask = arm_dma_set_mask, | |
0fa478df RH |
1877 | }; |
1878 | ||
4ce63fcd MS |
1879 | /** |
1880 | * arm_iommu_create_mapping | |
1881 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1882 | * @base: start address of the valid IO address space | |
68efd7d2 | 1883 | * @size: maximum size of the valid IO address space |
4ce63fcd MS |
1884 | * |
1885 | * Creates a mapping structure which holds information about used/unused | |
1886 | * IO address ranges, which is required to perform memory allocation and | |
1887 | * mapping with IOMMU aware functions. | |
1888 | * | |
1889 | * The client device need to be attached to the mapping with | |
1890 | * arm_iommu_attach_device function. | |
1891 | */ | |
1892 | struct dma_iommu_mapping * | |
1424532b | 1893 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size) |
4ce63fcd | 1894 | { |
68efd7d2 MS |
1895 | unsigned int bits = size >> PAGE_SHIFT; |
1896 | unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); | |
4ce63fcd | 1897 | struct dma_iommu_mapping *mapping; |
68efd7d2 | 1898 | int extensions = 1; |
4ce63fcd MS |
1899 | int err = -ENOMEM; |
1900 | ||
1424532b MS |
1901 | /* currently only 32-bit DMA address space is supported */ |
1902 | if (size > DMA_BIT_MASK(32) + 1) | |
1903 | return ERR_PTR(-ERANGE); | |
1904 | ||
68efd7d2 | 1905 | if (!bitmap_size) |
4ce63fcd MS |
1906 | return ERR_PTR(-EINVAL); |
1907 | ||
68efd7d2 MS |
1908 | if (bitmap_size > PAGE_SIZE) { |
1909 | extensions = bitmap_size / PAGE_SIZE; | |
1910 | bitmap_size = PAGE_SIZE; | |
1911 | } | |
1912 | ||
4ce63fcd MS |
1913 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); |
1914 | if (!mapping) | |
1915 | goto err; | |
1916 | ||
68efd7d2 MS |
1917 | mapping->bitmap_size = bitmap_size; |
1918 | mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *), | |
4d852ef8 AH |
1919 | GFP_KERNEL); |
1920 | if (!mapping->bitmaps) | |
4ce63fcd MS |
1921 | goto err2; |
1922 | ||
68efd7d2 | 1923 | mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL); |
4d852ef8 AH |
1924 | if (!mapping->bitmaps[0]) |
1925 | goto err3; | |
1926 | ||
1927 | mapping->nr_bitmaps = 1; | |
1928 | mapping->extensions = extensions; | |
4ce63fcd | 1929 | mapping->base = base; |
68efd7d2 | 1930 | mapping->bits = BITS_PER_BYTE * bitmap_size; |
4d852ef8 | 1931 | |
4ce63fcd MS |
1932 | spin_lock_init(&mapping->lock); |
1933 | ||
1934 | mapping->domain = iommu_domain_alloc(bus); | |
1935 | if (!mapping->domain) | |
4d852ef8 | 1936 | goto err4; |
4ce63fcd MS |
1937 | |
1938 | kref_init(&mapping->kref); | |
1939 | return mapping; | |
4d852ef8 AH |
1940 | err4: |
1941 | kfree(mapping->bitmaps[0]); | |
4ce63fcd | 1942 | err3: |
4d852ef8 | 1943 | kfree(mapping->bitmaps); |
4ce63fcd MS |
1944 | err2: |
1945 | kfree(mapping); | |
1946 | err: | |
1947 | return ERR_PTR(err); | |
1948 | } | |
18177d12 | 1949 | EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); |
4ce63fcd MS |
1950 | |
1951 | static void release_iommu_mapping(struct kref *kref) | |
1952 | { | |
4d852ef8 | 1953 | int i; |
4ce63fcd MS |
1954 | struct dma_iommu_mapping *mapping = |
1955 | container_of(kref, struct dma_iommu_mapping, kref); | |
1956 | ||
1957 | iommu_domain_free(mapping->domain); | |
4d852ef8 AH |
1958 | for (i = 0; i < mapping->nr_bitmaps; i++) |
1959 | kfree(mapping->bitmaps[i]); | |
1960 | kfree(mapping->bitmaps); | |
4ce63fcd MS |
1961 | kfree(mapping); |
1962 | } | |
1963 | ||
4d852ef8 AH |
1964 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) |
1965 | { | |
1966 | int next_bitmap; | |
1967 | ||
462859aa | 1968 | if (mapping->nr_bitmaps >= mapping->extensions) |
4d852ef8 AH |
1969 | return -EINVAL; |
1970 | ||
1971 | next_bitmap = mapping->nr_bitmaps; | |
1972 | mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size, | |
1973 | GFP_ATOMIC); | |
1974 | if (!mapping->bitmaps[next_bitmap]) | |
1975 | return -ENOMEM; | |
1976 | ||
1977 | mapping->nr_bitmaps++; | |
1978 | ||
1979 | return 0; | |
1980 | } | |
1981 | ||
4ce63fcd MS |
1982 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) |
1983 | { | |
1984 | if (mapping) | |
1985 | kref_put(&mapping->kref, release_iommu_mapping); | |
1986 | } | |
18177d12 | 1987 | EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); |
4ce63fcd | 1988 | |
eab8d653 LP |
1989 | static int __arm_iommu_attach_device(struct device *dev, |
1990 | struct dma_iommu_mapping *mapping) | |
1991 | { | |
1992 | int err; | |
1993 | ||
1994 | err = iommu_attach_device(mapping->domain, dev); | |
1995 | if (err) | |
1996 | return err; | |
1997 | ||
1998 | kref_get(&mapping->kref); | |
89cfdb19 | 1999 | to_dma_iommu_mapping(dev) = mapping; |
eab8d653 LP |
2000 | |
2001 | pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
2002 | return 0; | |
2003 | } | |
2004 | ||
4ce63fcd MS |
2005 | /** |
2006 | * arm_iommu_attach_device | |
2007 | * @dev: valid struct device pointer | |
2008 | * @mapping: io address space mapping structure (returned from | |
2009 | * arm_iommu_create_mapping) | |
2010 | * | |
eab8d653 LP |
2011 | * Attaches specified io address space mapping to the provided device. |
2012 | * This replaces the dma operations (dma_map_ops pointer) with the | |
2013 | * IOMMU aware version. | |
2014 | * | |
4bb25789 WD |
2015 | * More than one client might be attached to the same io address space |
2016 | * mapping. | |
4ce63fcd MS |
2017 | */ |
2018 | int arm_iommu_attach_device(struct device *dev, | |
2019 | struct dma_iommu_mapping *mapping) | |
2020 | { | |
2021 | int err; | |
2022 | ||
eab8d653 | 2023 | err = __arm_iommu_attach_device(dev, mapping); |
4ce63fcd MS |
2024 | if (err) |
2025 | return err; | |
2026 | ||
eab8d653 | 2027 | set_dma_ops(dev, &iommu_ops); |
4ce63fcd MS |
2028 | return 0; |
2029 | } | |
18177d12 | 2030 | EXPORT_SYMBOL_GPL(arm_iommu_attach_device); |
4ce63fcd | 2031 | |
eab8d653 | 2032 | static void __arm_iommu_detach_device(struct device *dev) |
6fe36758 HD |
2033 | { |
2034 | struct dma_iommu_mapping *mapping; | |
2035 | ||
2036 | mapping = to_dma_iommu_mapping(dev); | |
2037 | if (!mapping) { | |
2038 | dev_warn(dev, "Not attached\n"); | |
2039 | return; | |
2040 | } | |
2041 | ||
2042 | iommu_detach_device(mapping->domain, dev); | |
2043 | kref_put(&mapping->kref, release_iommu_mapping); | |
89cfdb19 | 2044 | to_dma_iommu_mapping(dev) = NULL; |
6fe36758 HD |
2045 | |
2046 | pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); | |
2047 | } | |
eab8d653 LP |
2048 | |
2049 | /** | |
2050 | * arm_iommu_detach_device | |
2051 | * @dev: valid struct device pointer | |
2052 | * | |
2053 | * Detaches the provided device from a previously attached map. | |
2054 | * This voids the dma operations (dma_map_ops pointer) | |
2055 | */ | |
2056 | void arm_iommu_detach_device(struct device *dev) | |
2057 | { | |
2058 | __arm_iommu_detach_device(dev); | |
2059 | set_dma_ops(dev, NULL); | |
2060 | } | |
18177d12 | 2061 | EXPORT_SYMBOL_GPL(arm_iommu_detach_device); |
6fe36758 | 2062 | |
4bb25789 WD |
2063 | static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent) |
2064 | { | |
2065 | return coherent ? &iommu_coherent_ops : &iommu_ops; | |
2066 | } | |
2067 | ||
2068 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
2069 | struct iommu_ops *iommu) | |
2070 | { | |
2071 | struct dma_iommu_mapping *mapping; | |
2072 | ||
2073 | if (!iommu) | |
2074 | return false; | |
2075 | ||
2076 | mapping = arm_iommu_create_mapping(dev->bus, dma_base, size); | |
2077 | if (IS_ERR(mapping)) { | |
2078 | pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n", | |
2079 | size, dev_name(dev)); | |
2080 | return false; | |
2081 | } | |
2082 | ||
eab8d653 | 2083 | if (__arm_iommu_attach_device(dev, mapping)) { |
4bb25789 WD |
2084 | pr_warn("Failed to attached device %s to IOMMU_mapping\n", |
2085 | dev_name(dev)); | |
2086 | arm_iommu_release_mapping(mapping); | |
2087 | return false; | |
2088 | } | |
2089 | ||
2090 | return true; | |
2091 | } | |
2092 | ||
2093 | static void arm_teardown_iommu_dma_ops(struct device *dev) | |
2094 | { | |
89cfdb19 | 2095 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4bb25789 | 2096 | |
c2273a18 WD |
2097 | if (!mapping) |
2098 | return; | |
2099 | ||
eab8d653 | 2100 | __arm_iommu_detach_device(dev); |
4bb25789 WD |
2101 | arm_iommu_release_mapping(mapping); |
2102 | } | |
2103 | ||
2104 | #else | |
2105 | ||
2106 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
2107 | struct iommu_ops *iommu) | |
2108 | { | |
2109 | return false; | |
2110 | } | |
2111 | ||
2112 | static void arm_teardown_iommu_dma_ops(struct device *dev) { } | |
2113 | ||
2114 | #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops | |
2115 | ||
2116 | #endif /* CONFIG_ARM_DMA_USE_IOMMU */ | |
2117 | ||
2118 | static struct dma_map_ops *arm_get_dma_map_ops(bool coherent) | |
2119 | { | |
2120 | return coherent ? &arm_coherent_dma_ops : &arm_dma_ops; | |
2121 | } | |
2122 | ||
2123 | void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
2124 | struct iommu_ops *iommu, bool coherent) | |
2125 | { | |
2126 | struct dma_map_ops *dma_ops; | |
2127 | ||
6f51ee70 | 2128 | dev->archdata.dma_coherent = coherent; |
4bb25789 WD |
2129 | if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) |
2130 | dma_ops = arm_get_iommu_dma_map_ops(coherent); | |
2131 | else | |
2132 | dma_ops = arm_get_dma_map_ops(coherent); | |
2133 | ||
2134 | set_dma_ops(dev, dma_ops); | |
2135 | } | |
2136 | ||
2137 | void arch_teardown_dma_ops(struct device *dev) | |
2138 | { | |
2139 | arm_teardown_iommu_dma_ops(dev); | |
2140 | } |