Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
c7909509 | 20 | #include <linux/dma-contiguous.h> |
39af22a7 | 21 | #include <linux/highmem.h> |
c7909509 | 22 | #include <linux/memblock.h> |
99d1717d | 23 | #include <linux/slab.h> |
4ce63fcd | 24 | #include <linux/iommu.h> |
e9da6e99 | 25 | #include <linux/io.h> |
4ce63fcd | 26 | #include <linux/vmalloc.h> |
158e8bfe | 27 | #include <linux/sizes.h> |
1da177e4 | 28 | |
23759dc6 | 29 | #include <asm/memory.h> |
43377453 | 30 | #include <asm/highmem.h> |
1da177e4 | 31 | #include <asm/cacheflush.h> |
1da177e4 | 32 | #include <asm/tlbflush.h> |
99d1717d | 33 | #include <asm/mach/arch.h> |
4ce63fcd | 34 | #include <asm/dma-iommu.h> |
c7909509 MS |
35 | #include <asm/mach/map.h> |
36 | #include <asm/system_info.h> | |
37 | #include <asm/dma-contiguous.h> | |
37134cd5 | 38 | |
022ae537 RK |
39 | #include "mm.h" |
40 | ||
15237e1f MS |
41 | /* |
42 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
43 | * is either exclusively owned by the CPU (and therefore may be accessed | |
44 | * by it) or exclusively owned by the DMA device. These helper functions | |
45 | * represent the transitions between these two ownership states. | |
46 | * | |
47 | * Note, however, that on later ARMs, this notion does not work due to | |
48 | * speculative prefetches. We model our approach on the assumption that | |
49 | * the CPU does do speculative prefetches, which means we clean caches | |
50 | * before transfers and delay cache invalidation until transfer completion. | |
51 | * | |
15237e1f | 52 | */ |
51fde349 | 53 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 54 | size_t, enum dma_data_direction); |
51fde349 | 55 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
56 | size_t, enum dma_data_direction); |
57 | ||
2dc6a016 MS |
58 | /** |
59 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
60 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
61 | * @page: page that buffer resides in | |
62 | * @offset: offset into page for start of buffer | |
63 | * @size: size of buffer to map | |
64 | * @dir: DMA transfer direction | |
65 | * | |
66 | * Ensure that any data held in the cache is appropriately discarded | |
67 | * or written back. | |
68 | * | |
69 | * The device owns this memory once this call has completed. The CPU | |
70 | * can regain ownership by calling dma_unmap_page(). | |
71 | */ | |
51fde349 | 72 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
73 | unsigned long offset, size_t size, enum dma_data_direction dir, |
74 | struct dma_attrs *attrs) | |
75 | { | |
97ef952a | 76 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
77 | __dma_page_cpu_to_dev(page, offset, size, dir); |
78 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
79 | } |
80 | ||
81 | /** | |
82 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
83 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
84 | * @handle: DMA address of buffer | |
85 | * @size: size of buffer (same as passed to dma_map_page) | |
86 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
87 | * | |
88 | * Unmap a page streaming mode DMA translation. The handle and size | |
89 | * must match what was provided in the previous dma_map_page() call. | |
90 | * All other usages are undefined. | |
91 | * | |
92 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
93 | * whatever the device wrote there. | |
94 | */ | |
51fde349 | 95 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
96 | size_t size, enum dma_data_direction dir, |
97 | struct dma_attrs *attrs) | |
98 | { | |
97ef952a | 99 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
100 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
101 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
102 | } |
103 | ||
51fde349 | 104 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
105 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
106 | { | |
107 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
108 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
109 | if (!arch_is_coherent()) |
110 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
2dc6a016 MS |
111 | } |
112 | ||
51fde349 | 113 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
114 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
115 | { | |
116 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
117 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
118 | if (!arch_is_coherent()) |
119 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
2dc6a016 MS |
120 | } |
121 | ||
122 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask); | |
123 | ||
124 | struct dma_map_ops arm_dma_ops = { | |
f99d6034 MS |
125 | .alloc = arm_dma_alloc, |
126 | .free = arm_dma_free, | |
127 | .mmap = arm_dma_mmap, | |
dc2832e1 | 128 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
129 | .map_page = arm_dma_map_page, |
130 | .unmap_page = arm_dma_unmap_page, | |
131 | .map_sg = arm_dma_map_sg, | |
132 | .unmap_sg = arm_dma_unmap_sg, | |
133 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
134 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
135 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
136 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
137 | .set_dma_mask = arm_dma_set_mask, | |
138 | }; | |
139 | EXPORT_SYMBOL(arm_dma_ops); | |
140 | ||
ab6494f0 CM |
141 | static u64 get_coherent_dma_mask(struct device *dev) |
142 | { | |
022ae537 | 143 | u64 mask = (u64)arm_dma_limit; |
ab6494f0 CM |
144 | |
145 | if (dev) { | |
146 | mask = dev->coherent_dma_mask; | |
147 | ||
148 | /* | |
149 | * Sanity check the DMA mask - it must be non-zero, and | |
150 | * must be able to be satisfied by a DMA allocation. | |
151 | */ | |
152 | if (mask == 0) { | |
153 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
154 | return 0; | |
155 | } | |
156 | ||
022ae537 | 157 | if ((~mask) & (u64)arm_dma_limit) { |
ab6494f0 CM |
158 | dev_warn(dev, "coherent DMA mask %#llx is smaller " |
159 | "than system GFP_DMA mask %#llx\n", | |
022ae537 | 160 | mask, (u64)arm_dma_limit); |
ab6494f0 CM |
161 | return 0; |
162 | } | |
163 | } | |
1da177e4 | 164 | |
ab6494f0 CM |
165 | return mask; |
166 | } | |
167 | ||
c7909509 MS |
168 | static void __dma_clear_buffer(struct page *page, size_t size) |
169 | { | |
170 | void *ptr; | |
171 | /* | |
172 | * Ensure that the allocated pages are zeroed, and that any data | |
173 | * lurking in the kernel direct-mapped region is invalidated. | |
174 | */ | |
175 | ptr = page_address(page); | |
4ce63fcd MS |
176 | if (ptr) { |
177 | memset(ptr, 0, size); | |
178 | dmac_flush_range(ptr, ptr + size); | |
179 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
180 | } | |
c7909509 MS |
181 | } |
182 | ||
7a9a32a9 RK |
183 | /* |
184 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
185 | * specified gfp mask. Note that 'size' must be page aligned. | |
186 | */ | |
187 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
188 | { | |
189 | unsigned long order = get_order(size); | |
190 | struct page *page, *p, *e; | |
7a9a32a9 RK |
191 | |
192 | page = alloc_pages(gfp, order); | |
193 | if (!page) | |
194 | return NULL; | |
195 | ||
196 | /* | |
197 | * Now split the huge page and free the excess pages | |
198 | */ | |
199 | split_page(page, order); | |
200 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
201 | __free_page(p); | |
202 | ||
c7909509 | 203 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
204 | |
205 | return page; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Free a DMA buffer. 'size' must be page aligned. | |
210 | */ | |
211 | static void __dma_free_buffer(struct page *page, size_t size) | |
212 | { | |
213 | struct page *e = page + (size >> PAGE_SHIFT); | |
214 | ||
215 | while (page < e) { | |
216 | __free_page(page); | |
217 | page++; | |
218 | } | |
219 | } | |
220 | ||
ab6494f0 | 221 | #ifdef CONFIG_MMU |
e9da6e99 MS |
222 | #ifdef CONFIG_HUGETLB_PAGE |
223 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
224 | #endif | |
a5e9d38b | 225 | |
e9da6e99 MS |
226 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
227 | pgprot_t prot, struct page **ret_page); | |
99d1717d | 228 | |
e9da6e99 MS |
229 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
230 | pgprot_t prot, struct page **ret_page, | |
231 | const void *caller); | |
99d1717d | 232 | |
e9da6e99 MS |
233 | static void * |
234 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
235 | const void *caller) | |
99d1717d | 236 | { |
e9da6e99 MS |
237 | struct vm_struct *area; |
238 | unsigned long addr; | |
99d1717d | 239 | |
e9da6e99 MS |
240 | /* |
241 | * DMA allocation can be mapped to user space, so lets | |
242 | * set VM_USERMAP flags too. | |
243 | */ | |
244 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
245 | caller); | |
246 | if (!area) | |
247 | return NULL; | |
248 | addr = (unsigned long)area->addr; | |
249 | area->phys_addr = __pfn_to_phys(page_to_pfn(page)); | |
99d1717d | 250 | |
e9da6e99 MS |
251 | if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) { |
252 | vunmap((void *)addr); | |
253 | return NULL; | |
254 | } | |
255 | return (void *)addr; | |
99d1717d | 256 | } |
1da177e4 | 257 | |
e9da6e99 | 258 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 259 | { |
e9da6e99 MS |
260 | unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP; |
261 | struct vm_struct *area = find_vm_area(cpu_addr); | |
262 | if (!area || (area->flags & flags) != flags) { | |
263 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
264 | return; | |
99d1717d | 265 | } |
e9da6e99 MS |
266 | unmap_kernel_range((unsigned long)cpu_addr, size); |
267 | vunmap(cpu_addr); | |
88c58f3b | 268 | } |
88c58f3b | 269 | |
6e5267aa MS |
270 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
271 | ||
e9da6e99 MS |
272 | struct dma_pool { |
273 | size_t size; | |
274 | spinlock_t lock; | |
275 | unsigned long *bitmap; | |
276 | unsigned long nr_pages; | |
277 | void *vaddr; | |
6b3fe472 | 278 | struct page **pages; |
c7909509 MS |
279 | }; |
280 | ||
e9da6e99 | 281 | static struct dma_pool atomic_pool = { |
6e5267aa | 282 | .size = DEFAULT_DMA_COHERENT_POOL_SIZE, |
e9da6e99 | 283 | }; |
c7909509 MS |
284 | |
285 | static int __init early_coherent_pool(char *p) | |
286 | { | |
e9da6e99 | 287 | atomic_pool.size = memparse(p, &p); |
c7909509 MS |
288 | return 0; |
289 | } | |
290 | early_param("coherent_pool", early_coherent_pool); | |
291 | ||
6e5267aa MS |
292 | void __init init_dma_coherent_pool_size(unsigned long size) |
293 | { | |
294 | /* | |
295 | * Catch any attempt to set the pool size too late. | |
296 | */ | |
297 | BUG_ON(atomic_pool.vaddr); | |
298 | ||
299 | /* | |
300 | * Set architecture specific coherent pool size only if | |
301 | * it has not been changed by kernel command line parameter. | |
302 | */ | |
303 | if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE) | |
304 | atomic_pool.size = size; | |
305 | } | |
306 | ||
c7909509 MS |
307 | /* |
308 | * Initialise the coherent pool for atomic allocations. | |
309 | */ | |
e9da6e99 | 310 | static int __init atomic_pool_init(void) |
c7909509 | 311 | { |
e9da6e99 | 312 | struct dma_pool *pool = &atomic_pool; |
c7909509 | 313 | pgprot_t prot = pgprot_dmacoherent(pgprot_kernel); |
e9da6e99 MS |
314 | unsigned long nr_pages = pool->size >> PAGE_SHIFT; |
315 | unsigned long *bitmap; | |
c7909509 | 316 | struct page *page; |
6b3fe472 | 317 | struct page **pages; |
c7909509 | 318 | void *ptr; |
e9da6e99 | 319 | int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long); |
c7909509 | 320 | |
e9da6e99 MS |
321 | bitmap = kzalloc(bitmap_size, GFP_KERNEL); |
322 | if (!bitmap) | |
323 | goto no_bitmap; | |
c7909509 | 324 | |
6b3fe472 HD |
325 | pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); |
326 | if (!pages) | |
327 | goto no_pages; | |
328 | ||
e9da6e99 MS |
329 | if (IS_ENABLED(CONFIG_CMA)) |
330 | ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page); | |
331 | else | |
332 | ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot, | |
333 | &page, NULL); | |
c7909509 | 334 | if (ptr) { |
6b3fe472 HD |
335 | int i; |
336 | ||
337 | for (i = 0; i < nr_pages; i++) | |
338 | pages[i] = page + i; | |
339 | ||
e9da6e99 MS |
340 | spin_lock_init(&pool->lock); |
341 | pool->vaddr = ptr; | |
6b3fe472 | 342 | pool->pages = pages; |
e9da6e99 MS |
343 | pool->bitmap = bitmap; |
344 | pool->nr_pages = nr_pages; | |
345 | pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n", | |
346 | (unsigned)pool->size / 1024); | |
c7909509 MS |
347 | return 0; |
348 | } | |
6b3fe472 | 349 | no_pages: |
e9da6e99 MS |
350 | kfree(bitmap); |
351 | no_bitmap: | |
352 | pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", | |
353 | (unsigned)pool->size / 1024); | |
c7909509 MS |
354 | return -ENOMEM; |
355 | } | |
356 | /* | |
357 | * CMA is activated by core_initcall, so we must be called after it. | |
358 | */ | |
e9da6e99 | 359 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
360 | |
361 | struct dma_contig_early_reserve { | |
362 | phys_addr_t base; | |
363 | unsigned long size; | |
364 | }; | |
365 | ||
366 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
367 | ||
368 | static int dma_mmu_remap_num __initdata; | |
369 | ||
370 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
371 | { | |
372 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
373 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
374 | dma_mmu_remap_num++; | |
375 | } | |
376 | ||
377 | void __init dma_contiguous_remap(void) | |
378 | { | |
379 | int i; | |
380 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
381 | phys_addr_t start = dma_mmu_remap[i].base; | |
382 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
383 | struct map_desc map; | |
384 | unsigned long addr; | |
385 | ||
386 | if (end > arm_lowmem_limit) | |
387 | end = arm_lowmem_limit; | |
388 | if (start >= end) | |
39f78e70 | 389 | continue; |
c7909509 MS |
390 | |
391 | map.pfn = __phys_to_pfn(start); | |
392 | map.virtual = __phys_to_virt(start); | |
393 | map.length = end - start; | |
394 | map.type = MT_MEMORY_DMA_READY; | |
395 | ||
396 | /* | |
397 | * Clear previous low-memory mapping | |
398 | */ | |
399 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 400 | addr += PMD_SIZE) |
c7909509 MS |
401 | pmd_clear(pmd_off_k(addr)); |
402 | ||
403 | iotable_init(&map, 1); | |
404 | } | |
405 | } | |
406 | ||
c7909509 MS |
407 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
408 | void *data) | |
409 | { | |
410 | struct page *page = virt_to_page(addr); | |
411 | pgprot_t prot = *(pgprot_t *)data; | |
412 | ||
413 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
418 | { | |
419 | unsigned long start = (unsigned long) page_address(page); | |
420 | unsigned end = start + size; | |
421 | ||
422 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
423 | dsb(); | |
424 | flush_tlb_kernel_range(start, end); | |
425 | } | |
426 | ||
427 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
428 | pgprot_t prot, struct page **ret_page, | |
429 | const void *caller) | |
430 | { | |
431 | struct page *page; | |
432 | void *ptr; | |
433 | page = __dma_alloc_buffer(dev, size, gfp); | |
434 | if (!page) | |
435 | return NULL; | |
436 | ||
437 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
438 | if (!ptr) { | |
439 | __dma_free_buffer(page, size); | |
440 | return NULL; | |
441 | } | |
442 | ||
443 | *ret_page = page; | |
444 | return ptr; | |
445 | } | |
446 | ||
e9da6e99 | 447 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 448 | { |
e9da6e99 MS |
449 | struct dma_pool *pool = &atomic_pool; |
450 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
451 | unsigned int pageno; | |
452 | unsigned long flags; | |
453 | void *ptr = NULL; | |
e4ea6918 | 454 | unsigned long align_mask; |
c7909509 | 455 | |
e9da6e99 MS |
456 | if (!pool->vaddr) { |
457 | WARN(1, "coherent pool not initialised!\n"); | |
c7909509 MS |
458 | return NULL; |
459 | } | |
460 | ||
461 | /* | |
462 | * Align the region allocation - allocations from pool are rather | |
463 | * small, so align them to their order in pages, minimum is a page | |
464 | * size. This helps reduce fragmentation of the DMA space. | |
465 | */ | |
e4ea6918 | 466 | align_mask = (1 << get_order(size)) - 1; |
e9da6e99 MS |
467 | |
468 | spin_lock_irqsave(&pool->lock, flags); | |
469 | pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages, | |
e4ea6918 | 470 | 0, count, align_mask); |
e9da6e99 MS |
471 | if (pageno < pool->nr_pages) { |
472 | bitmap_set(pool->bitmap, pageno, count); | |
473 | ptr = pool->vaddr + PAGE_SIZE * pageno; | |
6b3fe472 | 474 | *ret_page = pool->pages[pageno]; |
fb71285f MS |
475 | } else { |
476 | pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n" | |
477 | "Please increase it with coherent_pool= kernel parameter!\n", | |
478 | (unsigned)pool->size / 1024); | |
c7909509 | 479 | } |
e9da6e99 MS |
480 | spin_unlock_irqrestore(&pool->lock, flags); |
481 | ||
482 | return ptr; | |
c7909509 MS |
483 | } |
484 | ||
21d0a759 HD |
485 | static bool __in_atomic_pool(void *start, size_t size) |
486 | { | |
487 | struct dma_pool *pool = &atomic_pool; | |
488 | void *end = start + size; | |
489 | void *pool_start = pool->vaddr; | |
490 | void *pool_end = pool->vaddr + pool->size; | |
491 | ||
492 | if (start < pool_start || start > pool_end) | |
493 | return false; | |
494 | ||
495 | if (end <= pool_end) | |
496 | return true; | |
497 | ||
498 | WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n", | |
499 | start, end - 1, pool_start, pool_end - 1); | |
500 | ||
501 | return false; | |
502 | } | |
503 | ||
e9da6e99 | 504 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 505 | { |
e9da6e99 MS |
506 | struct dma_pool *pool = &atomic_pool; |
507 | unsigned long pageno, count; | |
508 | unsigned long flags; | |
c7909509 | 509 | |
21d0a759 | 510 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
511 | return 0; |
512 | ||
e9da6e99 MS |
513 | pageno = (start - pool->vaddr) >> PAGE_SHIFT; |
514 | count = size >> PAGE_SHIFT; | |
515 | ||
516 | spin_lock_irqsave(&pool->lock, flags); | |
517 | bitmap_clear(pool->bitmap, pageno, count); | |
518 | spin_unlock_irqrestore(&pool->lock, flags); | |
519 | ||
c7909509 MS |
520 | return 1; |
521 | } | |
522 | ||
523 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
524 | pgprot_t prot, struct page **ret_page) | |
525 | { | |
526 | unsigned long order = get_order(size); | |
527 | size_t count = size >> PAGE_SHIFT; | |
528 | struct page *page; | |
529 | ||
530 | page = dma_alloc_from_contiguous(dev, count, order); | |
531 | if (!page) | |
532 | return NULL; | |
533 | ||
534 | __dma_clear_buffer(page, size); | |
535 | __dma_remap(page, size, prot); | |
536 | ||
537 | *ret_page = page; | |
538 | return page_address(page); | |
539 | } | |
540 | ||
541 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
542 | size_t size) | |
543 | { | |
544 | __dma_remap(page, size, pgprot_kernel); | |
545 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); | |
546 | } | |
547 | ||
f99d6034 MS |
548 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
549 | { | |
550 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
551 | pgprot_writecombine(prot) : | |
552 | pgprot_dmacoherent(prot); | |
553 | return prot; | |
554 | } | |
555 | ||
c7909509 MS |
556 | #define nommu() 0 |
557 | ||
ab6494f0 | 558 | #else /* !CONFIG_MMU */ |
695ae0af | 559 | |
c7909509 MS |
560 | #define nommu() 1 |
561 | ||
f99d6034 | 562 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
c7909509 | 563 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL |
e9da6e99 | 564 | #define __alloc_from_pool(size, ret_page) NULL |
c7909509 MS |
565 | #define __alloc_from_contiguous(dev, size, prot, ret) NULL |
566 | #define __free_from_pool(cpu_addr, size) 0 | |
567 | #define __free_from_contiguous(dev, page, size) do { } while (0) | |
568 | #define __dma_free_remap(cpu_addr, size) do { } while (0) | |
31ebf944 RK |
569 | |
570 | #endif /* CONFIG_MMU */ | |
571 | ||
c7909509 MS |
572 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
573 | struct page **ret_page) | |
ab6494f0 | 574 | { |
c7909509 MS |
575 | struct page *page; |
576 | page = __dma_alloc_buffer(dev, size, gfp); | |
577 | if (!page) | |
578 | return NULL; | |
579 | ||
580 | *ret_page = page; | |
581 | return page_address(page); | |
582 | } | |
583 | ||
584 | ||
585 | ||
586 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
587 | gfp_t gfp, pgprot_t prot, const void *caller) | |
588 | { | |
589 | u64 mask = get_coherent_dma_mask(dev); | |
04da5694 | 590 | struct page *page; |
31ebf944 | 591 | void *addr; |
ab6494f0 | 592 | |
c7909509 MS |
593 | #ifdef CONFIG_DMA_API_DEBUG |
594 | u64 limit = (mask + 1) & ~mask; | |
595 | if (limit && size >= limit) { | |
596 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
597 | size, mask); | |
598 | return NULL; | |
599 | } | |
600 | #endif | |
601 | ||
602 | if (!mask) | |
603 | return NULL; | |
604 | ||
605 | if (mask < 0xffffffffULL) | |
606 | gfp |= GFP_DMA; | |
607 | ||
ea2e7057 SB |
608 | /* |
609 | * Following is a work-around (a.k.a. hack) to prevent pages | |
610 | * with __GFP_COMP being passed to split_page() which cannot | |
611 | * handle them. The real problem is that this flag probably | |
612 | * should be 0 on ARM as it is not supported on this | |
613 | * platform; see CONFIG_HUGETLBFS. | |
614 | */ | |
615 | gfp &= ~(__GFP_COMP); | |
616 | ||
553ac788 | 617 | *handle = DMA_ERROR_CODE; |
04da5694 | 618 | size = PAGE_ALIGN(size); |
ab6494f0 | 619 | |
c7909509 MS |
620 | if (arch_is_coherent() || nommu()) |
621 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
e9da6e99 MS |
622 | else if (gfp & GFP_ATOMIC) |
623 | addr = __alloc_from_pool(size, &page); | |
f1ae98da | 624 | else if (!IS_ENABLED(CONFIG_CMA)) |
c7909509 | 625 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); |
31ebf944 | 626 | else |
c7909509 | 627 | addr = __alloc_from_contiguous(dev, size, prot, &page); |
695ae0af | 628 | |
31ebf944 | 629 | if (addr) |
9eedd963 | 630 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 631 | |
31ebf944 RK |
632 | return addr; |
633 | } | |
1da177e4 LT |
634 | |
635 | /* | |
636 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
637 | * virtual and bus address for that space. | |
638 | */ | |
f99d6034 MS |
639 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
640 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 641 | { |
f99d6034 | 642 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); |
1fe53268 DB |
643 | void *memory; |
644 | ||
645 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
646 | return memory; | |
647 | ||
f99d6034 | 648 | return __dma_alloc(dev, size, handle, gfp, prot, |
45cd5290 | 649 | __builtin_return_address(0)); |
1da177e4 | 650 | } |
1da177e4 LT |
651 | |
652 | /* | |
f99d6034 | 653 | * Create userspace mapping for the DMA-coherent memory. |
1da177e4 | 654 | */ |
f99d6034 MS |
655 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
656 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
657 | struct dma_attrs *attrs) | |
1da177e4 | 658 | { |
ab6494f0 CM |
659 | int ret = -ENXIO; |
660 | #ifdef CONFIG_MMU | |
50262a4b MS |
661 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
662 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 663 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
664 | unsigned long off = vma->vm_pgoff; |
665 | ||
f99d6034 MS |
666 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
667 | ||
47142f07 MS |
668 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
669 | return ret; | |
670 | ||
50262a4b MS |
671 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
672 | ret = remap_pfn_range(vma, vma->vm_start, | |
673 | pfn + off, | |
674 | vma->vm_end - vma->vm_start, | |
675 | vma->vm_page_prot); | |
676 | } | |
ab6494f0 | 677 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
678 | |
679 | return ret; | |
680 | } | |
681 | ||
1da177e4 | 682 | /* |
c7909509 | 683 | * Free a buffer as defined by the above mapping. |
1da177e4 | 684 | */ |
f99d6034 MS |
685 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
686 | dma_addr_t handle, struct dma_attrs *attrs) | |
1da177e4 | 687 | { |
c7909509 | 688 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
5edf71ae | 689 | |
1fe53268 DB |
690 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
691 | return; | |
692 | ||
3e82d012 RK |
693 | size = PAGE_ALIGN(size); |
694 | ||
c7909509 MS |
695 | if (arch_is_coherent() || nommu()) { |
696 | __dma_free_buffer(page, size); | |
d9e0d149 AK |
697 | } else if (__free_from_pool(cpu_addr, size)) { |
698 | return; | |
f1ae98da | 699 | } else if (!IS_ENABLED(CONFIG_CMA)) { |
695ae0af | 700 | __dma_free_remap(cpu_addr, size); |
c7909509 MS |
701 | __dma_free_buffer(page, size); |
702 | } else { | |
c7909509 MS |
703 | /* |
704 | * Non-atomic allocations cannot be freed with IRQs disabled | |
705 | */ | |
706 | WARN_ON(irqs_disabled()); | |
707 | __free_from_contiguous(dev, page, size); | |
708 | } | |
1da177e4 | 709 | } |
afd1a321 | 710 | |
dc2832e1 MS |
711 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
712 | void *cpu_addr, dma_addr_t handle, size_t size, | |
713 | struct dma_attrs *attrs) | |
714 | { | |
715 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
716 | int ret; | |
717 | ||
718 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
719 | if (unlikely(ret)) | |
720 | return ret; | |
721 | ||
722 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
723 | return 0; | |
724 | } | |
725 | ||
4ea0d737 | 726 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
727 | size_t size, enum dma_data_direction dir, |
728 | void (*op)(const void *, size_t, int)) | |
43377453 NP |
729 | { |
730 | /* | |
731 | * A single sg entry may refer to multiple physically contiguous | |
732 | * pages. But we still need to process highmem pages individually. | |
733 | * If highmem is not configured then the bulk of this loop gets | |
734 | * optimized out. | |
735 | */ | |
736 | size_t left = size; | |
737 | do { | |
738 | size_t len = left; | |
93f1d629 RK |
739 | void *vaddr; |
740 | ||
741 | if (PageHighMem(page)) { | |
742 | if (len + offset > PAGE_SIZE) { | |
743 | if (offset >= PAGE_SIZE) { | |
744 | page += offset / PAGE_SIZE; | |
745 | offset %= PAGE_SIZE; | |
746 | } | |
747 | len = PAGE_SIZE - offset; | |
748 | } | |
749 | vaddr = kmap_high_get(page); | |
750 | if (vaddr) { | |
751 | vaddr += offset; | |
a9c9147e | 752 | op(vaddr, len, dir); |
93f1d629 | 753 | kunmap_high(page); |
7e5a69e8 | 754 | } else if (cache_is_vipt()) { |
39af22a7 NP |
755 | /* unmapped pages might still be cached */ |
756 | vaddr = kmap_atomic(page); | |
7e5a69e8 | 757 | op(vaddr + offset, len, dir); |
39af22a7 | 758 | kunmap_atomic(vaddr); |
43377453 | 759 | } |
93f1d629 RK |
760 | } else { |
761 | vaddr = page_address(page) + offset; | |
a9c9147e | 762 | op(vaddr, len, dir); |
43377453 | 763 | } |
43377453 NP |
764 | offset = 0; |
765 | page++; | |
766 | left -= len; | |
767 | } while (left); | |
768 | } | |
4ea0d737 | 769 | |
51fde349 MS |
770 | /* |
771 | * Make an area consistent for devices. | |
772 | * Note: Drivers should NOT use this function directly, as it will break | |
773 | * platforms with CONFIG_DMABOUNCE. | |
774 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
775 | */ | |
776 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
777 | size_t size, enum dma_data_direction dir) |
778 | { | |
65af191a | 779 | unsigned long paddr; |
65af191a | 780 | |
a9c9147e | 781 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
782 | |
783 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
784 | if (dir == DMA_FROM_DEVICE) { |
785 | outer_inv_range(paddr, paddr + size); | |
786 | } else { | |
787 | outer_clean_range(paddr, paddr + size); | |
788 | } | |
789 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 790 | } |
4ea0d737 | 791 | |
51fde349 | 792 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
793 | size_t size, enum dma_data_direction dir) |
794 | { | |
2ffe2da3 RK |
795 | unsigned long paddr = page_to_phys(page) + off; |
796 | ||
797 | /* FIXME: non-speculating: not required */ | |
798 | /* don't bother invalidating if DMA to device */ | |
799 | if (dir != DMA_TO_DEVICE) | |
800 | outer_inv_range(paddr, paddr + size); | |
801 | ||
a9c9147e | 802 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
c0177800 CM |
803 | |
804 | /* | |
805 | * Mark the D-cache clean for this page to avoid extra flushing. | |
806 | */ | |
807 | if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) | |
808 | set_bit(PG_dcache_clean, &page->flags); | |
4ea0d737 | 809 | } |
43377453 | 810 | |
afd1a321 | 811 | /** |
2a550e73 | 812 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
813 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
814 | * @sg: list of buffers | |
815 | * @nents: number of buffers to map | |
816 | * @dir: DMA transfer direction | |
817 | * | |
818 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
819 | * This is the scatter-gather version of the dma_map_single interface. | |
820 | * Here the scatter gather list elements are each tagged with the | |
821 | * appropriate dma address and length. They are obtained via | |
822 | * sg_dma_{address,length}. | |
823 | * | |
824 | * Device ownership issues as mentioned for dma_map_single are the same | |
825 | * here. | |
826 | */ | |
2dc6a016 MS |
827 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
828 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 829 | { |
2a550e73 | 830 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 831 | struct scatterlist *s; |
01135d92 | 832 | int i, j; |
afd1a321 RK |
833 | |
834 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
835 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
836 | s->dma_length = s->length; | |
837 | #endif | |
2a550e73 MS |
838 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
839 | s->length, dir, attrs); | |
01135d92 RK |
840 | if (dma_mapping_error(dev, s->dma_address)) |
841 | goto bad_mapping; | |
afd1a321 | 842 | } |
afd1a321 | 843 | return nents; |
01135d92 RK |
844 | |
845 | bad_mapping: | |
846 | for_each_sg(sg, s, i, j) | |
2a550e73 | 847 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 848 | return 0; |
afd1a321 | 849 | } |
afd1a321 RK |
850 | |
851 | /** | |
2a550e73 | 852 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
853 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
854 | * @sg: list of buffers | |
0adfca6f | 855 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
856 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
857 | * | |
858 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
859 | * rules concerning calls here are the same as for dma_unmap_single(). | |
860 | */ | |
2dc6a016 MS |
861 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
862 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 863 | { |
2a550e73 | 864 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 865 | struct scatterlist *s; |
01135d92 | 866 | |
01135d92 | 867 | int i; |
24056f52 | 868 | |
01135d92 | 869 | for_each_sg(sg, s, nents, i) |
2a550e73 | 870 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 871 | } |
afd1a321 RK |
872 | |
873 | /** | |
2a550e73 | 874 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
875 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
876 | * @sg: list of buffers | |
877 | * @nents: number of buffers to map (returned from dma_map_sg) | |
878 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
879 | */ | |
2dc6a016 | 880 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
881 | int nents, enum dma_data_direction dir) |
882 | { | |
2a550e73 | 883 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
884 | struct scatterlist *s; |
885 | int i; | |
886 | ||
2a550e73 MS |
887 | for_each_sg(sg, s, nents, i) |
888 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
889 | dir); | |
afd1a321 | 890 | } |
afd1a321 RK |
891 | |
892 | /** | |
2a550e73 | 893 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
894 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
895 | * @sg: list of buffers | |
896 | * @nents: number of buffers to map (returned from dma_map_sg) | |
897 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
898 | */ | |
2dc6a016 | 899 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
900 | int nents, enum dma_data_direction dir) |
901 | { | |
2a550e73 | 902 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
903 | struct scatterlist *s; |
904 | int i; | |
905 | ||
2a550e73 MS |
906 | for_each_sg(sg, s, nents, i) |
907 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
908 | dir); | |
afd1a321 | 909 | } |
24056f52 | 910 | |
022ae537 RK |
911 | /* |
912 | * Return whether the given device DMA address mask can be supported | |
913 | * properly. For example, if your device can only drive the low 24-bits | |
914 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
915 | * to this function. | |
916 | */ | |
917 | int dma_supported(struct device *dev, u64 mask) | |
918 | { | |
919 | if (mask < (u64)arm_dma_limit) | |
920 | return 0; | |
921 | return 1; | |
922 | } | |
923 | EXPORT_SYMBOL(dma_supported); | |
924 | ||
2dc6a016 | 925 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
926 | { |
927 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
928 | return -EIO; | |
929 | ||
022ae537 | 930 | *dev->dma_mask = dma_mask; |
022ae537 RK |
931 | |
932 | return 0; | |
933 | } | |
022ae537 | 934 | |
24056f52 RK |
935 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
936 | ||
937 | static int __init dma_debug_do_init(void) | |
938 | { | |
939 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
940 | return 0; | |
941 | } | |
942 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
943 | |
944 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
945 | ||
946 | /* IOMMU */ | |
947 | ||
948 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, | |
949 | size_t size) | |
950 | { | |
951 | unsigned int order = get_order(size); | |
952 | unsigned int align = 0; | |
953 | unsigned int count, start; | |
954 | unsigned long flags; | |
955 | ||
956 | count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) + | |
957 | (1 << mapping->order) - 1) >> mapping->order; | |
958 | ||
959 | if (order > mapping->order) | |
960 | align = (1 << (order - mapping->order)) - 1; | |
961 | ||
962 | spin_lock_irqsave(&mapping->lock, flags); | |
963 | start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0, | |
964 | count, align); | |
965 | if (start > mapping->bits) { | |
966 | spin_unlock_irqrestore(&mapping->lock, flags); | |
967 | return DMA_ERROR_CODE; | |
968 | } | |
969 | ||
970 | bitmap_set(mapping->bitmap, start, count); | |
971 | spin_unlock_irqrestore(&mapping->lock, flags); | |
972 | ||
973 | return mapping->base + (start << (mapping->order + PAGE_SHIFT)); | |
974 | } | |
975 | ||
976 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
977 | dma_addr_t addr, size_t size) | |
978 | { | |
979 | unsigned int start = (addr - mapping->base) >> | |
980 | (mapping->order + PAGE_SHIFT); | |
981 | unsigned int count = ((size >> PAGE_SHIFT) + | |
982 | (1 << mapping->order) - 1) >> mapping->order; | |
983 | unsigned long flags; | |
984 | ||
985 | spin_lock_irqsave(&mapping->lock, flags); | |
986 | bitmap_clear(mapping->bitmap, start, count); | |
987 | spin_unlock_irqrestore(&mapping->lock, flags); | |
988 | } | |
989 | ||
990 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
991 | { | |
992 | struct page **pages; | |
993 | int count = size >> PAGE_SHIFT; | |
994 | int array_size = count * sizeof(struct page *); | |
995 | int i = 0; | |
996 | ||
997 | if (array_size <= PAGE_SIZE) | |
998 | pages = kzalloc(array_size, gfp); | |
999 | else | |
1000 | pages = vzalloc(array_size); | |
1001 | if (!pages) | |
1002 | return NULL; | |
1003 | ||
1004 | while (count) { | |
593f4735 | 1005 | int j, order = __fls(count); |
4ce63fcd MS |
1006 | |
1007 | pages[i] = alloc_pages(gfp | __GFP_NOWARN, order); | |
1008 | while (!pages[i] && order) | |
1009 | pages[i] = alloc_pages(gfp | __GFP_NOWARN, --order); | |
1010 | if (!pages[i]) | |
1011 | goto error; | |
1012 | ||
1013 | if (order) | |
1014 | split_page(pages[i], order); | |
1015 | j = 1 << order; | |
1016 | while (--j) | |
1017 | pages[i + j] = pages[i] + j; | |
1018 | ||
1019 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
1020 | i += 1 << order; | |
1021 | count -= 1 << order; | |
1022 | } | |
1023 | ||
1024 | return pages; | |
1025 | error: | |
9fa8af91 | 1026 | while (i--) |
4ce63fcd MS |
1027 | if (pages[i]) |
1028 | __free_pages(pages[i], 0); | |
46c87852 | 1029 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1030 | kfree(pages); |
1031 | else | |
1032 | vfree(pages); | |
1033 | return NULL; | |
1034 | } | |
1035 | ||
1036 | static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t size) | |
1037 | { | |
1038 | int count = size >> PAGE_SHIFT; | |
1039 | int array_size = count * sizeof(struct page *); | |
1040 | int i; | |
1041 | for (i = 0; i < count; i++) | |
1042 | if (pages[i]) | |
1043 | __free_pages(pages[i], 0); | |
46c87852 | 1044 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1045 | kfree(pages); |
1046 | else | |
1047 | vfree(pages); | |
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | /* | |
1052 | * Create a CPU mapping for a specified pages | |
1053 | */ | |
1054 | static void * | |
e9da6e99 MS |
1055 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1056 | const void *caller) | |
4ce63fcd | 1057 | { |
e9da6e99 MS |
1058 | unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1059 | struct vm_struct *area; | |
1060 | unsigned long p; | |
4ce63fcd | 1061 | |
e9da6e99 MS |
1062 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, |
1063 | caller); | |
1064 | if (!area) | |
4ce63fcd | 1065 | return NULL; |
4ce63fcd | 1066 | |
e9da6e99 MS |
1067 | area->pages = pages; |
1068 | area->nr_pages = nr_pages; | |
1069 | p = (unsigned long)area->addr; | |
4ce63fcd | 1070 | |
e9da6e99 MS |
1071 | for (i = 0; i < nr_pages; i++) { |
1072 | phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i])); | |
1073 | if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot)) | |
1074 | goto err; | |
1075 | p += PAGE_SIZE; | |
4ce63fcd | 1076 | } |
e9da6e99 MS |
1077 | return area->addr; |
1078 | err: | |
1079 | unmap_kernel_range((unsigned long)area->addr, size); | |
1080 | vunmap(area->addr); | |
4ce63fcd MS |
1081 | return NULL; |
1082 | } | |
1083 | ||
1084 | /* | |
1085 | * Create a mapping in device IO address space for specified pages | |
1086 | */ | |
1087 | static dma_addr_t | |
1088 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1089 | { | |
1090 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1091 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1092 | dma_addr_t dma_addr, iova; | |
1093 | int i, ret = DMA_ERROR_CODE; | |
1094 | ||
1095 | dma_addr = __alloc_iova(mapping, size); | |
1096 | if (dma_addr == DMA_ERROR_CODE) | |
1097 | return dma_addr; | |
1098 | ||
1099 | iova = dma_addr; | |
1100 | for (i = 0; i < count; ) { | |
1101 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; | |
1102 | phys_addr_t phys = page_to_phys(pages[i]); | |
1103 | unsigned int len, j; | |
1104 | ||
1105 | for (j = i + 1; j < count; j++, next_pfn++) | |
1106 | if (page_to_pfn(pages[j]) != next_pfn) | |
1107 | break; | |
1108 | ||
1109 | len = (j - i) << PAGE_SHIFT; | |
1110 | ret = iommu_map(mapping->domain, iova, phys, len, 0); | |
1111 | if (ret < 0) | |
1112 | goto fail; | |
1113 | iova += len; | |
1114 | i = j; | |
1115 | } | |
1116 | return dma_addr; | |
1117 | fail: | |
1118 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1119 | __free_iova(mapping, dma_addr, size); | |
1120 | return DMA_ERROR_CODE; | |
1121 | } | |
1122 | ||
1123 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1124 | { | |
1125 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1126 | ||
1127 | /* | |
1128 | * add optional in-page offset from iova to size and align | |
1129 | * result to page size | |
1130 | */ | |
1131 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1132 | iova &= PAGE_MASK; | |
1133 | ||
1134 | iommu_unmap(mapping->domain, iova, size); | |
1135 | __free_iova(mapping, iova, size); | |
1136 | return 0; | |
1137 | } | |
1138 | ||
955c757e | 1139 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) |
e9da6e99 MS |
1140 | { |
1141 | struct vm_struct *area; | |
1142 | ||
955c757e MS |
1143 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1144 | return cpu_addr; | |
1145 | ||
e9da6e99 MS |
1146 | area = find_vm_area(cpu_addr); |
1147 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1148 | return area->pages; | |
1149 | return NULL; | |
1150 | } | |
1151 | ||
4ce63fcd MS |
1152 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1153 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1154 | { | |
1155 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); | |
1156 | struct page **pages; | |
1157 | void *addr = NULL; | |
1158 | ||
1159 | *handle = DMA_ERROR_CODE; | |
1160 | size = PAGE_ALIGN(size); | |
1161 | ||
1162 | pages = __iommu_alloc_buffer(dev, size, gfp); | |
1163 | if (!pages) | |
1164 | return NULL; | |
1165 | ||
1166 | *handle = __iommu_create_mapping(dev, pages, size); | |
1167 | if (*handle == DMA_ERROR_CODE) | |
1168 | goto err_buffer; | |
1169 | ||
955c757e MS |
1170 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1171 | return pages; | |
1172 | ||
e9da6e99 MS |
1173 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1174 | __builtin_return_address(0)); | |
4ce63fcd MS |
1175 | if (!addr) |
1176 | goto err_mapping; | |
1177 | ||
1178 | return addr; | |
1179 | ||
1180 | err_mapping: | |
1181 | __iommu_remove_mapping(dev, *handle, size); | |
1182 | err_buffer: | |
1183 | __iommu_free_buffer(dev, pages, size); | |
1184 | return NULL; | |
1185 | } | |
1186 | ||
1187 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1188 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1189 | struct dma_attrs *attrs) | |
1190 | { | |
e9da6e99 MS |
1191 | unsigned long uaddr = vma->vm_start; |
1192 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1193 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1194 | |
1195 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1196 | |
e9da6e99 MS |
1197 | if (!pages) |
1198 | return -ENXIO; | |
4ce63fcd | 1199 | |
e9da6e99 MS |
1200 | do { |
1201 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1202 | if (ret) { | |
1203 | pr_err("Remapping memory failed: %d\n", ret); | |
1204 | return ret; | |
1205 | } | |
1206 | uaddr += PAGE_SIZE; | |
1207 | usize -= PAGE_SIZE; | |
1208 | } while (usize > 0); | |
4ce63fcd | 1209 | |
4ce63fcd MS |
1210 | return 0; |
1211 | } | |
1212 | ||
1213 | /* | |
1214 | * free a page as defined by the above mapping. | |
1215 | * Must not be called with IRQs disabled. | |
1216 | */ | |
1217 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1218 | dma_addr_t handle, struct dma_attrs *attrs) | |
1219 | { | |
955c757e | 1220 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1221 | size = PAGE_ALIGN(size); |
1222 | ||
e9da6e99 MS |
1223 | if (!pages) { |
1224 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
1225 | return; | |
4ce63fcd | 1226 | } |
e9da6e99 | 1227 | |
955c757e MS |
1228 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { |
1229 | unmap_kernel_range((unsigned long)cpu_addr, size); | |
1230 | vunmap(cpu_addr); | |
1231 | } | |
e9da6e99 MS |
1232 | |
1233 | __iommu_remove_mapping(dev, handle, size); | |
1234 | __iommu_free_buffer(dev, pages, size); | |
4ce63fcd MS |
1235 | } |
1236 | ||
dc2832e1 MS |
1237 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1238 | void *cpu_addr, dma_addr_t dma_addr, | |
1239 | size_t size, struct dma_attrs *attrs) | |
1240 | { | |
1241 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1242 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1243 | ||
1244 | if (!pages) | |
1245 | return -ENXIO; | |
1246 | ||
1247 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1248 | GFP_KERNEL); | |
4ce63fcd MS |
1249 | } |
1250 | ||
1251 | /* | |
1252 | * Map a part of the scatter-gather list into contiguous io address space | |
1253 | */ | |
1254 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1255 | size_t size, dma_addr_t *handle, | |
97ef952a | 1256 | enum dma_data_direction dir, struct dma_attrs *attrs) |
4ce63fcd MS |
1257 | { |
1258 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1259 | dma_addr_t iova, iova_base; | |
1260 | int ret = 0; | |
1261 | unsigned int count; | |
1262 | struct scatterlist *s; | |
1263 | ||
1264 | size = PAGE_ALIGN(size); | |
1265 | *handle = DMA_ERROR_CODE; | |
1266 | ||
1267 | iova_base = iova = __alloc_iova(mapping, size); | |
1268 | if (iova == DMA_ERROR_CODE) | |
1269 | return -ENOMEM; | |
1270 | ||
1271 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
1272 | phys_addr_t phys = page_to_phys(sg_page(s)); | |
1273 | unsigned int len = PAGE_ALIGN(s->offset + s->length); | |
1274 | ||
97ef952a MS |
1275 | if (!arch_is_coherent() && |
1276 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1277 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1278 | ||
1279 | ret = iommu_map(mapping->domain, iova, phys, len, 0); | |
1280 | if (ret < 0) | |
1281 | goto fail; | |
1282 | count += len >> PAGE_SHIFT; | |
1283 | iova += len; | |
1284 | } | |
1285 | *handle = iova_base; | |
1286 | ||
1287 | return 0; | |
1288 | fail: | |
1289 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1290 | __free_iova(mapping, iova_base, size); | |
1291 | return ret; | |
1292 | } | |
1293 | ||
1294 | /** | |
1295 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1296 | * @dev: valid struct device pointer | |
1297 | * @sg: list of buffers | |
1298 | * @nents: number of buffers to map | |
1299 | * @dir: DMA transfer direction | |
1300 | * | |
1301 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1302 | * The scatter gather list elements are merged together (if possible) and | |
1303 | * tagged with the appropriate dma address and length. They are obtained via | |
1304 | * sg_dma_{address,length}. | |
1305 | */ | |
1306 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1307 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1308 | { | |
1309 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1310 | int i, count = 0; | |
1311 | unsigned int offset = s->offset; | |
1312 | unsigned int size = s->offset + s->length; | |
1313 | unsigned int max = dma_get_max_seg_size(dev); | |
1314 | ||
1315 | for (i = 1; i < nents; i++) { | |
1316 | s = sg_next(s); | |
1317 | ||
1318 | s->dma_address = DMA_ERROR_CODE; | |
1319 | s->dma_length = 0; | |
1320 | ||
1321 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1322 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
97ef952a | 1323 | dir, attrs) < 0) |
4ce63fcd MS |
1324 | goto bad_mapping; |
1325 | ||
1326 | dma->dma_address += offset; | |
1327 | dma->dma_length = size - offset; | |
1328 | ||
1329 | size = offset = s->offset; | |
1330 | start = s; | |
1331 | dma = sg_next(dma); | |
1332 | count += 1; | |
1333 | } | |
1334 | size += s->length; | |
1335 | } | |
97ef952a | 1336 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs) < 0) |
4ce63fcd MS |
1337 | goto bad_mapping; |
1338 | ||
1339 | dma->dma_address += offset; | |
1340 | dma->dma_length = size - offset; | |
1341 | ||
1342 | return count+1; | |
1343 | ||
1344 | bad_mapping: | |
1345 | for_each_sg(sg, s, count, i) | |
1346 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | /** | |
1351 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1352 | * @dev: valid struct device pointer | |
1353 | * @sg: list of buffers | |
1354 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1355 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1356 | * | |
1357 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1358 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1359 | */ | |
1360 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1361 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1362 | { | |
1363 | struct scatterlist *s; | |
1364 | int i; | |
1365 | ||
1366 | for_each_sg(sg, s, nents, i) { | |
1367 | if (sg_dma_len(s)) | |
1368 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1369 | sg_dma_len(s)); | |
97ef952a MS |
1370 | if (!arch_is_coherent() && |
1371 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1372 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1373 | s->length, dir); | |
1374 | } | |
1375 | } | |
1376 | ||
1377 | /** | |
1378 | * arm_iommu_sync_sg_for_cpu | |
1379 | * @dev: valid struct device pointer | |
1380 | * @sg: list of buffers | |
1381 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1382 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1383 | */ | |
1384 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1385 | int nents, enum dma_data_direction dir) | |
1386 | { | |
1387 | struct scatterlist *s; | |
1388 | int i; | |
1389 | ||
1390 | for_each_sg(sg, s, nents, i) | |
1391 | if (!arch_is_coherent()) | |
1392 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); | |
1393 | ||
1394 | } | |
1395 | ||
1396 | /** | |
1397 | * arm_iommu_sync_sg_for_device | |
1398 | * @dev: valid struct device pointer | |
1399 | * @sg: list of buffers | |
1400 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1401 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1402 | */ | |
1403 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1404 | int nents, enum dma_data_direction dir) | |
1405 | { | |
1406 | struct scatterlist *s; | |
1407 | int i; | |
1408 | ||
1409 | for_each_sg(sg, s, nents, i) | |
1410 | if (!arch_is_coherent()) | |
1411 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); | |
1412 | } | |
1413 | ||
1414 | ||
1415 | /** | |
1416 | * arm_iommu_map_page | |
1417 | * @dev: valid struct device pointer | |
1418 | * @page: page that buffer resides in | |
1419 | * @offset: offset into page for start of buffer | |
1420 | * @size: size of buffer to map | |
1421 | * @dir: DMA transfer direction | |
1422 | * | |
1423 | * IOMMU aware version of arm_dma_map_page() | |
1424 | */ | |
1425 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1426 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1427 | struct dma_attrs *attrs) | |
1428 | { | |
1429 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1430 | dma_addr_t dma_addr; | |
1431 | int ret, len = PAGE_ALIGN(size + offset); | |
1432 | ||
97ef952a | 1433 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1434 | __dma_page_cpu_to_dev(page, offset, size, dir); |
1435 | ||
1436 | dma_addr = __alloc_iova(mapping, len); | |
1437 | if (dma_addr == DMA_ERROR_CODE) | |
1438 | return dma_addr; | |
1439 | ||
1440 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0); | |
1441 | if (ret < 0) | |
1442 | goto fail; | |
1443 | ||
1444 | return dma_addr + offset; | |
1445 | fail: | |
1446 | __free_iova(mapping, dma_addr, len); | |
1447 | return DMA_ERROR_CODE; | |
1448 | } | |
1449 | ||
1450 | /** | |
1451 | * arm_iommu_unmap_page | |
1452 | * @dev: valid struct device pointer | |
1453 | * @handle: DMA address of buffer | |
1454 | * @size: size of buffer (same as passed to dma_map_page) | |
1455 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1456 | * | |
1457 | * IOMMU aware version of arm_dma_unmap_page() | |
1458 | */ | |
1459 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1460 | size_t size, enum dma_data_direction dir, | |
1461 | struct dma_attrs *attrs) | |
1462 | { | |
1463 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1464 | dma_addr_t iova = handle & PAGE_MASK; | |
1465 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1466 | int offset = handle & ~PAGE_MASK; | |
1467 | int len = PAGE_ALIGN(size + offset); | |
1468 | ||
1469 | if (!iova) | |
1470 | return; | |
1471 | ||
97ef952a | 1472 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1473 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1474 | ||
1475 | iommu_unmap(mapping->domain, iova, len); | |
1476 | __free_iova(mapping, iova, len); | |
1477 | } | |
1478 | ||
1479 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1480 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1481 | { | |
1482 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1483 | dma_addr_t iova = handle & PAGE_MASK; | |
1484 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1485 | unsigned int offset = handle & ~PAGE_MASK; | |
1486 | ||
1487 | if (!iova) | |
1488 | return; | |
1489 | ||
1490 | if (!arch_is_coherent()) | |
1491 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
1492 | } | |
1493 | ||
1494 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1495 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1496 | { | |
1497 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1498 | dma_addr_t iova = handle & PAGE_MASK; | |
1499 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1500 | unsigned int offset = handle & ~PAGE_MASK; | |
1501 | ||
1502 | if (!iova) | |
1503 | return; | |
1504 | ||
1505 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1506 | } | |
1507 | ||
1508 | struct dma_map_ops iommu_ops = { | |
1509 | .alloc = arm_iommu_alloc_attrs, | |
1510 | .free = arm_iommu_free_attrs, | |
1511 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 1512 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
1513 | |
1514 | .map_page = arm_iommu_map_page, | |
1515 | .unmap_page = arm_iommu_unmap_page, | |
1516 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1517 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1518 | ||
1519 | .map_sg = arm_iommu_map_sg, | |
1520 | .unmap_sg = arm_iommu_unmap_sg, | |
1521 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1522 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
1523 | }; | |
1524 | ||
1525 | /** | |
1526 | * arm_iommu_create_mapping | |
1527 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1528 | * @base: start address of the valid IO address space | |
1529 | * @size: size of the valid IO address space | |
1530 | * @order: accuracy of the IO addresses allocations | |
1531 | * | |
1532 | * Creates a mapping structure which holds information about used/unused | |
1533 | * IO address ranges, which is required to perform memory allocation and | |
1534 | * mapping with IOMMU aware functions. | |
1535 | * | |
1536 | * The client device need to be attached to the mapping with | |
1537 | * arm_iommu_attach_device function. | |
1538 | */ | |
1539 | struct dma_iommu_mapping * | |
1540 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size, | |
1541 | int order) | |
1542 | { | |
1543 | unsigned int count = size >> (PAGE_SHIFT + order); | |
1544 | unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long); | |
1545 | struct dma_iommu_mapping *mapping; | |
1546 | int err = -ENOMEM; | |
1547 | ||
1548 | if (!count) | |
1549 | return ERR_PTR(-EINVAL); | |
1550 | ||
1551 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); | |
1552 | if (!mapping) | |
1553 | goto err; | |
1554 | ||
1555 | mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL); | |
1556 | if (!mapping->bitmap) | |
1557 | goto err2; | |
1558 | ||
1559 | mapping->base = base; | |
1560 | mapping->bits = BITS_PER_BYTE * bitmap_size; | |
1561 | mapping->order = order; | |
1562 | spin_lock_init(&mapping->lock); | |
1563 | ||
1564 | mapping->domain = iommu_domain_alloc(bus); | |
1565 | if (!mapping->domain) | |
1566 | goto err3; | |
1567 | ||
1568 | kref_init(&mapping->kref); | |
1569 | return mapping; | |
1570 | err3: | |
1571 | kfree(mapping->bitmap); | |
1572 | err2: | |
1573 | kfree(mapping); | |
1574 | err: | |
1575 | return ERR_PTR(err); | |
1576 | } | |
1577 | ||
1578 | static void release_iommu_mapping(struct kref *kref) | |
1579 | { | |
1580 | struct dma_iommu_mapping *mapping = | |
1581 | container_of(kref, struct dma_iommu_mapping, kref); | |
1582 | ||
1583 | iommu_domain_free(mapping->domain); | |
1584 | kfree(mapping->bitmap); | |
1585 | kfree(mapping); | |
1586 | } | |
1587 | ||
1588 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) | |
1589 | { | |
1590 | if (mapping) | |
1591 | kref_put(&mapping->kref, release_iommu_mapping); | |
1592 | } | |
1593 | ||
1594 | /** | |
1595 | * arm_iommu_attach_device | |
1596 | * @dev: valid struct device pointer | |
1597 | * @mapping: io address space mapping structure (returned from | |
1598 | * arm_iommu_create_mapping) | |
1599 | * | |
1600 | * Attaches specified io address space mapping to the provided device, | |
1601 | * this replaces the dma operations (dma_map_ops pointer) with the | |
1602 | * IOMMU aware version. More than one client might be attached to | |
1603 | * the same io address space mapping. | |
1604 | */ | |
1605 | int arm_iommu_attach_device(struct device *dev, | |
1606 | struct dma_iommu_mapping *mapping) | |
1607 | { | |
1608 | int err; | |
1609 | ||
1610 | err = iommu_attach_device(mapping->domain, dev); | |
1611 | if (err) | |
1612 | return err; | |
1613 | ||
1614 | kref_get(&mapping->kref); | |
1615 | dev->archdata.mapping = mapping; | |
1616 | set_dma_ops(dev, &iommu_ops); | |
1617 | ||
1618 | pr_info("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
1619 | return 0; | |
1620 | } | |
1621 | ||
1622 | #endif |