Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | ||
23759dc6 | 21 | #include <asm/memory.h> |
43377453 | 22 | #include <asm/highmem.h> |
1da177e4 | 23 | #include <asm/cacheflush.h> |
1da177e4 | 24 | #include <asm/tlbflush.h> |
37134cd5 KH |
25 | #include <asm/sizes.h> |
26 | ||
27 | /* Sanity check size */ | |
28 | #if (CONSISTENT_DMA_SIZE % SZ_2M) | |
29 | #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB" | |
30 | #endif | |
1da177e4 | 31 | |
1da177e4 | 32 | #define CONSISTENT_END (0xffe00000) |
37134cd5 KH |
33 | #define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE) |
34 | ||
1da177e4 | 35 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) |
37134cd5 KH |
36 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) |
37 | #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) | |
38 | ||
ab6494f0 CM |
39 | static u64 get_coherent_dma_mask(struct device *dev) |
40 | { | |
41 | u64 mask = ISA_DMA_THRESHOLD; | |
42 | ||
43 | if (dev) { | |
44 | mask = dev->coherent_dma_mask; | |
45 | ||
46 | /* | |
47 | * Sanity check the DMA mask - it must be non-zero, and | |
48 | * must be able to be satisfied by a DMA allocation. | |
49 | */ | |
50 | if (mask == 0) { | |
51 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
52 | return 0; | |
53 | } | |
54 | ||
55 | if ((~mask) & ISA_DMA_THRESHOLD) { | |
56 | dev_warn(dev, "coherent DMA mask %#llx is smaller " | |
57 | "than system GFP_DMA mask %#llx\n", | |
58 | mask, (unsigned long long)ISA_DMA_THRESHOLD); | |
59 | return 0; | |
60 | } | |
61 | } | |
1da177e4 | 62 | |
ab6494f0 CM |
63 | return mask; |
64 | } | |
65 | ||
7a9a32a9 RK |
66 | /* |
67 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
68 | * specified gfp mask. Note that 'size' must be page aligned. | |
69 | */ | |
70 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
71 | { | |
72 | unsigned long order = get_order(size); | |
73 | struct page *page, *p, *e; | |
74 | void *ptr; | |
75 | u64 mask = get_coherent_dma_mask(dev); | |
76 | ||
77 | #ifdef CONFIG_DMA_API_DEBUG | |
78 | u64 limit = (mask + 1) & ~mask; | |
79 | if (limit && size >= limit) { | |
80 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
81 | size, mask); | |
82 | return NULL; | |
83 | } | |
84 | #endif | |
85 | ||
86 | if (!mask) | |
87 | return NULL; | |
88 | ||
89 | if (mask < 0xffffffffULL) | |
90 | gfp |= GFP_DMA; | |
91 | ||
92 | page = alloc_pages(gfp, order); | |
93 | if (!page) | |
94 | return NULL; | |
95 | ||
96 | /* | |
97 | * Now split the huge page and free the excess pages | |
98 | */ | |
99 | split_page(page, order); | |
100 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
101 | __free_page(p); | |
102 | ||
103 | /* | |
104 | * Ensure that the allocated pages are zeroed, and that any data | |
105 | * lurking in the kernel direct-mapped region is invalidated. | |
106 | */ | |
107 | ptr = page_address(page); | |
108 | memset(ptr, 0, size); | |
109 | dmac_flush_range(ptr, ptr + size); | |
110 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
111 | ||
112 | return page; | |
113 | } | |
114 | ||
115 | /* | |
116 | * Free a DMA buffer. 'size' must be page aligned. | |
117 | */ | |
118 | static void __dma_free_buffer(struct page *page, size_t size) | |
119 | { | |
120 | struct page *e = page + (size >> PAGE_SHIFT); | |
121 | ||
122 | while (page < e) { | |
123 | __free_page(page); | |
124 | page++; | |
125 | } | |
126 | } | |
127 | ||
ab6494f0 | 128 | #ifdef CONFIG_MMU |
1da177e4 | 129 | /* |
37134cd5 | 130 | * These are the page tables (2MB each) covering uncached, DMA consistent allocations |
1da177e4 | 131 | */ |
37134cd5 | 132 | static pte_t *consistent_pte[NUM_CONSISTENT_PTES]; |
1da177e4 | 133 | |
13ccf3ad | 134 | #include "vmregion.h" |
1da177e4 | 135 | |
13ccf3ad RK |
136 | static struct arm_vmregion_head consistent_head = { |
137 | .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock), | |
1da177e4 LT |
138 | .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), |
139 | .vm_start = CONSISTENT_BASE, | |
140 | .vm_end = CONSISTENT_END, | |
141 | }; | |
142 | ||
1da177e4 LT |
143 | #ifdef CONFIG_HUGETLB_PAGE |
144 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
145 | #endif | |
146 | ||
147 | static void * | |
f9e3214a | 148 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, |
1da177e4 LT |
149 | pgprot_t prot) |
150 | { | |
151 | struct page *page; | |
13ccf3ad | 152 | struct arm_vmregion *c; |
1da177e4 | 153 | |
37134cd5 | 154 | if (!consistent_pte[0]) { |
1da177e4 LT |
155 | printk(KERN_ERR "%s: not initialised\n", __func__); |
156 | dump_stack(); | |
157 | return NULL; | |
158 | } | |
159 | ||
1da177e4 | 160 | size = PAGE_ALIGN(size); |
1da177e4 | 161 | |
7a9a32a9 | 162 | page = __dma_alloc_buffer(dev, size, gfp); |
1da177e4 LT |
163 | if (!page) |
164 | goto no_page; | |
165 | ||
1da177e4 LT |
166 | /* |
167 | * Allocate a virtual address in the consistent mapping region. | |
168 | */ | |
13ccf3ad | 169 | c = arm_vmregion_alloc(&consistent_head, size, |
1da177e4 LT |
170 | gfp & ~(__GFP_DMA | __GFP_HIGHMEM)); |
171 | if (c) { | |
37134cd5 | 172 | pte_t *pte; |
37134cd5 KH |
173 | int idx = CONSISTENT_PTE_INDEX(c->vm_start); |
174 | u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
1da177e4 | 175 | |
37134cd5 | 176 | pte = consistent_pte[idx] + off; |
1da177e4 LT |
177 | c->vm_pages = page; |
178 | ||
179 | /* | |
180 | * Set the "dma handle" | |
181 | */ | |
182 | *handle = page_to_dma(dev, page); | |
183 | ||
184 | do { | |
185 | BUG_ON(!pte_none(*pte)); | |
186 | ||
1da177e4 LT |
187 | /* |
188 | * x86 does not mark the pages reserved... | |
189 | */ | |
190 | SetPageReserved(page); | |
ad1ae2fe | 191 | set_pte_ext(pte, mk_pte(page, prot), 0); |
1da177e4 LT |
192 | page++; |
193 | pte++; | |
37134cd5 KH |
194 | off++; |
195 | if (off >= PTRS_PER_PTE) { | |
196 | off = 0; | |
197 | pte = consistent_pte[++idx]; | |
198 | } | |
1da177e4 LT |
199 | } while (size -= PAGE_SIZE); |
200 | ||
1da177e4 LT |
201 | return (void *)c->vm_start; |
202 | } | |
203 | ||
204 | if (page) | |
7a9a32a9 | 205 | __dma_free_buffer(page, size); |
1da177e4 LT |
206 | no_page: |
207 | *handle = ~0; | |
208 | return NULL; | |
209 | } | |
ab6494f0 CM |
210 | #else /* !CONFIG_MMU */ |
211 | static void * | |
212 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, | |
213 | pgprot_t prot) | |
214 | { | |
215 | void *virt; | |
216 | u64 mask = get_coherent_dma_mask(dev); | |
217 | ||
218 | if (!mask) | |
219 | goto error; | |
220 | ||
c06e004c | 221 | if (mask < 0xffffffffULL) |
ab6494f0 CM |
222 | gfp |= GFP_DMA; |
223 | virt = kmalloc(size, gfp); | |
224 | if (!virt) | |
225 | goto error; | |
226 | ||
227 | *handle = virt_to_dma(dev, virt); | |
228 | return virt; | |
229 | ||
230 | error: | |
231 | *handle = ~0; | |
232 | return NULL; | |
233 | } | |
234 | #endif /* CONFIG_MMU */ | |
1da177e4 LT |
235 | |
236 | /* | |
237 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
238 | * virtual and bus address for that space. | |
239 | */ | |
240 | void * | |
f9e3214a | 241 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 | 242 | { |
1fe53268 DB |
243 | void *memory; |
244 | ||
245 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
246 | return memory; | |
247 | ||
23759dc6 LB |
248 | if (arch_is_coherent()) { |
249 | void *virt; | |
250 | ||
251 | virt = kmalloc(size, gfp); | |
252 | if (!virt) | |
253 | return NULL; | |
254 | *handle = virt_to_dma(dev, virt); | |
255 | ||
256 | return virt; | |
257 | } | |
258 | ||
1da177e4 LT |
259 | return __dma_alloc(dev, size, handle, gfp, |
260 | pgprot_noncached(pgprot_kernel)); | |
261 | } | |
262 | EXPORT_SYMBOL(dma_alloc_coherent); | |
263 | ||
264 | /* | |
265 | * Allocate a writecombining region, in much the same way as | |
266 | * dma_alloc_coherent above. | |
267 | */ | |
268 | void * | |
f9e3214a | 269 | dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 LT |
270 | { |
271 | return __dma_alloc(dev, size, handle, gfp, | |
272 | pgprot_writecombine(pgprot_kernel)); | |
273 | } | |
274 | EXPORT_SYMBOL(dma_alloc_writecombine); | |
275 | ||
276 | static int dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
277 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
278 | { | |
ab6494f0 CM |
279 | int ret = -ENXIO; |
280 | #ifdef CONFIG_MMU | |
13ccf3ad RK |
281 | unsigned long user_size, kern_size; |
282 | struct arm_vmregion *c; | |
1da177e4 LT |
283 | |
284 | user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; | |
285 | ||
13ccf3ad | 286 | c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr); |
1da177e4 LT |
287 | if (c) { |
288 | unsigned long off = vma->vm_pgoff; | |
289 | ||
290 | kern_size = (c->vm_end - c->vm_start) >> PAGE_SHIFT; | |
291 | ||
292 | if (off < kern_size && | |
293 | user_size <= (kern_size - off)) { | |
1da177e4 LT |
294 | ret = remap_pfn_range(vma, vma->vm_start, |
295 | page_to_pfn(c->vm_pages) + off, | |
296 | user_size << PAGE_SHIFT, | |
297 | vma->vm_page_prot); | |
298 | } | |
299 | } | |
ab6494f0 | 300 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
301 | |
302 | return ret; | |
303 | } | |
304 | ||
305 | int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, | |
306 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
307 | { | |
308 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
309 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
310 | } | |
311 | EXPORT_SYMBOL(dma_mmap_coherent); | |
312 | ||
313 | int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma, | |
314 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
315 | { | |
316 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
317 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
318 | } | |
319 | EXPORT_SYMBOL(dma_mmap_writecombine); | |
320 | ||
321 | /* | |
322 | * free a page as defined by the above mapping. | |
5edf71ae | 323 | * Must not be called with IRQs disabled. |
1da177e4 | 324 | */ |
ab6494f0 | 325 | #ifdef CONFIG_MMU |
1da177e4 LT |
326 | void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) |
327 | { | |
13ccf3ad RK |
328 | struct arm_vmregion *c; |
329 | unsigned long addr; | |
1da177e4 | 330 | pte_t *ptep; |
37134cd5 KH |
331 | int idx; |
332 | u32 off; | |
1da177e4 | 333 | |
5edf71ae RK |
334 | WARN_ON(irqs_disabled()); |
335 | ||
1fe53268 DB |
336 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
337 | return; | |
338 | ||
23759dc6 LB |
339 | if (arch_is_coherent()) { |
340 | kfree(cpu_addr); | |
341 | return; | |
342 | } | |
343 | ||
1da177e4 LT |
344 | size = PAGE_ALIGN(size); |
345 | ||
13ccf3ad | 346 | c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr); |
1da177e4 LT |
347 | if (!c) |
348 | goto no_area; | |
349 | ||
350 | if ((c->vm_end - c->vm_start) != size) { | |
351 | printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n", | |
352 | __func__, c->vm_end - c->vm_start, size); | |
353 | dump_stack(); | |
354 | size = c->vm_end - c->vm_start; | |
355 | } | |
356 | ||
37134cd5 KH |
357 | idx = CONSISTENT_PTE_INDEX(c->vm_start); |
358 | off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
359 | ptep = consistent_pte[idx] + off; | |
1da177e4 LT |
360 | addr = c->vm_start; |
361 | do { | |
362 | pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep); | |
363 | unsigned long pfn; | |
364 | ||
365 | ptep++; | |
366 | addr += PAGE_SIZE; | |
37134cd5 KH |
367 | off++; |
368 | if (off >= PTRS_PER_PTE) { | |
369 | off = 0; | |
370 | ptep = consistent_pte[++idx]; | |
371 | } | |
1da177e4 LT |
372 | |
373 | if (!pte_none(pte) && pte_present(pte)) { | |
374 | pfn = pte_pfn(pte); | |
375 | ||
376 | if (pfn_valid(pfn)) { | |
377 | struct page *page = pfn_to_page(pfn); | |
378 | ||
379 | /* | |
380 | * x86 does not mark the pages reserved... | |
381 | */ | |
382 | ClearPageReserved(page); | |
1da177e4 LT |
383 | continue; |
384 | } | |
385 | } | |
1da177e4 LT |
386 | printk(KERN_CRIT "%s: bad page in kernel page table\n", |
387 | __func__); | |
388 | } while (size -= PAGE_SIZE); | |
389 | ||
390 | flush_tlb_kernel_range(c->vm_start, c->vm_end); | |
391 | ||
13ccf3ad | 392 | arm_vmregion_free(&consistent_head, c); |
7a9a32a9 RK |
393 | |
394 | __dma_free_buffer(dma_to_page(dev, handle), size); | |
1da177e4 LT |
395 | return; |
396 | ||
397 | no_area: | |
1da177e4 LT |
398 | printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n", |
399 | __func__, cpu_addr); | |
400 | dump_stack(); | |
401 | } | |
ab6494f0 CM |
402 | #else /* !CONFIG_MMU */ |
403 | void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) | |
404 | { | |
405 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) | |
406 | return; | |
407 | kfree(cpu_addr); | |
408 | } | |
409 | #endif /* CONFIG_MMU */ | |
1da177e4 LT |
410 | EXPORT_SYMBOL(dma_free_coherent); |
411 | ||
412 | /* | |
413 | * Initialise the consistent memory allocation. | |
414 | */ | |
415 | static int __init consistent_init(void) | |
416 | { | |
ab6494f0 CM |
417 | int ret = 0; |
418 | #ifdef CONFIG_MMU | |
1da177e4 LT |
419 | pgd_t *pgd; |
420 | pmd_t *pmd; | |
421 | pte_t *pte; | |
ab6494f0 | 422 | int i = 0; |
37134cd5 | 423 | u32 base = CONSISTENT_BASE; |
1da177e4 | 424 | |
1da177e4 | 425 | do { |
37134cd5 KH |
426 | pgd = pgd_offset(&init_mm, base); |
427 | pmd = pmd_alloc(&init_mm, pgd, base); | |
1da177e4 LT |
428 | if (!pmd) { |
429 | printk(KERN_ERR "%s: no pmd tables\n", __func__); | |
430 | ret = -ENOMEM; | |
431 | break; | |
432 | } | |
433 | WARN_ON(!pmd_none(*pmd)); | |
434 | ||
37134cd5 | 435 | pte = pte_alloc_kernel(pmd, base); |
1da177e4 LT |
436 | if (!pte) { |
437 | printk(KERN_ERR "%s: no pte tables\n", __func__); | |
438 | ret = -ENOMEM; | |
439 | break; | |
440 | } | |
441 | ||
37134cd5 KH |
442 | consistent_pte[i++] = pte; |
443 | base += (1 << PGDIR_SHIFT); | |
444 | } while (base < CONSISTENT_END); | |
ab6494f0 | 445 | #endif /* !CONFIG_MMU */ |
1da177e4 | 446 | |
1da177e4 LT |
447 | return ret; |
448 | } | |
449 | ||
450 | core_initcall(consistent_init); | |
451 | ||
452 | /* | |
453 | * Make an area consistent for devices. | |
105ef9a0 DW |
454 | * Note: Drivers should NOT use this function directly, as it will break |
455 | * platforms with CONFIG_DMABOUNCE. | |
456 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
1da177e4 | 457 | */ |
84aa462e | 458 | void dma_cache_maint(const void *start, size_t size, int direction) |
1da177e4 | 459 | { |
1522ac3e RK |
460 | void (*inner_op)(const void *, const void *); |
461 | void (*outer_op)(unsigned long, unsigned long); | |
1da177e4 | 462 | |
1522ac3e | 463 | BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1)); |
953233dc | 464 | |
1da177e4 LT |
465 | switch (direction) { |
466 | case DMA_FROM_DEVICE: /* invalidate only */ | |
1522ac3e RK |
467 | inner_op = dmac_inv_range; |
468 | outer_op = outer_inv_range; | |
1da177e4 LT |
469 | break; |
470 | case DMA_TO_DEVICE: /* writeback only */ | |
1522ac3e RK |
471 | inner_op = dmac_clean_range; |
472 | outer_op = outer_clean_range; | |
1da177e4 LT |
473 | break; |
474 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | |
1522ac3e RK |
475 | inner_op = dmac_flush_range; |
476 | outer_op = outer_flush_range; | |
1da177e4 LT |
477 | break; |
478 | default: | |
479 | BUG(); | |
480 | } | |
1522ac3e RK |
481 | |
482 | inner_op(start, start + size); | |
483 | outer_op(__pa(start), __pa(start) + size); | |
1da177e4 | 484 | } |
84aa462e | 485 | EXPORT_SYMBOL(dma_cache_maint); |
afd1a321 | 486 | |
43377453 NP |
487 | static void dma_cache_maint_contiguous(struct page *page, unsigned long offset, |
488 | size_t size, int direction) | |
489 | { | |
490 | void *vaddr; | |
491 | unsigned long paddr; | |
492 | void (*inner_op)(const void *, const void *); | |
493 | void (*outer_op)(unsigned long, unsigned long); | |
494 | ||
495 | switch (direction) { | |
496 | case DMA_FROM_DEVICE: /* invalidate only */ | |
497 | inner_op = dmac_inv_range; | |
498 | outer_op = outer_inv_range; | |
499 | break; | |
500 | case DMA_TO_DEVICE: /* writeback only */ | |
501 | inner_op = dmac_clean_range; | |
502 | outer_op = outer_clean_range; | |
503 | break; | |
504 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | |
505 | inner_op = dmac_flush_range; | |
506 | outer_op = outer_flush_range; | |
507 | break; | |
508 | default: | |
509 | BUG(); | |
510 | } | |
511 | ||
512 | if (!PageHighMem(page)) { | |
513 | vaddr = page_address(page) + offset; | |
514 | inner_op(vaddr, vaddr + size); | |
515 | } else { | |
516 | vaddr = kmap_high_get(page); | |
517 | if (vaddr) { | |
518 | vaddr += offset; | |
519 | inner_op(vaddr, vaddr + size); | |
520 | kunmap_high(page); | |
521 | } | |
522 | } | |
523 | ||
524 | paddr = page_to_phys(page) + offset; | |
525 | outer_op(paddr, paddr + size); | |
526 | } | |
527 | ||
528 | void dma_cache_maint_page(struct page *page, unsigned long offset, | |
529 | size_t size, int dir) | |
530 | { | |
531 | /* | |
532 | * A single sg entry may refer to multiple physically contiguous | |
533 | * pages. But we still need to process highmem pages individually. | |
534 | * If highmem is not configured then the bulk of this loop gets | |
535 | * optimized out. | |
536 | */ | |
537 | size_t left = size; | |
538 | do { | |
539 | size_t len = left; | |
540 | if (PageHighMem(page) && len + offset > PAGE_SIZE) { | |
541 | if (offset >= PAGE_SIZE) { | |
542 | page += offset / PAGE_SIZE; | |
543 | offset %= PAGE_SIZE; | |
544 | } | |
545 | len = PAGE_SIZE - offset; | |
546 | } | |
547 | dma_cache_maint_contiguous(page, offset, len, dir); | |
548 | offset = 0; | |
549 | page++; | |
550 | left -= len; | |
551 | } while (left); | |
552 | } | |
553 | EXPORT_SYMBOL(dma_cache_maint_page); | |
554 | ||
afd1a321 RK |
555 | /** |
556 | * dma_map_sg - map a set of SG buffers for streaming mode DMA | |
557 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
558 | * @sg: list of buffers | |
559 | * @nents: number of buffers to map | |
560 | * @dir: DMA transfer direction | |
561 | * | |
562 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
563 | * This is the scatter-gather version of the dma_map_single interface. | |
564 | * Here the scatter gather list elements are each tagged with the | |
565 | * appropriate dma address and length. They are obtained via | |
566 | * sg_dma_{address,length}. | |
567 | * | |
568 | * Device ownership issues as mentioned for dma_map_single are the same | |
569 | * here. | |
570 | */ | |
571 | int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
572 | enum dma_data_direction dir) | |
573 | { | |
574 | struct scatterlist *s; | |
01135d92 | 575 | int i, j; |
afd1a321 RK |
576 | |
577 | for_each_sg(sg, s, nents, i) { | |
01135d92 RK |
578 | s->dma_address = dma_map_page(dev, sg_page(s), s->offset, |
579 | s->length, dir); | |
580 | if (dma_mapping_error(dev, s->dma_address)) | |
581 | goto bad_mapping; | |
afd1a321 | 582 | } |
afd1a321 | 583 | return nents; |
01135d92 RK |
584 | |
585 | bad_mapping: | |
586 | for_each_sg(sg, s, i, j) | |
587 | dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); | |
588 | return 0; | |
afd1a321 RK |
589 | } |
590 | EXPORT_SYMBOL(dma_map_sg); | |
591 | ||
592 | /** | |
593 | * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
594 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
595 | * @sg: list of buffers | |
596 | * @nents: number of buffers to unmap (returned from dma_map_sg) | |
597 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
598 | * | |
599 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
600 | * rules concerning calls here are the same as for dma_unmap_single(). | |
601 | */ | |
602 | void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
603 | enum dma_data_direction dir) | |
604 | { | |
01135d92 RK |
605 | struct scatterlist *s; |
606 | int i; | |
607 | ||
608 | for_each_sg(sg, s, nents, i) | |
609 | dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); | |
afd1a321 RK |
610 | } |
611 | EXPORT_SYMBOL(dma_unmap_sg); | |
612 | ||
613 | /** | |
614 | * dma_sync_sg_for_cpu | |
615 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
616 | * @sg: list of buffers | |
617 | * @nents: number of buffers to map (returned from dma_map_sg) | |
618 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
619 | */ | |
620 | void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
621 | int nents, enum dma_data_direction dir) | |
622 | { | |
623 | struct scatterlist *s; | |
624 | int i; | |
625 | ||
626 | for_each_sg(sg, s, nents, i) { | |
309dbbab RK |
627 | dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0, |
628 | sg_dma_len(s), dir); | |
afd1a321 RK |
629 | } |
630 | } | |
631 | EXPORT_SYMBOL(dma_sync_sg_for_cpu); | |
632 | ||
633 | /** | |
634 | * dma_sync_sg_for_device | |
635 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
636 | * @sg: list of buffers | |
637 | * @nents: number of buffers to map (returned from dma_map_sg) | |
638 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
639 | */ | |
640 | void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
641 | int nents, enum dma_data_direction dir) | |
642 | { | |
643 | struct scatterlist *s; | |
644 | int i; | |
645 | ||
646 | for_each_sg(sg, s, nents, i) { | |
2638b4db RK |
647 | if (!dmabounce_sync_for_device(dev, sg_dma_address(s), 0, |
648 | sg_dma_len(s), dir)) | |
649 | continue; | |
650 | ||
afd1a321 | 651 | if (!arch_is_coherent()) |
43377453 NP |
652 | dma_cache_maint_page(sg_page(s), s->offset, |
653 | s->length, dir); | |
afd1a321 RK |
654 | } |
655 | } | |
656 | EXPORT_SYMBOL(dma_sync_sg_for_device); |