Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/flush.c | |
3 | * | |
4 | * Copyright (C) 1995-2002 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/module.h> | |
11 | #include <linux/mm.h> | |
12 | #include <linux/pagemap.h> | |
13 | ||
14 | #include <asm/cacheflush.h> | |
46097c7d | 15 | #include <asm/cachetype.h> |
1da177e4 | 16 | #include <asm/system.h> |
8d802d28 RK |
17 | #include <asm/tlbflush.h> |
18 | ||
1b2e2b73 RK |
19 | #include "mm.h" |
20 | ||
8d802d28 | 21 | #ifdef CONFIG_CPU_CACHE_VIPT |
d7b6b358 | 22 | |
481467d6 CM |
23 | #define ALIAS_FLUSH_START 0xffff4000 |
24 | ||
481467d6 CM |
25 | static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) |
26 | { | |
27 | unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); | |
141fa40c | 28 | const int zero = 0; |
481467d6 | 29 | |
ad1ae2fe | 30 | set_pte_ext(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL), 0); |
481467d6 CM |
31 | flush_tlb_kernel_page(to); |
32 | ||
33 | asm( "mcrr p15, 0, %1, %0, c14\n" | |
df71dfd4 | 34 | " mcr p15, 0, %2, c7, c10, 4" |
481467d6 | 35 | : |
141fa40c | 36 | : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) |
481467d6 CM |
37 | : "cc"); |
38 | } | |
39 | ||
d7b6b358 RK |
40 | void flush_cache_mm(struct mm_struct *mm) |
41 | { | |
42 | if (cache_is_vivt()) { | |
2f0b1926 | 43 | vivt_flush_cache_mm(mm); |
d7b6b358 RK |
44 | return; |
45 | } | |
46 | ||
47 | if (cache_is_vipt_aliasing()) { | |
48 | asm( "mcr p15, 0, %0, c7, c14, 0\n" | |
df71dfd4 | 49 | " mcr p15, 0, %0, c7, c10, 4" |
d7b6b358 RK |
50 | : |
51 | : "r" (0) | |
52 | : "cc"); | |
df71dfd4 | 53 | __flush_icache_all(); |
d7b6b358 RK |
54 | } |
55 | } | |
56 | ||
57 | void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
58 | { | |
59 | if (cache_is_vivt()) { | |
2f0b1926 | 60 | vivt_flush_cache_range(vma, start, end); |
d7b6b358 RK |
61 | return; |
62 | } | |
63 | ||
64 | if (cache_is_vipt_aliasing()) { | |
65 | asm( "mcr p15, 0, %0, c7, c14, 0\n" | |
df71dfd4 | 66 | " mcr p15, 0, %0, c7, c10, 4" |
d7b6b358 RK |
67 | : |
68 | : "r" (0) | |
69 | : "cc"); | |
df71dfd4 | 70 | __flush_icache_all(); |
d7b6b358 RK |
71 | } |
72 | } | |
73 | ||
74 | void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) | |
75 | { | |
76 | if (cache_is_vivt()) { | |
2f0b1926 | 77 | vivt_flush_cache_page(vma, user_addr, pfn); |
d7b6b358 RK |
78 | return; |
79 | } | |
80 | ||
2df341ed | 81 | if (cache_is_vipt_aliasing()) { |
d7b6b358 | 82 | flush_pfn_alias(pfn, user_addr); |
2df341ed RK |
83 | __flush_icache_all(); |
84 | } | |
d7b6b358 | 85 | } |
a188ad2b GD |
86 | |
87 | void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, | |
88 | unsigned long uaddr, void *kaddr, | |
89 | unsigned long len, int write) | |
90 | { | |
91 | if (cache_is_vivt()) { | |
2f0b1926 | 92 | vivt_flush_ptrace_access(vma, page, uaddr, kaddr, len, write); |
a188ad2b GD |
93 | return; |
94 | } | |
95 | ||
96 | if (cache_is_vipt_aliasing()) { | |
97 | flush_pfn_alias(page_to_pfn(page), uaddr); | |
2df341ed | 98 | __flush_icache_all(); |
a188ad2b GD |
99 | return; |
100 | } | |
101 | ||
102 | /* VIPT non-aliasing cache */ | |
56f8ba83 | 103 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)) && |
a71ebdfa | 104 | vma->vm_flags & VM_EXEC) { |
a188ad2b GD |
105 | unsigned long addr = (unsigned long)kaddr; |
106 | /* only flushing the kernel mapping on non-aliasing VIPT */ | |
107 | __cpuc_coherent_kern_range(addr, addr + len); | |
108 | } | |
109 | } | |
8d802d28 RK |
110 | #else |
111 | #define flush_pfn_alias(pfn,vaddr) do { } while (0) | |
112 | #endif | |
1da177e4 | 113 | |
8830f04a | 114 | void __flush_dcache_page(struct address_space *mapping, struct page *page) |
1da177e4 | 115 | { |
b7dc0b2c RK |
116 | void *addr = page_address(page); |
117 | ||
1da177e4 LT |
118 | /* |
119 | * Writeback any data associated with the kernel mapping of this | |
120 | * page. This ensures that data in the physical page is mutually | |
121 | * coherent with the kernels mapping. | |
122 | */ | |
13f96d8f NP |
123 | #ifdef CONFIG_HIGHMEM |
124 | /* | |
125 | * kmap_atomic() doesn't set the page virtual address, and | |
126 | * kunmap_atomic() takes care of cache flushing already. | |
127 | */ | |
b7dc0b2c | 128 | if (addr) |
13f96d8f | 129 | #endif |
b7dc0b2c | 130 | __cpuc_flush_dcache_page(addr); |
1da177e4 LT |
131 | |
132 | /* | |
8830f04a RK |
133 | * If this is a page cache page, and we have an aliasing VIPT cache, |
134 | * we only need to do one flush - which would be at the relevant | |
8d802d28 RK |
135 | * userspace colour, which is congruent with page->index. |
136 | */ | |
f91fb05d | 137 | if (mapping && cache_is_vipt_aliasing()) |
8830f04a RK |
138 | flush_pfn_alias(page_to_pfn(page), |
139 | page->index << PAGE_CACHE_SHIFT); | |
140 | } | |
141 | ||
142 | static void __flush_dcache_aliases(struct address_space *mapping, struct page *page) | |
143 | { | |
144 | struct mm_struct *mm = current->active_mm; | |
145 | struct vm_area_struct *mpnt; | |
146 | struct prio_tree_iter iter; | |
147 | pgoff_t pgoff; | |
8d802d28 | 148 | |
1da177e4 LT |
149 | /* |
150 | * There are possible user space mappings of this page: | |
151 | * - VIVT cache: we need to also write back and invalidate all user | |
152 | * data in the current VM view associated with this page. | |
153 | * - aliasing VIPT: we only need to find one mapping of this page. | |
154 | */ | |
155 | pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT); | |
156 | ||
157 | flush_dcache_mmap_lock(mapping); | |
158 | vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) { | |
159 | unsigned long offset; | |
160 | ||
161 | /* | |
162 | * If this VMA is not in our MM, we can ignore it. | |
163 | */ | |
164 | if (mpnt->vm_mm != mm) | |
165 | continue; | |
166 | if (!(mpnt->vm_flags & VM_MAYSHARE)) | |
167 | continue; | |
168 | offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; | |
169 | flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page)); | |
1da177e4 LT |
170 | } |
171 | flush_dcache_mmap_unlock(mapping); | |
172 | } | |
173 | ||
174 | /* | |
175 | * Ensure cache coherency between kernel mapping and userspace mapping | |
176 | * of this page. | |
177 | * | |
178 | * We have three cases to consider: | |
179 | * - VIPT non-aliasing cache: fully coherent so nothing required. | |
180 | * - VIVT: fully aliasing, so we need to handle every alias in our | |
181 | * current VM view. | |
182 | * - VIPT aliasing: need to handle one alias in our current VM view. | |
183 | * | |
184 | * If we need to handle aliasing: | |
185 | * If the page only exists in the page cache and there are no user | |
186 | * space mappings, we can be lazy and remember that we may have dirty | |
187 | * kernel cache lines for later. Otherwise, we assume we have | |
188 | * aliasing mappings. | |
df2f5e72 RK |
189 | * |
190 | * Note that we disable the lazy flush for SMP. | |
1da177e4 LT |
191 | */ |
192 | void flush_dcache_page(struct page *page) | |
193 | { | |
421fe93c RK |
194 | struct address_space *mapping; |
195 | ||
196 | /* | |
197 | * The zero page is never written to, so never has any dirty | |
198 | * cache lines, and therefore never needs to be flushed. | |
199 | */ | |
200 | if (page == ZERO_PAGE(0)) | |
201 | return; | |
202 | ||
203 | mapping = page_mapping(page); | |
1da177e4 | 204 | |
df2f5e72 | 205 | #ifndef CONFIG_SMP |
d73cd428 | 206 | if (!PageHighMem(page) && mapping && !mapping_mapped(mapping)) |
1da177e4 | 207 | set_bit(PG_dcache_dirty, &page->flags); |
df2f5e72 RK |
208 | else |
209 | #endif | |
210 | { | |
1da177e4 | 211 | __flush_dcache_page(mapping, page); |
8830f04a RK |
212 | if (mapping && cache_is_vivt()) |
213 | __flush_dcache_aliases(mapping, page); | |
826cbdaf CM |
214 | else if (mapping) |
215 | __flush_icache_all(); | |
8830f04a | 216 | } |
1da177e4 LT |
217 | } |
218 | EXPORT_SYMBOL(flush_dcache_page); | |
6020dff0 RK |
219 | |
220 | /* | |
221 | * Flush an anonymous page so that users of get_user_pages() | |
222 | * can safely access the data. The expected sequence is: | |
223 | * | |
224 | * get_user_pages() | |
225 | * -> flush_anon_page | |
226 | * memcpy() to/from page | |
227 | * if written to page, flush_dcache_page() | |
228 | */ | |
229 | void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) | |
230 | { | |
231 | unsigned long pfn; | |
232 | ||
233 | /* VIPT non-aliasing caches need do nothing */ | |
234 | if (cache_is_vipt_nonaliasing()) | |
235 | return; | |
236 | ||
237 | /* | |
238 | * Write back and invalidate userspace mapping. | |
239 | */ | |
240 | pfn = page_to_pfn(page); | |
241 | if (cache_is_vivt()) { | |
242 | flush_cache_page(vma, vmaddr, pfn); | |
243 | } else { | |
244 | /* | |
245 | * For aliasing VIPT, we can flush an alias of the | |
246 | * userspace address only. | |
247 | */ | |
248 | flush_pfn_alias(pfn, vmaddr); | |
2df341ed | 249 | __flush_icache_all(); |
6020dff0 RK |
250 | } |
251 | ||
252 | /* | |
253 | * Invalidate kernel mapping. No data should be contained | |
254 | * in this mapping of the page. FIXME: this is overkill | |
255 | * since we actually ask for a write-back and invalidate. | |
256 | */ | |
257 | __cpuc_flush_dcache_page(page_address(page)); | |
258 | } |