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d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
d111e8f9 RK |
14 | #include <linux/mman.h> |
15 | #include <linux/nodemask.h> | |
2778f620 | 16 | #include <linux/memblock.h> |
d907387c | 17 | #include <linux/fs.h> |
0536bdf3 | 18 | #include <linux/vmalloc.h> |
158e8bfe | 19 | #include <linux/sizes.h> |
d111e8f9 | 20 | |
15d07dc9 | 21 | #include <asm/cp15.h> |
0ba8b9b2 | 22 | #include <asm/cputype.h> |
37efe642 | 23 | #include <asm/sections.h> |
3f973e22 | 24 | #include <asm/cachetype.h> |
d111e8f9 | 25 | #include <asm/setup.h> |
e616c591 | 26 | #include <asm/smp_plat.h> |
d111e8f9 | 27 | #include <asm/tlb.h> |
d73cd428 | 28 | #include <asm/highmem.h> |
9f97da78 | 29 | #include <asm/system_info.h> |
247055aa | 30 | #include <asm/traps.h> |
d111e8f9 RK |
31 | |
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/mach/map.h> | |
c2794437 | 34 | #include <asm/mach/pci.h> |
d111e8f9 RK |
35 | |
36 | #include "mm.h" | |
de40614e | 37 | #include "tcm.h" |
d111e8f9 | 38 | |
d111e8f9 RK |
39 | /* |
40 | * empty_zero_page is a special page that is used for | |
41 | * zero-initialized data and COW. | |
42 | */ | |
43 | struct page *empty_zero_page; | |
3653f3ab | 44 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
45 | |
46 | /* | |
47 | * The pmd table for the upper-most set of pages. | |
48 | */ | |
49 | pmd_t *top_pmd; | |
50 | ||
ae8f1541 RK |
51 | #define CPOLICY_UNCACHED 0 |
52 | #define CPOLICY_BUFFERED 1 | |
53 | #define CPOLICY_WRITETHROUGH 2 | |
54 | #define CPOLICY_WRITEBACK 3 | |
55 | #define CPOLICY_WRITEALLOC 4 | |
56 | ||
57 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
58 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 59 | pgprot_t pgprot_user; |
ae8f1541 | 60 | pgprot_t pgprot_kernel; |
cc577c26 CD |
61 | pgprot_t pgprot_hyp_device; |
62 | pgprot_t pgprot_s2; | |
63 | pgprot_t pgprot_s2_device; | |
ae8f1541 | 64 | |
44b18693 | 65 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
66 | EXPORT_SYMBOL(pgprot_kernel); |
67 | ||
68 | struct cachepolicy { | |
69 | const char policy[16]; | |
70 | unsigned int cr_mask; | |
442e70c0 | 71 | pmdval_t pmd; |
f6e3354d | 72 | pteval_t pte; |
cc577c26 | 73 | pteval_t pte_s2; |
ae8f1541 RK |
74 | }; |
75 | ||
cc577c26 CD |
76 | #ifdef CONFIG_ARM_LPAE |
77 | #define s2_policy(policy) policy | |
78 | #else | |
79 | #define s2_policy(policy) 0 | |
80 | #endif | |
81 | ||
ae8f1541 RK |
82 | static struct cachepolicy cache_policies[] __initdata = { |
83 | { | |
84 | .policy = "uncached", | |
85 | .cr_mask = CR_W|CR_C, | |
86 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 87 | .pte = L_PTE_MT_UNCACHED, |
cc577c26 | 88 | .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), |
ae8f1541 RK |
89 | }, { |
90 | .policy = "buffered", | |
91 | .cr_mask = CR_C, | |
92 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 93 | .pte = L_PTE_MT_BUFFERABLE, |
cc577c26 | 94 | .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), |
ae8f1541 RK |
95 | }, { |
96 | .policy = "writethrough", | |
97 | .cr_mask = 0, | |
98 | .pmd = PMD_SECT_WT, | |
bb30f36f | 99 | .pte = L_PTE_MT_WRITETHROUGH, |
cc577c26 | 100 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH), |
ae8f1541 RK |
101 | }, { |
102 | .policy = "writeback", | |
103 | .cr_mask = 0, | |
104 | .pmd = PMD_SECT_WB, | |
bb30f36f | 105 | .pte = L_PTE_MT_WRITEBACK, |
cc577c26 | 106 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), |
ae8f1541 RK |
107 | }, { |
108 | .policy = "writealloc", | |
109 | .cr_mask = 0, | |
110 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 111 | .pte = L_PTE_MT_WRITEALLOC, |
cc577c26 | 112 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), |
ae8f1541 RK |
113 | } |
114 | }; | |
115 | ||
b849a60e | 116 | #ifdef CONFIG_CPU_CP15 |
ae8f1541 | 117 | /* |
6cbdc8c5 | 118 | * These are useful for identifying cache coherency |
ae8f1541 RK |
119 | * problems by allowing the cache or the cache and |
120 | * writebuffer to be turned off. (Note: the write | |
121 | * buffer should not be on and the cache off). | |
122 | */ | |
2b0d8c25 | 123 | static int __init early_cachepolicy(char *p) |
ae8f1541 RK |
124 | { |
125 | int i; | |
126 | ||
127 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | |
128 | int len = strlen(cache_policies[i].policy); | |
129 | ||
2b0d8c25 | 130 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ae8f1541 RK |
131 | cachepolicy = i; |
132 | cr_alignment &= ~cache_policies[i].cr_mask; | |
133 | cr_no_alignment &= ~cache_policies[i].cr_mask; | |
ae8f1541 RK |
134 | break; |
135 | } | |
136 | } | |
137 | if (i == ARRAY_SIZE(cache_policies)) | |
138 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); | |
4b46d641 RK |
139 | /* |
140 | * This restriction is partly to do with the way we boot; it is | |
141 | * unpredictable to have memory mapped using two different sets of | |
142 | * memory attributes (shared, type, and cache attribs). We can not | |
143 | * change these attributes once the initial assembly has setup the | |
144 | * page tables. | |
145 | */ | |
11179d8c CM |
146 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
147 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); | |
148 | cachepolicy = CPOLICY_WRITEBACK; | |
149 | } | |
ae8f1541 RK |
150 | flush_cache_all(); |
151 | set_cr(cr_alignment); | |
2b0d8c25 | 152 | return 0; |
ae8f1541 | 153 | } |
2b0d8c25 | 154 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 155 | |
2b0d8c25 | 156 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
157 | { |
158 | char *p = "buffered"; | |
159 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
160 | early_cachepolicy(p); |
161 | return 0; | |
ae8f1541 | 162 | } |
2b0d8c25 | 163 | early_param("nocache", early_nocache); |
ae8f1541 | 164 | |
2b0d8c25 | 165 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
166 | { |
167 | char *p = "uncached"; | |
168 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
169 | early_cachepolicy(p); |
170 | return 0; | |
ae8f1541 | 171 | } |
2b0d8c25 | 172 | early_param("nowb", early_nowrite); |
ae8f1541 | 173 | |
1b6ba46b | 174 | #ifndef CONFIG_ARM_LPAE |
2b0d8c25 | 175 | static int __init early_ecc(char *p) |
ae8f1541 | 176 | { |
2b0d8c25 | 177 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 178 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 179 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 180 | ecc_mask = 0; |
2b0d8c25 | 181 | return 0; |
ae8f1541 | 182 | } |
2b0d8c25 | 183 | early_param("ecc", early_ecc); |
1b6ba46b | 184 | #endif |
ae8f1541 RK |
185 | |
186 | static int __init noalign_setup(char *__unused) | |
187 | { | |
188 | cr_alignment &= ~CR_A; | |
189 | cr_no_alignment &= ~CR_A; | |
190 | set_cr(cr_alignment); | |
191 | return 1; | |
192 | } | |
193 | __setup("noalign", noalign_setup); | |
194 | ||
255d1f86 RK |
195 | #ifndef CONFIG_SMP |
196 | void adjust_cr(unsigned long mask, unsigned long set) | |
197 | { | |
198 | unsigned long flags; | |
199 | ||
200 | mask &= ~CR_A; | |
201 | ||
202 | set &= mask; | |
203 | ||
204 | local_irq_save(flags); | |
205 | ||
206 | cr_no_alignment = (cr_no_alignment & ~mask) | set; | |
207 | cr_alignment = (cr_alignment & ~mask) | set; | |
208 | ||
209 | set_cr((get_cr() & ~mask) | set); | |
210 | ||
211 | local_irq_restore(flags); | |
212 | } | |
213 | #endif | |
214 | ||
b849a60e UKK |
215 | #else /* ifdef CONFIG_CPU_CP15 */ |
216 | ||
217 | static int __init early_cachepolicy(char *p) | |
218 | { | |
219 | pr_warning("cachepolicy kernel parameter not supported without cp15\n"); | |
220 | } | |
221 | early_param("cachepolicy", early_cachepolicy); | |
222 | ||
223 | static int __init noalign_setup(char *__unused) | |
224 | { | |
225 | pr_warning("noalign kernel parameter not supported without cp15\n"); | |
226 | } | |
227 | __setup("noalign", noalign_setup); | |
228 | ||
229 | #endif /* ifdef CONFIG_CPU_CP15 / else */ | |
230 | ||
36bb94ba | 231 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
b1cce6b1 | 232 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 233 | |
b29e9f5e | 234 | static struct mem_type mem_types[] = { |
0af92bef | 235 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
236 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
237 | L_PTE_SHARED, | |
0af92bef | 238 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 239 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
240 | .domain = DOMAIN_IO, |
241 | }, | |
242 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 243 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 244 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 245 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
246 | .domain = DOMAIN_IO, |
247 | }, | |
248 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 249 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
250 | .prot_l1 = PMD_TYPE_TABLE, |
251 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
252 | .domain = DOMAIN_IO, | |
c2794437 | 253 | }, |
1ad77a87 | 254 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 255 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 256 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 257 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 258 | .domain = DOMAIN_IO, |
ae8f1541 | 259 | }, |
ebb4c658 RK |
260 | [MT_UNCACHED] = { |
261 | .prot_pte = PROT_PTE_DEVICE, | |
262 | .prot_l1 = PMD_TYPE_TABLE, | |
263 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
264 | .domain = DOMAIN_IO, | |
265 | }, | |
ae8f1541 | 266 | [MT_CACHECLEAN] = { |
9ef79635 | 267 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
268 | .domain = DOMAIN_KERNEL, |
269 | }, | |
1b6ba46b | 270 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 | 271 | [MT_MINICLEAN] = { |
9ef79635 | 272 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
273 | .domain = DOMAIN_KERNEL, |
274 | }, | |
1b6ba46b | 275 | #endif |
ae8f1541 RK |
276 | [MT_LOW_VECTORS] = { |
277 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 278 | L_PTE_RDONLY, |
ae8f1541 RK |
279 | .prot_l1 = PMD_TYPE_TABLE, |
280 | .domain = DOMAIN_USER, | |
281 | }, | |
282 | [MT_HIGH_VECTORS] = { | |
283 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 284 | L_PTE_USER | L_PTE_RDONLY, |
ae8f1541 RK |
285 | .prot_l1 = PMD_TYPE_TABLE, |
286 | .domain = DOMAIN_USER, | |
287 | }, | |
288 | [MT_MEMORY] = { | |
36bb94ba | 289 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
f1a2481c | 290 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 291 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
292 | .domain = DOMAIN_KERNEL, |
293 | }, | |
294 | [MT_ROM] = { | |
9ef79635 | 295 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
296 | .domain = DOMAIN_KERNEL, |
297 | }, | |
e4707dd3 | 298 | [MT_MEMORY_NONCACHED] = { |
f1a2481c | 299 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 300 | L_PTE_MT_BUFFERABLE, |
f1a2481c | 301 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
302 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
303 | .domain = DOMAIN_KERNEL, | |
304 | }, | |
cb9d7707 | 305 | [MT_MEMORY_DTCM] = { |
f444fce3 | 306 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 307 | L_PTE_XN, |
f444fce3 LW |
308 | .prot_l1 = PMD_TYPE_TABLE, |
309 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
310 | .domain = DOMAIN_KERNEL, | |
cb9d7707 LW |
311 | }, |
312 | [MT_MEMORY_ITCM] = { | |
36bb94ba | 313 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
cb9d7707 | 314 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 315 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 316 | }, |
8fb54284 SS |
317 | [MT_MEMORY_SO] = { |
318 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
93d5bf07 | 319 | L_PTE_MT_UNCACHED | L_PTE_XN, |
8fb54284 SS |
320 | .prot_l1 = PMD_TYPE_TABLE, |
321 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | | |
322 | PMD_SECT_UNCACHED | PMD_SECT_XN, | |
323 | .domain = DOMAIN_KERNEL, | |
324 | }, | |
c7909509 MS |
325 | [MT_MEMORY_DMA_READY] = { |
326 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, | |
327 | .prot_l1 = PMD_TYPE_TABLE, | |
328 | .domain = DOMAIN_KERNEL, | |
329 | }, | |
ae8f1541 RK |
330 | }; |
331 | ||
b29e9f5e RK |
332 | const struct mem_type *get_mem_type(unsigned int type) |
333 | { | |
334 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
335 | } | |
69d3a84a | 336 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 337 | |
ae8f1541 RK |
338 | /* |
339 | * Adjust the PMD section entries according to the CPU in use. | |
340 | */ | |
341 | static void __init build_mem_type_table(void) | |
342 | { | |
343 | struct cachepolicy *cp; | |
344 | unsigned int cr = get_cr(); | |
442e70c0 | 345 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
cc577c26 | 346 | pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot; |
ae8f1541 RK |
347 | int cpu_arch = cpu_architecture(); |
348 | int i; | |
349 | ||
11179d8c | 350 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 351 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
352 | if (cachepolicy > CPOLICY_BUFFERED) |
353 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 354 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
355 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
356 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 357 | #endif |
11179d8c | 358 | } |
ae8f1541 RK |
359 | if (cpu_arch < CPU_ARCH_ARMv5) { |
360 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
361 | cachepolicy = CPOLICY_WRITEBACK; | |
362 | ecc_mask = 0; | |
363 | } | |
f00ec48f RK |
364 | if (is_smp()) |
365 | cachepolicy = CPOLICY_WRITEALLOC; | |
ae8f1541 | 366 | |
1ad77a87 | 367 | /* |
b1cce6b1 RK |
368 | * Strip out features not present on earlier architectures. |
369 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
370 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 371 | */ |
b1cce6b1 RK |
372 | if (cpu_arch < CPU_ARCH_ARMv5) |
373 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
374 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
375 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
376 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
377 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
378 | |
379 | /* | |
b1cce6b1 RK |
380 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
381 | * "update-able on write" bit on ARM610). However, Xscale and | |
382 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 383 | */ |
b1cce6b1 | 384 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
9ef79635 | 385 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 386 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
387 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
388 | } | |
389 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
390 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
391 | if (mem_types[i].prot_l1) |
392 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
393 | if (mem_types[i].prot_sect) |
394 | mem_types[i].prot_sect |= PMD_BIT4; | |
395 | } | |
396 | } | |
ae8f1541 | 397 | |
b1cce6b1 RK |
398 | /* |
399 | * Mark the device areas according to the CPU/architecture. | |
400 | */ | |
401 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
402 | if (!cpu_is_xsc3()) { | |
403 | /* | |
404 | * Mark device regions on ARMv6+ as execute-never | |
405 | * to prevent speculative instruction fetches. | |
406 | */ | |
407 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
408 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
409 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
410 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
411 | } | |
412 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
413 | /* | |
414 | * For ARMv7 with TEX remapping, | |
415 | * - shared device is SXCB=1100 | |
416 | * - nonshared device is SXCB=0100 | |
417 | * - write combine device mem is SXCB=0001 | |
418 | * (Uncached Normal memory) | |
419 | */ | |
420 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
421 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
422 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
423 | } else if (cpu_is_xsc3()) { | |
424 | /* | |
425 | * For Xscale3, | |
426 | * - shared device is TEXCB=00101 | |
427 | * - nonshared device is TEXCB=01000 | |
428 | * - write combine device mem is TEXCB=00100 | |
429 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
430 | */ | |
431 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
432 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
433 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
434 | } else { | |
435 | /* | |
436 | * For ARMv6 and ARMv7 without TEX remapping, | |
437 | * - shared device is TEXCB=00001 | |
438 | * - nonshared device is TEXCB=01000 | |
439 | * - write combine device mem is TEXCB=00100 | |
440 | * (Uncached Normal in ARMv6 parlance). | |
441 | */ | |
442 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
443 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
444 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
445 | } | |
446 | } else { | |
447 | /* | |
448 | * On others, write combining is "Uncached/Buffered" | |
449 | */ | |
450 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
451 | } | |
452 | ||
453 | /* | |
454 | * Now deal with the memory-type mappings | |
455 | */ | |
ae8f1541 | 456 | cp = &cache_policies[cachepolicy]; |
bb30f36f | 457 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
cc577c26 CD |
458 | s2_pgprot = cp->pte_s2; |
459 | hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte; | |
bb30f36f | 460 | |
ae8f1541 RK |
461 | /* |
462 | * ARMv6 and above have extended page tables. | |
463 | */ | |
464 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
1b6ba46b | 465 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
466 | /* |
467 | * Mark cache clean areas and XIP ROM read only | |
468 | * from SVC mode and no access from userspace. | |
469 | */ | |
470 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
471 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
472 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
1b6ba46b | 473 | #endif |
ae8f1541 | 474 | |
f00ec48f RK |
475 | if (is_smp()) { |
476 | /* | |
477 | * Mark memory with the "shared" attribute | |
478 | * for SMP systems | |
479 | */ | |
480 | user_pgprot |= L_PTE_SHARED; | |
481 | kern_pgprot |= L_PTE_SHARED; | |
482 | vecs_pgprot |= L_PTE_SHARED; | |
cc577c26 | 483 | s2_pgprot |= L_PTE_SHARED; |
f00ec48f RK |
484 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; |
485 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
486 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
487 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
488 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | |
489 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; | |
c7909509 | 490 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
f00ec48f RK |
491 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; |
492 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
493 | } | |
ae8f1541 RK |
494 | } |
495 | ||
e4707dd3 PW |
496 | /* |
497 | * Non-cacheable Normal - intended for memory areas that must | |
498 | * not cause dirty cache line writebacks when used | |
499 | */ | |
500 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
501 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
502 | /* Non-cacheable Normal is XCB = 001 */ | |
503 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
504 | PMD_SECT_BUFFERED; | |
505 | } else { | |
506 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
507 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
508 | PMD_SECT_TEX(1); | |
509 | } | |
510 | } else { | |
511 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; | |
512 | } | |
513 | ||
1b6ba46b CM |
514 | #ifdef CONFIG_ARM_LPAE |
515 | /* | |
516 | * Do not generate access flag faults for the kernel mappings. | |
517 | */ | |
518 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
519 | mem_types[i].prot_pte |= PTE_EXT_AF; | |
1a3abcf4 VA |
520 | if (mem_types[i].prot_sect) |
521 | mem_types[i].prot_sect |= PMD_SECT_AF; | |
1b6ba46b CM |
522 | } |
523 | kern_pgprot |= PTE_EXT_AF; | |
524 | vecs_pgprot |= PTE_EXT_AF; | |
525 | #endif | |
526 | ||
ae8f1541 | 527 | for (i = 0; i < 16; i++) { |
864aa04c | 528 | pteval_t v = pgprot_val(protection_map[i]); |
bb30f36f | 529 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
530 | } |
531 | ||
bb30f36f RK |
532 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
533 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 534 | |
44b18693 | 535 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 536 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
36bb94ba | 537 | L_PTE_DIRTY | kern_pgprot); |
cc577c26 CD |
538 | pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot); |
539 | pgprot_s2_device = __pgprot(s2_device_pgprot); | |
540 | pgprot_hyp_device = __pgprot(hyp_device_pgprot); | |
ae8f1541 RK |
541 | |
542 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
543 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
544 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; | |
f1a2481c | 545 | mem_types[MT_MEMORY].prot_pte |= kern_pgprot; |
c7909509 | 546 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; |
f1a2481c | 547 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; |
ae8f1541 RK |
548 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
549 | ||
550 | switch (cp->pmd) { | |
551 | case PMD_SECT_WT: | |
552 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
553 | break; | |
554 | case PMD_SECT_WB: | |
555 | case PMD_SECT_WBWA: | |
556 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
557 | break; | |
558 | } | |
559 | printk("Memory policy: ECC %sabled, Data cache %s\n", | |
560 | ecc_mask ? "en" : "dis", cp->policy); | |
2497f0a8 RK |
561 | |
562 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
563 | struct mem_type *t = &mem_types[i]; | |
564 | if (t->prot_l1) | |
565 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
566 | if (t->prot_sect) | |
567 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
568 | } | |
ae8f1541 RK |
569 | } |
570 | ||
d907387c CM |
571 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
572 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
573 | unsigned long size, pgprot_t vma_prot) | |
574 | { | |
575 | if (!pfn_valid(pfn)) | |
576 | return pgprot_noncached(vma_prot); | |
577 | else if (file->f_flags & O_SYNC) | |
578 | return pgprot_writecombine(vma_prot); | |
579 | return vma_prot; | |
580 | } | |
581 | EXPORT_SYMBOL(phys_mem_access_prot); | |
582 | #endif | |
583 | ||
ae8f1541 RK |
584 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
585 | ||
0536bdf3 | 586 | static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) |
3abe9d33 | 587 | { |
0536bdf3 | 588 | void *ptr = __va(memblock_alloc(sz, align)); |
2778f620 RK |
589 | memset(ptr, 0, sz); |
590 | return ptr; | |
3abe9d33 RK |
591 | } |
592 | ||
0536bdf3 NP |
593 | static void __init *early_alloc(unsigned long sz) |
594 | { | |
595 | return early_alloc_aligned(sz, sz); | |
596 | } | |
597 | ||
4bb2e27d | 598 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) |
ae8f1541 | 599 | { |
24e6c699 | 600 | if (pmd_none(*pmd)) { |
410f1483 | 601 | pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
97092e0c | 602 | __pmd_populate(pmd, __pa(pte), prot); |
24e6c699 | 603 | } |
4bb2e27d RK |
604 | BUG_ON(pmd_bad(*pmd)); |
605 | return pte_offset_kernel(pmd, addr); | |
606 | } | |
ae8f1541 | 607 | |
4bb2e27d RK |
608 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
609 | unsigned long end, unsigned long pfn, | |
610 | const struct mem_type *type) | |
611 | { | |
612 | pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); | |
24e6c699 | 613 | do { |
40d192b6 | 614 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
24e6c699 RK |
615 | pfn++; |
616 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
617 | } |
618 | ||
37468b30 | 619 | static void __init __map_init_section(pmd_t *pmd, unsigned long addr, |
e651eab0 S |
620 | unsigned long end, phys_addr_t phys, |
621 | const struct mem_type *type) | |
ae8f1541 | 622 | { |
37468b30 PYC |
623 | pmd_t *p = pmd; |
624 | ||
e651eab0 | 625 | #ifndef CONFIG_ARM_LPAE |
24e6c699 | 626 | /* |
e651eab0 S |
627 | * In classic MMU format, puds and pmds are folded in to |
628 | * the pgds. pmd_offset gives the PGD entry. PGDs refer to a | |
629 | * group of L1 entries making up one logical pointer to | |
630 | * an L2 table (2MB), where as PMDs refer to the individual | |
631 | * L1 entries (1MB). Hence increment to get the correct | |
632 | * offset for odd 1MB sections. | |
633 | * (See arch/arm/include/asm/pgtable-2level.h) | |
24e6c699 | 634 | */ |
e651eab0 S |
635 | if (addr & SECTION_SIZE) |
636 | pmd++; | |
1b6ba46b | 637 | #endif |
e651eab0 S |
638 | do { |
639 | *pmd = __pmd(phys | type->prot_sect); | |
640 | phys += SECTION_SIZE; | |
641 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
24e6c699 | 642 | |
37468b30 | 643 | flush_pmd_entry(p); |
e651eab0 | 644 | } |
ae8f1541 | 645 | |
e651eab0 S |
646 | static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, |
647 | unsigned long end, phys_addr_t phys, | |
648 | const struct mem_type *type) | |
649 | { | |
650 | pmd_t *pmd = pmd_offset(pud, addr); | |
651 | unsigned long next; | |
652 | ||
653 | do { | |
24e6c699 | 654 | /* |
e651eab0 S |
655 | * With LPAE, we must loop over to map |
656 | * all the pmds for the given range. | |
24e6c699 | 657 | */ |
e651eab0 S |
658 | next = pmd_addr_end(addr, end); |
659 | ||
660 | /* | |
661 | * Try a section mapping - addr, next and phys must all be | |
662 | * aligned to a section boundary. | |
663 | */ | |
664 | if (type->prot_sect && | |
665 | ((addr | next | phys) & ~SECTION_MASK) == 0) { | |
37468b30 | 666 | __map_init_section(pmd, addr, next, phys, type); |
e651eab0 S |
667 | } else { |
668 | alloc_init_pte(pmd, addr, next, | |
669 | __phys_to_pfn(phys), type); | |
670 | } | |
671 | ||
672 | phys += next - addr; | |
673 | ||
674 | } while (pmd++, addr = next, addr != end); | |
ae8f1541 RK |
675 | } |
676 | ||
14904927 | 677 | static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, |
20d6956d VA |
678 | unsigned long end, phys_addr_t phys, |
679 | const struct mem_type *type) | |
516295e5 RK |
680 | { |
681 | pud_t *pud = pud_offset(pgd, addr); | |
682 | unsigned long next; | |
683 | ||
684 | do { | |
685 | next = pud_addr_end(addr, end); | |
e651eab0 | 686 | alloc_init_pmd(pud, addr, next, phys, type); |
516295e5 RK |
687 | phys += next - addr; |
688 | } while (pud++, addr = next, addr != end); | |
689 | } | |
690 | ||
1b6ba46b | 691 | #ifndef CONFIG_ARM_LPAE |
4a56c1e4 RK |
692 | static void __init create_36bit_mapping(struct map_desc *md, |
693 | const struct mem_type *type) | |
694 | { | |
97092e0c RK |
695 | unsigned long addr, length, end; |
696 | phys_addr_t phys; | |
4a56c1e4 RK |
697 | pgd_t *pgd; |
698 | ||
699 | addr = md->virtual; | |
cae6292b | 700 | phys = __pfn_to_phys(md->pfn); |
4a56c1e4 RK |
701 | length = PAGE_ALIGN(md->length); |
702 | ||
703 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
704 | printk(KERN_ERR "MM: CPU does not support supersection " | |
705 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 706 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
707 | return; |
708 | } | |
709 | ||
710 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
711 | * Since domain assignments can in fact be arbitrary, the | |
712 | * 'domain == 0' check below is required to insure that ARMv6 | |
713 | * supersections are only allocated for domain 0 regardless | |
714 | * of the actual domain assignments in use. | |
715 | */ | |
716 | if (type->domain) { | |
717 | printk(KERN_ERR "MM: invalid domain in supersection " | |
718 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 719 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
720 | return; |
721 | } | |
722 | ||
723 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
29a38193 WD |
724 | printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" |
725 | " at 0x%08lx invalid alignment\n", | |
726 | (long long)__pfn_to_phys((u64)md->pfn), addr); | |
4a56c1e4 RK |
727 | return; |
728 | } | |
729 | ||
730 | /* | |
731 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
732 | * (See ARMv6 spec). | |
733 | */ | |
734 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
735 | ||
736 | pgd = pgd_offset_k(addr); | |
737 | end = addr + length; | |
738 | do { | |
516295e5 RK |
739 | pud_t *pud = pud_offset(pgd, addr); |
740 | pmd_t *pmd = pmd_offset(pud, addr); | |
4a56c1e4 RK |
741 | int i; |
742 | ||
743 | for (i = 0; i < 16; i++) | |
744 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
745 | ||
746 | addr += SUPERSECTION_SIZE; | |
747 | phys += SUPERSECTION_SIZE; | |
748 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
749 | } while (addr != end); | |
750 | } | |
1b6ba46b | 751 | #endif /* !CONFIG_ARM_LPAE */ |
4a56c1e4 | 752 | |
ae8f1541 RK |
753 | /* |
754 | * Create the page directory entries and any necessary | |
755 | * page tables for the mapping specified by `md'. We | |
756 | * are able to cope here with varying sizes and address | |
757 | * offsets, and we take full advantage of sections and | |
758 | * supersections. | |
759 | */ | |
a2227120 | 760 | static void __init create_mapping(struct map_desc *md) |
ae8f1541 | 761 | { |
cae6292b WD |
762 | unsigned long addr, length, end; |
763 | phys_addr_t phys; | |
d5c98176 | 764 | const struct mem_type *type; |
24e6c699 | 765 | pgd_t *pgd; |
ae8f1541 RK |
766 | |
767 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
29a38193 WD |
768 | printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" |
769 | " at 0x%08lx in user region\n", | |
770 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
ae8f1541 RK |
771 | return; |
772 | } | |
773 | ||
774 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
0536bdf3 NP |
775 | md->virtual >= PAGE_OFFSET && |
776 | (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { | |
29a38193 | 777 | printk(KERN_WARNING "BUG: mapping for 0x%08llx" |
0536bdf3 | 778 | " at 0x%08lx out of vmalloc space\n", |
29a38193 | 779 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); |
ae8f1541 RK |
780 | } |
781 | ||
d5c98176 | 782 | type = &mem_types[md->type]; |
ae8f1541 | 783 | |
1b6ba46b | 784 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
785 | /* |
786 | * Catch 36-bit addresses | |
787 | */ | |
4a56c1e4 RK |
788 | if (md->pfn >= 0x100000) { |
789 | create_36bit_mapping(md, type); | |
790 | return; | |
ae8f1541 | 791 | } |
1b6ba46b | 792 | #endif |
ae8f1541 | 793 | |
7b9c7b4d | 794 | addr = md->virtual & PAGE_MASK; |
cae6292b | 795 | phys = __pfn_to_phys(md->pfn); |
7b9c7b4d | 796 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 797 | |
24e6c699 | 798 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
29a38193 | 799 | printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " |
ae8f1541 | 800 | "be mapped using pages, ignoring.\n", |
29a38193 | 801 | (long long)__pfn_to_phys(md->pfn), addr); |
ae8f1541 RK |
802 | return; |
803 | } | |
804 | ||
24e6c699 RK |
805 | pgd = pgd_offset_k(addr); |
806 | end = addr + length; | |
807 | do { | |
808 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 809 | |
516295e5 | 810 | alloc_init_pud(pgd, addr, next, phys, type); |
ae8f1541 | 811 | |
24e6c699 RK |
812 | phys += next - addr; |
813 | addr = next; | |
814 | } while (pgd++, addr != end); | |
ae8f1541 RK |
815 | } |
816 | ||
817 | /* | |
818 | * Create the architecture specific mappings | |
819 | */ | |
820 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
821 | { | |
0536bdf3 NP |
822 | struct map_desc *md; |
823 | struct vm_struct *vm; | |
101eeda3 | 824 | struct static_vm *svm; |
0536bdf3 NP |
825 | |
826 | if (!nr) | |
827 | return; | |
ae8f1541 | 828 | |
101eeda3 | 829 | svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm)); |
0536bdf3 NP |
830 | |
831 | for (md = io_desc; nr; md++, nr--) { | |
832 | create_mapping(md); | |
101eeda3 JK |
833 | |
834 | vm = &svm->vm; | |
0536bdf3 NP |
835 | vm->addr = (void *)(md->virtual & PAGE_MASK); |
836 | vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); | |
c2794437 RH |
837 | vm->phys_addr = __pfn_to_phys(md->pfn); |
838 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; | |
576d2f25 | 839 | vm->flags |= VM_ARM_MTYPE(md->type); |
0536bdf3 | 840 | vm->caller = iotable_init; |
101eeda3 | 841 | add_static_vm_early(svm++); |
0536bdf3 | 842 | } |
ae8f1541 RK |
843 | } |
844 | ||
c2794437 RH |
845 | void __init vm_reserve_area_early(unsigned long addr, unsigned long size, |
846 | void *caller) | |
847 | { | |
848 | struct vm_struct *vm; | |
101eeda3 JK |
849 | struct static_vm *svm; |
850 | ||
851 | svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm)); | |
c2794437 | 852 | |
101eeda3 | 853 | vm = &svm->vm; |
c2794437 RH |
854 | vm->addr = (void *)addr; |
855 | vm->size = size; | |
863e99a8 | 856 | vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; |
c2794437 | 857 | vm->caller = caller; |
101eeda3 | 858 | add_static_vm_early(svm); |
c2794437 RH |
859 | } |
860 | ||
19b52abe NP |
861 | #ifndef CONFIG_ARM_LPAE |
862 | ||
863 | /* | |
864 | * The Linux PMD is made of two consecutive section entries covering 2MB | |
865 | * (see definition in include/asm/pgtable-2level.h). However a call to | |
866 | * create_mapping() may optimize static mappings by using individual | |
867 | * 1MB section mappings. This leaves the actual PMD potentially half | |
868 | * initialized if the top or bottom section entry isn't used, leaving it | |
869 | * open to problems if a subsequent ioremap() or vmalloc() tries to use | |
870 | * the virtual space left free by that unused section entry. | |
871 | * | |
872 | * Let's avoid the issue by inserting dummy vm entries covering the unused | |
873 | * PMD halves once the static mappings are in place. | |
874 | */ | |
875 | ||
876 | static void __init pmd_empty_section_gap(unsigned long addr) | |
877 | { | |
c2794437 | 878 | vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); |
19b52abe NP |
879 | } |
880 | ||
881 | static void __init fill_pmd_gaps(void) | |
882 | { | |
101eeda3 | 883 | struct static_vm *svm; |
19b52abe NP |
884 | struct vm_struct *vm; |
885 | unsigned long addr, next = 0; | |
886 | pmd_t *pmd; | |
887 | ||
101eeda3 JK |
888 | list_for_each_entry(svm, &static_vmlist, list) { |
889 | vm = &svm->vm; | |
19b52abe NP |
890 | addr = (unsigned long)vm->addr; |
891 | if (addr < next) | |
892 | continue; | |
893 | ||
894 | /* | |
895 | * Check if this vm starts on an odd section boundary. | |
896 | * If so and the first section entry for this PMD is free | |
897 | * then we block the corresponding virtual address. | |
898 | */ | |
899 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
900 | pmd = pmd_off_k(addr); | |
901 | if (pmd_none(*pmd)) | |
902 | pmd_empty_section_gap(addr & PMD_MASK); | |
903 | } | |
904 | ||
905 | /* | |
906 | * Then check if this vm ends on an odd section boundary. | |
907 | * If so and the second section entry for this PMD is empty | |
908 | * then we block the corresponding virtual address. | |
909 | */ | |
910 | addr += vm->size; | |
911 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
912 | pmd = pmd_off_k(addr) + 1; | |
913 | if (pmd_none(*pmd)) | |
914 | pmd_empty_section_gap(addr); | |
915 | } | |
916 | ||
917 | /* no need to look at any vm entry until we hit the next PMD */ | |
918 | next = (addr + PMD_SIZE - 1) & PMD_MASK; | |
919 | } | |
920 | } | |
921 | ||
922 | #else | |
923 | #define fill_pmd_gaps() do { } while (0) | |
924 | #endif | |
925 | ||
c2794437 RH |
926 | #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) |
927 | static void __init pci_reserve_io(void) | |
928 | { | |
101eeda3 | 929 | struct static_vm *svm; |
c2794437 | 930 | |
101eeda3 JK |
931 | svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); |
932 | if (svm) | |
933 | return; | |
c2794437 | 934 | |
c2794437 RH |
935 | vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); |
936 | } | |
937 | #else | |
938 | #define pci_reserve_io() do { } while (0) | |
939 | #endif | |
940 | ||
e5c5f2ad RH |
941 | #ifdef CONFIG_DEBUG_LL |
942 | void __init debug_ll_io_init(void) | |
943 | { | |
944 | struct map_desc map; | |
945 | ||
946 | debug_ll_addr(&map.pfn, &map.virtual); | |
947 | if (!map.pfn || !map.virtual) | |
948 | return; | |
949 | map.pfn = __phys_to_pfn(map.pfn); | |
950 | map.virtual &= PAGE_MASK; | |
951 | map.length = PAGE_SIZE; | |
952 | map.type = MT_DEVICE; | |
953 | create_mapping(&map); | |
954 | } | |
955 | #endif | |
956 | ||
0536bdf3 NP |
957 | static void * __initdata vmalloc_min = |
958 | (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); | |
6c5da7ac RK |
959 | |
960 | /* | |
961 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
962 | * bytes. This can be used to increase (or decrease) the vmalloc | |
0536bdf3 | 963 | * area - the default is 240m. |
6c5da7ac | 964 | */ |
2b0d8c25 | 965 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 966 | { |
79612395 | 967 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
968 | |
969 | if (vmalloc_reserve < SZ_16M) { | |
970 | vmalloc_reserve = SZ_16M; | |
971 | printk(KERN_WARNING | |
972 | "vmalloc area too small, limiting to %luMB\n", | |
973 | vmalloc_reserve >> 20); | |
974 | } | |
9210807c NP |
975 | |
976 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
977 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
978 | printk(KERN_WARNING | |
979 | "vmalloc area is too big, limiting to %luMB\n", | |
980 | vmalloc_reserve >> 20); | |
981 | } | |
79612395 RK |
982 | |
983 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); | |
2b0d8c25 | 984 | return 0; |
6c5da7ac | 985 | } |
2b0d8c25 | 986 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 987 | |
c7909509 | 988 | phys_addr_t arm_lowmem_limit __initdata = 0; |
8df65168 | 989 | |
0371d3f7 | 990 | void __init sanity_check_meminfo(void) |
60296c71 | 991 | { |
dde5828f | 992 | int i, j, highmem = 0; |
82f66704 | 993 | phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1; |
60296c71 | 994 | |
4b5f32ce | 995 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
a1bbaec0 | 996 | struct membank *bank = &meminfo.bank[j]; |
28d4bf7a | 997 | phys_addr_t size_limit; |
60296c71 | 998 | |
a1bbaec0 | 999 | *bank = meminfo.bank[i]; |
28d4bf7a | 1000 | size_limit = bank->size; |
77f73a2c | 1001 | |
82f66704 | 1002 | if (bank->start >= vmalloc_limit) |
dde5828f | 1003 | highmem = 1; |
28d4bf7a CC |
1004 | else |
1005 | size_limit = vmalloc_limit - bank->start; | |
dde5828f RK |
1006 | |
1007 | bank->highmem = highmem; | |
1008 | ||
adf2e9fd | 1009 | #ifdef CONFIG_HIGHMEM |
a1bbaec0 NP |
1010 | /* |
1011 | * Split those memory banks which are partially overlapping | |
1012 | * the vmalloc area greatly simplifying things later. | |
1013 | */ | |
28d4bf7a | 1014 | if (!highmem && bank->size > size_limit) { |
a1bbaec0 NP |
1015 | if (meminfo.nr_banks >= NR_BANKS) { |
1016 | printk(KERN_CRIT "NR_BANKS too low, " | |
1017 | "ignoring high memory\n"); | |
1018 | } else { | |
1019 | memmove(bank + 1, bank, | |
1020 | (meminfo.nr_banks - i) * sizeof(*bank)); | |
1021 | meminfo.nr_banks++; | |
1022 | i++; | |
28d4bf7a | 1023 | bank[1].size -= size_limit; |
82f66704 | 1024 | bank[1].start = vmalloc_limit; |
dde5828f | 1025 | bank[1].highmem = highmem = 1; |
a1bbaec0 NP |
1026 | j++; |
1027 | } | |
28d4bf7a | 1028 | bank->size = size_limit; |
a1bbaec0 NP |
1029 | } |
1030 | #else | |
77f73a2c WD |
1031 | /* |
1032 | * Highmem banks not allowed with !CONFIG_HIGHMEM. | |
1033 | */ | |
1034 | if (highmem) { | |
1035 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " | |
1036 | "(!CONFIG_HIGHMEM).\n", | |
1037 | (unsigned long long)bank->start, | |
1038 | (unsigned long long)bank->start + bank->size - 1); | |
1039 | continue; | |
1040 | } | |
1041 | ||
a1bbaec0 NP |
1042 | /* |
1043 | * Check whether this memory bank would partially overlap | |
1044 | * the vmalloc area. | |
1045 | */ | |
28d4bf7a | 1046 | if (bank->size > size_limit) { |
e33b9d08 RK |
1047 | printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " |
1048 | "to -%.8llx (vmalloc region overlap).\n", | |
1049 | (unsigned long long)bank->start, | |
1050 | (unsigned long long)bank->start + bank->size - 1, | |
28d4bf7a CC |
1051 | (unsigned long long)bank->start + size_limit - 1); |
1052 | bank->size = size_limit; | |
a1bbaec0 NP |
1053 | } |
1054 | #endif | |
c7909509 MS |
1055 | if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit) |
1056 | arm_lowmem_limit = bank->start + bank->size; | |
40f7bfe4 | 1057 | |
a1bbaec0 | 1058 | j++; |
60296c71 | 1059 | } |
e616c591 RK |
1060 | #ifdef CONFIG_HIGHMEM |
1061 | if (highmem) { | |
1062 | const char *reason = NULL; | |
1063 | ||
1064 | if (cache_is_vipt_aliasing()) { | |
1065 | /* | |
1066 | * Interactions between kmap and other mappings | |
1067 | * make highmem support with aliasing VIPT caches | |
1068 | * rather difficult. | |
1069 | */ | |
1070 | reason = "with VIPT aliasing cache"; | |
e616c591 RK |
1071 | } |
1072 | if (reason) { | |
1073 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", | |
1074 | reason); | |
1075 | while (j > 0 && meminfo.bank[j - 1].highmem) | |
1076 | j--; | |
1077 | } | |
1078 | } | |
1079 | #endif | |
4b5f32ce | 1080 | meminfo.nr_banks = j; |
c7909509 MS |
1081 | high_memory = __va(arm_lowmem_limit - 1) + 1; |
1082 | memblock_set_current_limit(arm_lowmem_limit); | |
60296c71 LB |
1083 | } |
1084 | ||
4b5f32ce | 1085 | static inline void prepare_page_table(void) |
d111e8f9 RK |
1086 | { |
1087 | unsigned long addr; | |
8df65168 | 1088 | phys_addr_t end; |
d111e8f9 RK |
1089 | |
1090 | /* | |
1091 | * Clear out all the mappings below the kernel image. | |
1092 | */ | |
e73fc88e | 1093 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
d111e8f9 RK |
1094 | pmd_clear(pmd_off_k(addr)); |
1095 | ||
1096 | #ifdef CONFIG_XIP_KERNEL | |
1097 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
e73fc88e | 1098 | addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; |
d111e8f9 | 1099 | #endif |
e73fc88e | 1100 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
d111e8f9 RK |
1101 | pmd_clear(pmd_off_k(addr)); |
1102 | ||
8df65168 RK |
1103 | /* |
1104 | * Find the end of the first block of lowmem. | |
1105 | */ | |
1106 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; | |
c7909509 MS |
1107 | if (end >= arm_lowmem_limit) |
1108 | end = arm_lowmem_limit; | |
8df65168 | 1109 | |
d111e8f9 RK |
1110 | /* |
1111 | * Clear out all the kernel space mappings, except for the first | |
0536bdf3 | 1112 | * memory bank, up to the vmalloc region. |
d111e8f9 | 1113 | */ |
8df65168 | 1114 | for (addr = __phys_to_virt(end); |
0536bdf3 | 1115 | addr < VMALLOC_START; addr += PMD_SIZE) |
d111e8f9 RK |
1116 | pmd_clear(pmd_off_k(addr)); |
1117 | } | |
1118 | ||
1b6ba46b CM |
1119 | #ifdef CONFIG_ARM_LPAE |
1120 | /* the first page is reserved for pgd */ | |
1121 | #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ | |
1122 | PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) | |
1123 | #else | |
e73fc88e | 1124 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
1b6ba46b | 1125 | #endif |
e73fc88e | 1126 | |
d111e8f9 | 1127 | /* |
2778f620 | 1128 | * Reserve the special regions of memory |
d111e8f9 | 1129 | */ |
2778f620 | 1130 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 1131 | { |
d111e8f9 RK |
1132 | /* |
1133 | * Reserve the page tables. These are already in use, | |
1134 | * and can only be in node 0. | |
1135 | */ | |
e73fc88e | 1136 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
d111e8f9 | 1137 | |
d111e8f9 RK |
1138 | #ifdef CONFIG_SA1111 |
1139 | /* | |
1140 | * Because of the SA1111 DMA bug, we want to preserve our | |
1141 | * precious DMA-able memory... | |
1142 | */ | |
2778f620 | 1143 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 1144 | #endif |
d111e8f9 RK |
1145 | } |
1146 | ||
1147 | /* | |
0536bdf3 NP |
1148 | * Set up the device mappings. Since we clear out the page tables for all |
1149 | * mappings above VMALLOC_START, we will remove any debug device mappings. | |
d111e8f9 RK |
1150 | * This means you have to be careful how you debug this function, or any |
1151 | * called function. This means you can't use any function or debugging | |
1152 | * method which may touch any device, otherwise the kernel _will_ crash. | |
1153 | */ | |
1154 | static void __init devicemaps_init(struct machine_desc *mdesc) | |
1155 | { | |
1156 | struct map_desc map; | |
1157 | unsigned long addr; | |
94e5a85b | 1158 | void *vectors; |
d111e8f9 RK |
1159 | |
1160 | /* | |
1161 | * Allocate the vector page early. | |
1162 | */ | |
94e5a85b RK |
1163 | vectors = early_alloc(PAGE_SIZE); |
1164 | ||
1165 | early_trap_init(vectors); | |
d111e8f9 | 1166 | |
0536bdf3 | 1167 | for (addr = VMALLOC_START; addr; addr += PMD_SIZE) |
d111e8f9 RK |
1168 | pmd_clear(pmd_off_k(addr)); |
1169 | ||
1170 | /* | |
1171 | * Map the kernel if it is XIP. | |
1172 | * It is always first in the modulearea. | |
1173 | */ | |
1174 | #ifdef CONFIG_XIP_KERNEL | |
1175 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 1176 | map.virtual = MODULES_VADDR; |
37efe642 | 1177 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
1178 | map.type = MT_ROM; |
1179 | create_mapping(&map); | |
1180 | #endif | |
1181 | ||
1182 | /* | |
1183 | * Map the cache flushing regions. | |
1184 | */ | |
1185 | #ifdef FLUSH_BASE | |
1186 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
1187 | map.virtual = FLUSH_BASE; | |
1188 | map.length = SZ_1M; | |
1189 | map.type = MT_CACHECLEAN; | |
1190 | create_mapping(&map); | |
1191 | #endif | |
1192 | #ifdef FLUSH_BASE_MINICACHE | |
1193 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
1194 | map.virtual = FLUSH_BASE_MINICACHE; | |
1195 | map.length = SZ_1M; | |
1196 | map.type = MT_MINICLEAN; | |
1197 | create_mapping(&map); | |
1198 | #endif | |
1199 | ||
1200 | /* | |
1201 | * Create a mapping for the machine vectors at the high-vectors | |
1202 | * location (0xffff0000). If we aren't using high-vectors, also | |
1203 | * create a mapping at the low-vectors virtual address. | |
1204 | */ | |
94e5a85b | 1205 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
d111e8f9 RK |
1206 | map.virtual = 0xffff0000; |
1207 | map.length = PAGE_SIZE; | |
1208 | map.type = MT_HIGH_VECTORS; | |
1209 | create_mapping(&map); | |
1210 | ||
1211 | if (!vectors_high()) { | |
1212 | map.virtual = 0; | |
1213 | map.type = MT_LOW_VECTORS; | |
1214 | create_mapping(&map); | |
1215 | } | |
1216 | ||
1217 | /* | |
1218 | * Ask the machine support to map in the statically mapped devices. | |
1219 | */ | |
1220 | if (mdesc->map_io) | |
1221 | mdesc->map_io(); | |
bc37324e MR |
1222 | else |
1223 | debug_ll_io_init(); | |
19b52abe | 1224 | fill_pmd_gaps(); |
d111e8f9 | 1225 | |
c2794437 RH |
1226 | /* Reserve fixed i/o space in VMALLOC region */ |
1227 | pci_reserve_io(); | |
1228 | ||
d111e8f9 RK |
1229 | /* |
1230 | * Finally flush the caches and tlb to ensure that we're in a | |
1231 | * consistent state wrt the writebuffer. This also ensures that | |
1232 | * any write-allocated cache lines in the vector page are written | |
1233 | * back. After this point, we can start to touch devices again. | |
1234 | */ | |
1235 | local_flush_tlb_all(); | |
1236 | flush_cache_all(); | |
1237 | } | |
1238 | ||
d73cd428 NP |
1239 | static void __init kmap_init(void) |
1240 | { | |
1241 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
1242 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
1243 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
1244 | #endif |
1245 | } | |
1246 | ||
a2227120 RK |
1247 | static void __init map_lowmem(void) |
1248 | { | |
8df65168 | 1249 | struct memblock_region *reg; |
a2227120 RK |
1250 | |
1251 | /* Map all the lowmem memory banks. */ | |
8df65168 RK |
1252 | for_each_memblock(memory, reg) { |
1253 | phys_addr_t start = reg->base; | |
1254 | phys_addr_t end = start + reg->size; | |
1255 | struct map_desc map; | |
1256 | ||
c7909509 MS |
1257 | if (end > arm_lowmem_limit) |
1258 | end = arm_lowmem_limit; | |
8df65168 RK |
1259 | if (start >= end) |
1260 | break; | |
1261 | ||
1262 | map.pfn = __phys_to_pfn(start); | |
1263 | map.virtual = __phys_to_virt(start); | |
1264 | map.length = end - start; | |
1265 | map.type = MT_MEMORY; | |
a2227120 | 1266 | |
8df65168 | 1267 | create_mapping(&map); |
a2227120 RK |
1268 | } |
1269 | } | |
1270 | ||
d111e8f9 RK |
1271 | /* |
1272 | * paging_init() sets up the page tables, initialises the zone memory | |
1273 | * maps, and sets up the zero page, bad page and bad page tables. | |
1274 | */ | |
4b5f32ce | 1275 | void __init paging_init(struct machine_desc *mdesc) |
d111e8f9 RK |
1276 | { |
1277 | void *zero_page; | |
1278 | ||
c7909509 | 1279 | memblock_set_current_limit(arm_lowmem_limit); |
0371d3f7 | 1280 | |
d111e8f9 | 1281 | build_mem_type_table(); |
4b5f32ce | 1282 | prepare_page_table(); |
a2227120 | 1283 | map_lowmem(); |
c7909509 | 1284 | dma_contiguous_remap(); |
d111e8f9 | 1285 | devicemaps_init(mdesc); |
d73cd428 | 1286 | kmap_init(); |
de40614e | 1287 | tcm_init(); |
d111e8f9 RK |
1288 | |
1289 | top_pmd = pmd_off_k(0xffff0000); | |
1290 | ||
3abe9d33 RK |
1291 | /* allocate the zero page. */ |
1292 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1293 | |
8d717a52 | 1294 | bootmem_init(); |
2778f620 | 1295 | |
d111e8f9 | 1296 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1297 | __flush_dcache_page(NULL, empty_zero_page); |
d111e8f9 | 1298 | } |