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d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
d111e8f9 RK |
14 | #include <linux/mman.h> |
15 | #include <linux/nodemask.h> | |
2778f620 | 16 | #include <linux/memblock.h> |
d907387c | 17 | #include <linux/fs.h> |
0536bdf3 | 18 | #include <linux/vmalloc.h> |
158e8bfe | 19 | #include <linux/sizes.h> |
d111e8f9 | 20 | |
15d07dc9 | 21 | #include <asm/cp15.h> |
0ba8b9b2 | 22 | #include <asm/cputype.h> |
37efe642 | 23 | #include <asm/sections.h> |
3f973e22 | 24 | #include <asm/cachetype.h> |
99b4ac9a | 25 | #include <asm/fixmap.h> |
ebd4922e | 26 | #include <asm/sections.h> |
d111e8f9 | 27 | #include <asm/setup.h> |
e616c591 | 28 | #include <asm/smp_plat.h> |
d111e8f9 | 29 | #include <asm/tlb.h> |
d73cd428 | 30 | #include <asm/highmem.h> |
9f97da78 | 31 | #include <asm/system_info.h> |
247055aa | 32 | #include <asm/traps.h> |
a77e0c7b SS |
33 | #include <asm/procinfo.h> |
34 | #include <asm/memory.h> | |
d111e8f9 RK |
35 | |
36 | #include <asm/mach/arch.h> | |
37 | #include <asm/mach/map.h> | |
c2794437 | 38 | #include <asm/mach/pci.h> |
a05e54c1 | 39 | #include <asm/fixmap.h> |
d111e8f9 | 40 | |
9254970c | 41 | #include "fault.h" |
d111e8f9 | 42 | #include "mm.h" |
de40614e | 43 | #include "tcm.h" |
d111e8f9 | 44 | |
d111e8f9 RK |
45 | /* |
46 | * empty_zero_page is a special page that is used for | |
47 | * zero-initialized data and COW. | |
48 | */ | |
49 | struct page *empty_zero_page; | |
3653f3ab | 50 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
51 | |
52 | /* | |
53 | * The pmd table for the upper-most set of pages. | |
54 | */ | |
55 | pmd_t *top_pmd; | |
56 | ||
1d4d3715 JL |
57 | pmdval_t user_pmd_table = _PAGE_USER_TABLE; |
58 | ||
ae8f1541 RK |
59 | #define CPOLICY_UNCACHED 0 |
60 | #define CPOLICY_BUFFERED 1 | |
61 | #define CPOLICY_WRITETHROUGH 2 | |
62 | #define CPOLICY_WRITEBACK 3 | |
63 | #define CPOLICY_WRITEALLOC 4 | |
64 | ||
65 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
66 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 67 | pgprot_t pgprot_user; |
ae8f1541 | 68 | pgprot_t pgprot_kernel; |
cc577c26 CD |
69 | pgprot_t pgprot_hyp_device; |
70 | pgprot_t pgprot_s2; | |
71 | pgprot_t pgprot_s2_device; | |
ae8f1541 | 72 | |
44b18693 | 73 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
74 | EXPORT_SYMBOL(pgprot_kernel); |
75 | ||
76 | struct cachepolicy { | |
77 | const char policy[16]; | |
78 | unsigned int cr_mask; | |
442e70c0 | 79 | pmdval_t pmd; |
f6e3354d | 80 | pteval_t pte; |
cc577c26 | 81 | pteval_t pte_s2; |
ae8f1541 RK |
82 | }; |
83 | ||
cc577c26 CD |
84 | #ifdef CONFIG_ARM_LPAE |
85 | #define s2_policy(policy) policy | |
86 | #else | |
87 | #define s2_policy(policy) 0 | |
88 | #endif | |
89 | ||
ae8f1541 RK |
90 | static struct cachepolicy cache_policies[] __initdata = { |
91 | { | |
92 | .policy = "uncached", | |
93 | .cr_mask = CR_W|CR_C, | |
94 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 95 | .pte = L_PTE_MT_UNCACHED, |
cc577c26 | 96 | .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), |
ae8f1541 RK |
97 | }, { |
98 | .policy = "buffered", | |
99 | .cr_mask = CR_C, | |
100 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 101 | .pte = L_PTE_MT_BUFFERABLE, |
cc577c26 | 102 | .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), |
ae8f1541 RK |
103 | }, { |
104 | .policy = "writethrough", | |
105 | .cr_mask = 0, | |
106 | .pmd = PMD_SECT_WT, | |
bb30f36f | 107 | .pte = L_PTE_MT_WRITETHROUGH, |
cc577c26 | 108 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH), |
ae8f1541 RK |
109 | }, { |
110 | .policy = "writeback", | |
111 | .cr_mask = 0, | |
112 | .pmd = PMD_SECT_WB, | |
bb30f36f | 113 | .pte = L_PTE_MT_WRITEBACK, |
cc577c26 | 114 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), |
ae8f1541 RK |
115 | }, { |
116 | .policy = "writealloc", | |
117 | .cr_mask = 0, | |
118 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 119 | .pte = L_PTE_MT_WRITEALLOC, |
cc577c26 | 120 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), |
ae8f1541 RK |
121 | } |
122 | }; | |
123 | ||
b849a60e | 124 | #ifdef CONFIG_CPU_CP15 |
20e7e364 RK |
125 | static unsigned long initial_pmd_value __initdata = 0; |
126 | ||
ae8f1541 | 127 | /* |
ca8f0b0a RK |
128 | * Initialise the cache_policy variable with the initial state specified |
129 | * via the "pmd" value. This is used to ensure that on ARMv6 and later, | |
130 | * the C code sets the page tables up with the same policy as the head | |
131 | * assembly code, which avoids an illegal state where the TLBs can get | |
132 | * confused. See comments in early_cachepolicy() for more information. | |
ae8f1541 | 133 | */ |
ca8f0b0a | 134 | void __init init_default_cache_policy(unsigned long pmd) |
ae8f1541 RK |
135 | { |
136 | int i; | |
137 | ||
20e7e364 RK |
138 | initial_pmd_value = pmd; |
139 | ||
ca8f0b0a RK |
140 | pmd &= PMD_SECT_TEX(1) | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE; |
141 | ||
142 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) | |
143 | if (cache_policies[i].pmd == pmd) { | |
144 | cachepolicy = i; | |
145 | break; | |
146 | } | |
147 | ||
148 | if (i == ARRAY_SIZE(cache_policies)) | |
149 | pr_err("ERROR: could not find cache policy\n"); | |
150 | } | |
151 | ||
152 | /* | |
153 | * These are useful for identifying cache coherency problems by allowing | |
154 | * the cache or the cache and writebuffer to be turned off. (Note: the | |
155 | * write buffer should not be on and the cache off). | |
156 | */ | |
157 | static int __init early_cachepolicy(char *p) | |
158 | { | |
159 | int i, selected = -1; | |
160 | ||
ae8f1541 RK |
161 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { |
162 | int len = strlen(cache_policies[i].policy); | |
163 | ||
2b0d8c25 | 164 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ca8f0b0a | 165 | selected = i; |
ae8f1541 RK |
166 | break; |
167 | } | |
168 | } | |
ca8f0b0a RK |
169 | |
170 | if (selected == -1) | |
171 | pr_err("ERROR: unknown or unsupported cache policy\n"); | |
172 | ||
4b46d641 RK |
173 | /* |
174 | * This restriction is partly to do with the way we boot; it is | |
175 | * unpredictable to have memory mapped using two different sets of | |
176 | * memory attributes (shared, type, and cache attribs). We can not | |
177 | * change these attributes once the initial assembly has setup the | |
178 | * page tables. | |
179 | */ | |
ca8f0b0a RK |
180 | if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) { |
181 | pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n", | |
182 | cache_policies[cachepolicy].policy); | |
183 | return 0; | |
184 | } | |
185 | ||
186 | if (selected != cachepolicy) { | |
187 | unsigned long cr = __clear_cr(cache_policies[selected].cr_mask); | |
188 | cachepolicy = selected; | |
189 | flush_cache_all(); | |
190 | set_cr(cr); | |
11179d8c | 191 | } |
2b0d8c25 | 192 | return 0; |
ae8f1541 | 193 | } |
2b0d8c25 | 194 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 195 | |
2b0d8c25 | 196 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
197 | { |
198 | char *p = "buffered"; | |
4ed89f22 | 199 | pr_warn("nocache is deprecated; use cachepolicy=%s\n", p); |
2b0d8c25 JK |
200 | early_cachepolicy(p); |
201 | return 0; | |
ae8f1541 | 202 | } |
2b0d8c25 | 203 | early_param("nocache", early_nocache); |
ae8f1541 | 204 | |
2b0d8c25 | 205 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
206 | { |
207 | char *p = "uncached"; | |
4ed89f22 | 208 | pr_warn("nowb is deprecated; use cachepolicy=%s\n", p); |
2b0d8c25 JK |
209 | early_cachepolicy(p); |
210 | return 0; | |
ae8f1541 | 211 | } |
2b0d8c25 | 212 | early_param("nowb", early_nowrite); |
ae8f1541 | 213 | |
1b6ba46b | 214 | #ifndef CONFIG_ARM_LPAE |
2b0d8c25 | 215 | static int __init early_ecc(char *p) |
ae8f1541 | 216 | { |
2b0d8c25 | 217 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 218 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 219 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 220 | ecc_mask = 0; |
2b0d8c25 | 221 | return 0; |
ae8f1541 | 222 | } |
2b0d8c25 | 223 | early_param("ecc", early_ecc); |
1b6ba46b | 224 | #endif |
ae8f1541 | 225 | |
b849a60e UKK |
226 | #else /* ifdef CONFIG_CPU_CP15 */ |
227 | ||
228 | static int __init early_cachepolicy(char *p) | |
229 | { | |
8b521cb2 | 230 | pr_warn("cachepolicy kernel parameter not supported without cp15\n"); |
b849a60e UKK |
231 | } |
232 | early_param("cachepolicy", early_cachepolicy); | |
233 | ||
234 | static int __init noalign_setup(char *__unused) | |
235 | { | |
8b521cb2 | 236 | pr_warn("noalign kernel parameter not supported without cp15\n"); |
b849a60e UKK |
237 | } |
238 | __setup("noalign", noalign_setup); | |
239 | ||
240 | #endif /* ifdef CONFIG_CPU_CP15 / else */ | |
241 | ||
36bb94ba | 242 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
4d9c5b89 | 243 | #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE |
b1cce6b1 | 244 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 245 | |
b29e9f5e | 246 | static struct mem_type mem_types[] = { |
0af92bef | 247 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
248 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
249 | L_PTE_SHARED, | |
4d9c5b89 CD |
250 | .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) | |
251 | s2_policy(L_PTE_S2_MT_DEV_SHARED) | | |
252 | L_PTE_SHARED, | |
0af92bef | 253 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 254 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
255 | .domain = DOMAIN_IO, |
256 | }, | |
257 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 258 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 259 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 260 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
261 | .domain = DOMAIN_IO, |
262 | }, | |
263 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 264 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
265 | .prot_l1 = PMD_TYPE_TABLE, |
266 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
267 | .domain = DOMAIN_IO, | |
c2794437 | 268 | }, |
1ad77a87 | 269 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 270 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 271 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 272 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 273 | .domain = DOMAIN_IO, |
ae8f1541 | 274 | }, |
ebb4c658 RK |
275 | [MT_UNCACHED] = { |
276 | .prot_pte = PROT_PTE_DEVICE, | |
277 | .prot_l1 = PMD_TYPE_TABLE, | |
278 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
279 | .domain = DOMAIN_IO, | |
280 | }, | |
ae8f1541 | 281 | [MT_CACHECLEAN] = { |
9ef79635 | 282 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
283 | .domain = DOMAIN_KERNEL, |
284 | }, | |
1b6ba46b | 285 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 | 286 | [MT_MINICLEAN] = { |
9ef79635 | 287 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
288 | .domain = DOMAIN_KERNEL, |
289 | }, | |
1b6ba46b | 290 | #endif |
ae8f1541 RK |
291 | [MT_LOW_VECTORS] = { |
292 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 293 | L_PTE_RDONLY, |
ae8f1541 | 294 | .prot_l1 = PMD_TYPE_TABLE, |
a02d8dfd | 295 | .domain = DOMAIN_VECTORS, |
ae8f1541 RK |
296 | }, |
297 | [MT_HIGH_VECTORS] = { | |
298 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 299 | L_PTE_USER | L_PTE_RDONLY, |
ae8f1541 | 300 | .prot_l1 = PMD_TYPE_TABLE, |
a02d8dfd | 301 | .domain = DOMAIN_VECTORS, |
ae8f1541 | 302 | }, |
2e2c9de2 | 303 | [MT_MEMORY_RWX] = { |
36bb94ba | 304 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
f1a2481c | 305 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 306 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
307 | .domain = DOMAIN_KERNEL, |
308 | }, | |
ebd4922e RK |
309 | [MT_MEMORY_RW] = { |
310 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
311 | L_PTE_XN, | |
312 | .prot_l1 = PMD_TYPE_TABLE, | |
313 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, | |
314 | .domain = DOMAIN_KERNEL, | |
315 | }, | |
ae8f1541 | 316 | [MT_ROM] = { |
9ef79635 | 317 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
318 | .domain = DOMAIN_KERNEL, |
319 | }, | |
2e2c9de2 | 320 | [MT_MEMORY_RWX_NONCACHED] = { |
f1a2481c | 321 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 322 | L_PTE_MT_BUFFERABLE, |
f1a2481c | 323 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
324 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
325 | .domain = DOMAIN_KERNEL, | |
326 | }, | |
2e2c9de2 | 327 | [MT_MEMORY_RW_DTCM] = { |
f444fce3 | 328 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 329 | L_PTE_XN, |
f444fce3 LW |
330 | .prot_l1 = PMD_TYPE_TABLE, |
331 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
332 | .domain = DOMAIN_KERNEL, | |
cb9d7707 | 333 | }, |
2e2c9de2 | 334 | [MT_MEMORY_RWX_ITCM] = { |
36bb94ba | 335 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
cb9d7707 | 336 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 337 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 338 | }, |
2e2c9de2 | 339 | [MT_MEMORY_RW_SO] = { |
8fb54284 | 340 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
93d5bf07 | 341 | L_PTE_MT_UNCACHED | L_PTE_XN, |
8fb54284 SS |
342 | .prot_l1 = PMD_TYPE_TABLE, |
343 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | | |
344 | PMD_SECT_UNCACHED | PMD_SECT_XN, | |
345 | .domain = DOMAIN_KERNEL, | |
346 | }, | |
c7909509 | 347 | [MT_MEMORY_DMA_READY] = { |
71b55663 RK |
348 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
349 | L_PTE_XN, | |
c7909509 MS |
350 | .prot_l1 = PMD_TYPE_TABLE, |
351 | .domain = DOMAIN_KERNEL, | |
352 | }, | |
ae8f1541 RK |
353 | }; |
354 | ||
b29e9f5e RK |
355 | const struct mem_type *get_mem_type(unsigned int type) |
356 | { | |
357 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
358 | } | |
69d3a84a | 359 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 360 | |
a5f4c561 SA |
361 | static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr); |
362 | ||
363 | static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS] | |
364 | __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata; | |
365 | ||
366 | static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr) | |
367 | { | |
368 | return &bm_pte[pte_index(addr)]; | |
369 | } | |
370 | ||
371 | static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr) | |
372 | { | |
373 | return pte_offset_kernel(dir, addr); | |
374 | } | |
375 | ||
376 | static inline pmd_t * __init fixmap_pmd(unsigned long addr) | |
377 | { | |
378 | pgd_t *pgd = pgd_offset_k(addr); | |
379 | pud_t *pud = pud_offset(pgd, addr); | |
380 | pmd_t *pmd = pmd_offset(pud, addr); | |
381 | ||
382 | return pmd; | |
383 | } | |
384 | ||
385 | void __init early_fixmap_init(void) | |
386 | { | |
387 | pmd_t *pmd; | |
388 | ||
389 | /* | |
390 | * The early fixmap range spans multiple pmds, for which | |
391 | * we are not prepared: | |
392 | */ | |
393 | BUILD_BUG_ON((__fix_to_virt(__end_of_permanent_fixed_addresses) >> PMD_SHIFT) | |
394 | != FIXADDR_TOP >> PMD_SHIFT); | |
395 | ||
396 | pmd = fixmap_pmd(FIXADDR_TOP); | |
397 | pmd_populate_kernel(&init_mm, pmd, bm_pte); | |
398 | ||
399 | pte_offset_fixmap = pte_offset_early_fixmap; | |
400 | } | |
401 | ||
99b4ac9a KC |
402 | /* |
403 | * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range(). | |
404 | * As a result, this can only be called with preemption disabled, as under | |
405 | * stop_machine(). | |
406 | */ | |
407 | void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) | |
408 | { | |
409 | unsigned long vaddr = __fix_to_virt(idx); | |
a5f4c561 | 410 | pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr); |
99b4ac9a KC |
411 | |
412 | /* Make sure fixmap region does not exceed available allocation. */ | |
413 | BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) > | |
414 | FIXADDR_END); | |
415 | BUG_ON(idx >= __end_of_fixed_addresses); | |
416 | ||
417 | if (pgprot_val(prot)) | |
418 | set_pte_at(NULL, vaddr, pte, | |
419 | pfn_pte(phys >> PAGE_SHIFT, prot)); | |
420 | else | |
421 | pte_clear(NULL, vaddr, pte); | |
422 | local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE); | |
423 | } | |
424 | ||
ae8f1541 RK |
425 | /* |
426 | * Adjust the PMD section entries according to the CPU in use. | |
427 | */ | |
428 | static void __init build_mem_type_table(void) | |
429 | { | |
430 | struct cachepolicy *cp; | |
431 | unsigned int cr = get_cr(); | |
442e70c0 | 432 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
cc577c26 | 433 | pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot; |
ae8f1541 RK |
434 | int cpu_arch = cpu_architecture(); |
435 | int i; | |
436 | ||
11179d8c | 437 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 438 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
439 | if (cachepolicy > CPOLICY_BUFFERED) |
440 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 441 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
442 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
443 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 444 | #endif |
11179d8c | 445 | } |
ae8f1541 RK |
446 | if (cpu_arch < CPU_ARCH_ARMv5) { |
447 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
448 | cachepolicy = CPOLICY_WRITEBACK; | |
449 | ecc_mask = 0; | |
450 | } | |
ca8f0b0a | 451 | |
20e7e364 RK |
452 | if (is_smp()) { |
453 | if (cachepolicy != CPOLICY_WRITEALLOC) { | |
454 | pr_warn("Forcing write-allocate cache policy for SMP\n"); | |
455 | cachepolicy = CPOLICY_WRITEALLOC; | |
456 | } | |
457 | if (!(initial_pmd_value & PMD_SECT_S)) { | |
458 | pr_warn("Forcing shared mappings for SMP\n"); | |
459 | initial_pmd_value |= PMD_SECT_S; | |
460 | } | |
ca8f0b0a | 461 | } |
ae8f1541 | 462 | |
1ad77a87 | 463 | /* |
b1cce6b1 RK |
464 | * Strip out features not present on earlier architectures. |
465 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
466 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 467 | */ |
b1cce6b1 RK |
468 | if (cpu_arch < CPU_ARCH_ARMv5) |
469 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
470 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
471 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
472 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
473 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
474 | |
475 | /* | |
b1cce6b1 RK |
476 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
477 | * "update-able on write" bit on ARM610). However, Xscale and | |
478 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 479 | */ |
b1cce6b1 | 480 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
9ef79635 | 481 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 482 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
483 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
484 | } | |
485 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
486 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
487 | if (mem_types[i].prot_l1) |
488 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
489 | if (mem_types[i].prot_sect) |
490 | mem_types[i].prot_sect |= PMD_BIT4; | |
491 | } | |
492 | } | |
ae8f1541 | 493 | |
b1cce6b1 RK |
494 | /* |
495 | * Mark the device areas according to the CPU/architecture. | |
496 | */ | |
497 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
498 | if (!cpu_is_xsc3()) { | |
499 | /* | |
500 | * Mark device regions on ARMv6+ as execute-never | |
501 | * to prevent speculative instruction fetches. | |
502 | */ | |
503 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
504 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
505 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
506 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
ebd4922e RK |
507 | |
508 | /* Also setup NX memory mapping */ | |
509 | mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN; | |
b1cce6b1 RK |
510 | } |
511 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
512 | /* | |
513 | * For ARMv7 with TEX remapping, | |
514 | * - shared device is SXCB=1100 | |
515 | * - nonshared device is SXCB=0100 | |
516 | * - write combine device mem is SXCB=0001 | |
517 | * (Uncached Normal memory) | |
518 | */ | |
519 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
520 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
521 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
522 | } else if (cpu_is_xsc3()) { | |
523 | /* | |
524 | * For Xscale3, | |
525 | * - shared device is TEXCB=00101 | |
526 | * - nonshared device is TEXCB=01000 | |
527 | * - write combine device mem is TEXCB=00100 | |
528 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
529 | */ | |
530 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
531 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
532 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
533 | } else { | |
534 | /* | |
535 | * For ARMv6 and ARMv7 without TEX remapping, | |
536 | * - shared device is TEXCB=00001 | |
537 | * - nonshared device is TEXCB=01000 | |
538 | * - write combine device mem is TEXCB=00100 | |
539 | * (Uncached Normal in ARMv6 parlance). | |
540 | */ | |
541 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
542 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
543 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
544 | } | |
545 | } else { | |
546 | /* | |
547 | * On others, write combining is "Uncached/Buffered" | |
548 | */ | |
549 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
550 | } | |
551 | ||
552 | /* | |
553 | * Now deal with the memory-type mappings | |
554 | */ | |
ae8f1541 | 555 | cp = &cache_policies[cachepolicy]; |
bb30f36f | 556 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
cc577c26 | 557 | s2_pgprot = cp->pte_s2; |
4d9c5b89 CD |
558 | hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte; |
559 | s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2; | |
bb30f36f | 560 | |
1d4d3715 | 561 | #ifndef CONFIG_ARM_LPAE |
b6ccb980 WD |
562 | /* |
563 | * We don't use domains on ARMv6 (since this causes problems with | |
564 | * v6/v7 kernels), so we must use a separate memory type for user | |
565 | * r/o, kernel r/w to map the vectors page. | |
566 | */ | |
b6ccb980 WD |
567 | if (cpu_arch == CPU_ARCH_ARMv6) |
568 | vecs_pgprot |= L_PTE_MT_VECTORS; | |
1d4d3715 JL |
569 | |
570 | /* | |
571 | * Check is it with support for the PXN bit | |
572 | * in the Short-descriptor translation table format descriptors. | |
573 | */ | |
574 | if (cpu_arch == CPU_ARCH_ARMv7 && | |
575 | (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) == 4) { | |
576 | user_pmd_table |= PMD_PXNTABLE; | |
577 | } | |
b6ccb980 | 578 | #endif |
bb30f36f | 579 | |
ae8f1541 RK |
580 | /* |
581 | * ARMv6 and above have extended page tables. | |
582 | */ | |
583 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
1b6ba46b | 584 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
585 | /* |
586 | * Mark cache clean areas and XIP ROM read only | |
587 | * from SVC mode and no access from userspace. | |
588 | */ | |
589 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
590 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
591 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
1b6ba46b | 592 | #endif |
ae8f1541 | 593 | |
20e7e364 RK |
594 | /* |
595 | * If the initial page tables were created with the S bit | |
596 | * set, then we need to do the same here for the same | |
597 | * reasons given in early_cachepolicy(). | |
598 | */ | |
599 | if (initial_pmd_value & PMD_SECT_S) { | |
f00ec48f RK |
600 | user_pgprot |= L_PTE_SHARED; |
601 | kern_pgprot |= L_PTE_SHARED; | |
602 | vecs_pgprot |= L_PTE_SHARED; | |
cc577c26 | 603 | s2_pgprot |= L_PTE_SHARED; |
f00ec48f RK |
604 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; |
605 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
606 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
607 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
2e2c9de2 RK |
608 | mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S; |
609 | mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED; | |
ebd4922e RK |
610 | mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S; |
611 | mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED; | |
c7909509 | 612 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
2e2c9de2 RK |
613 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S; |
614 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED; | |
f00ec48f | 615 | } |
ae8f1541 RK |
616 | } |
617 | ||
e4707dd3 PW |
618 | /* |
619 | * Non-cacheable Normal - intended for memory areas that must | |
620 | * not cause dirty cache line writebacks when used | |
621 | */ | |
622 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
623 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
624 | /* Non-cacheable Normal is XCB = 001 */ | |
2e2c9de2 | 625 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= |
e4707dd3 PW |
626 | PMD_SECT_BUFFERED; |
627 | } else { | |
628 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
2e2c9de2 | 629 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= |
e4707dd3 PW |
630 | PMD_SECT_TEX(1); |
631 | } | |
632 | } else { | |
2e2c9de2 | 633 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; |
e4707dd3 PW |
634 | } |
635 | ||
1b6ba46b CM |
636 | #ifdef CONFIG_ARM_LPAE |
637 | /* | |
638 | * Do not generate access flag faults for the kernel mappings. | |
639 | */ | |
640 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
641 | mem_types[i].prot_pte |= PTE_EXT_AF; | |
1a3abcf4 VA |
642 | if (mem_types[i].prot_sect) |
643 | mem_types[i].prot_sect |= PMD_SECT_AF; | |
1b6ba46b CM |
644 | } |
645 | kern_pgprot |= PTE_EXT_AF; | |
646 | vecs_pgprot |= PTE_EXT_AF; | |
1d4d3715 JL |
647 | |
648 | /* | |
649 | * Set PXN for user mappings | |
650 | */ | |
651 | user_pgprot |= PTE_EXT_PXN; | |
1b6ba46b CM |
652 | #endif |
653 | ||
ae8f1541 | 654 | for (i = 0; i < 16; i++) { |
864aa04c | 655 | pteval_t v = pgprot_val(protection_map[i]); |
bb30f36f | 656 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
657 | } |
658 | ||
bb30f36f RK |
659 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
660 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 661 | |
44b18693 | 662 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 663 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
36bb94ba | 664 | L_PTE_DIRTY | kern_pgprot); |
cc577c26 CD |
665 | pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot); |
666 | pgprot_s2_device = __pgprot(s2_device_pgprot); | |
667 | pgprot_hyp_device = __pgprot(hyp_device_pgprot); | |
ae8f1541 RK |
668 | |
669 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
670 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
2e2c9de2 RK |
671 | mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd; |
672 | mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; | |
ebd4922e RK |
673 | mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; |
674 | mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; | |
c7909509 | 675 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; |
2e2c9de2 | 676 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; |
ae8f1541 RK |
677 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
678 | ||
679 | switch (cp->pmd) { | |
680 | case PMD_SECT_WT: | |
681 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
682 | break; | |
683 | case PMD_SECT_WB: | |
684 | case PMD_SECT_WBWA: | |
685 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
686 | break; | |
687 | } | |
905b5797 MS |
688 | pr_info("Memory policy: %sData cache %s\n", |
689 | ecc_mask ? "ECC enabled, " : "", cp->policy); | |
2497f0a8 RK |
690 | |
691 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
692 | struct mem_type *t = &mem_types[i]; | |
693 | if (t->prot_l1) | |
694 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
695 | if (t->prot_sect) | |
696 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
697 | } | |
ae8f1541 RK |
698 | } |
699 | ||
d907387c CM |
700 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
701 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
702 | unsigned long size, pgprot_t vma_prot) | |
703 | { | |
704 | if (!pfn_valid(pfn)) | |
705 | return pgprot_noncached(vma_prot); | |
706 | else if (file->f_flags & O_SYNC) | |
707 | return pgprot_writecombine(vma_prot); | |
708 | return vma_prot; | |
709 | } | |
710 | EXPORT_SYMBOL(phys_mem_access_prot); | |
711 | #endif | |
712 | ||
ae8f1541 RK |
713 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
714 | ||
0536bdf3 | 715 | static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) |
3abe9d33 | 716 | { |
0536bdf3 | 717 | void *ptr = __va(memblock_alloc(sz, align)); |
2778f620 RK |
718 | memset(ptr, 0, sz); |
719 | return ptr; | |
3abe9d33 RK |
720 | } |
721 | ||
0536bdf3 NP |
722 | static void __init *early_alloc(unsigned long sz) |
723 | { | |
724 | return early_alloc_aligned(sz, sz); | |
725 | } | |
726 | ||
4bb2e27d | 727 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) |
ae8f1541 | 728 | { |
24e6c699 | 729 | if (pmd_none(*pmd)) { |
410f1483 | 730 | pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
97092e0c | 731 | __pmd_populate(pmd, __pa(pte), prot); |
24e6c699 | 732 | } |
4bb2e27d RK |
733 | BUG_ON(pmd_bad(*pmd)); |
734 | return pte_offset_kernel(pmd, addr); | |
735 | } | |
ae8f1541 | 736 | |
4bb2e27d RK |
737 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
738 | unsigned long end, unsigned long pfn, | |
739 | const struct mem_type *type) | |
740 | { | |
741 | pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); | |
24e6c699 | 742 | do { |
40d192b6 | 743 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
24e6c699 RK |
744 | pfn++; |
745 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
746 | } |
747 | ||
37468b30 | 748 | static void __init __map_init_section(pmd_t *pmd, unsigned long addr, |
e651eab0 S |
749 | unsigned long end, phys_addr_t phys, |
750 | const struct mem_type *type) | |
ae8f1541 | 751 | { |
37468b30 PYC |
752 | pmd_t *p = pmd; |
753 | ||
e651eab0 | 754 | #ifndef CONFIG_ARM_LPAE |
24e6c699 | 755 | /* |
e651eab0 S |
756 | * In classic MMU format, puds and pmds are folded in to |
757 | * the pgds. pmd_offset gives the PGD entry. PGDs refer to a | |
758 | * group of L1 entries making up one logical pointer to | |
759 | * an L2 table (2MB), where as PMDs refer to the individual | |
760 | * L1 entries (1MB). Hence increment to get the correct | |
761 | * offset for odd 1MB sections. | |
762 | * (See arch/arm/include/asm/pgtable-2level.h) | |
24e6c699 | 763 | */ |
e651eab0 S |
764 | if (addr & SECTION_SIZE) |
765 | pmd++; | |
1b6ba46b | 766 | #endif |
e651eab0 S |
767 | do { |
768 | *pmd = __pmd(phys | type->prot_sect); | |
769 | phys += SECTION_SIZE; | |
770 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
24e6c699 | 771 | |
37468b30 | 772 | flush_pmd_entry(p); |
e651eab0 | 773 | } |
ae8f1541 | 774 | |
e651eab0 S |
775 | static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, |
776 | unsigned long end, phys_addr_t phys, | |
777 | const struct mem_type *type) | |
778 | { | |
779 | pmd_t *pmd = pmd_offset(pud, addr); | |
780 | unsigned long next; | |
781 | ||
782 | do { | |
24e6c699 | 783 | /* |
e651eab0 S |
784 | * With LPAE, we must loop over to map |
785 | * all the pmds for the given range. | |
24e6c699 | 786 | */ |
e651eab0 S |
787 | next = pmd_addr_end(addr, end); |
788 | ||
789 | /* | |
790 | * Try a section mapping - addr, next and phys must all be | |
791 | * aligned to a section boundary. | |
792 | */ | |
793 | if (type->prot_sect && | |
794 | ((addr | next | phys) & ~SECTION_MASK) == 0) { | |
37468b30 | 795 | __map_init_section(pmd, addr, next, phys, type); |
e651eab0 S |
796 | } else { |
797 | alloc_init_pte(pmd, addr, next, | |
798 | __phys_to_pfn(phys), type); | |
799 | } | |
800 | ||
801 | phys += next - addr; | |
802 | ||
803 | } while (pmd++, addr = next, addr != end); | |
ae8f1541 RK |
804 | } |
805 | ||
14904927 | 806 | static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, |
20d6956d VA |
807 | unsigned long end, phys_addr_t phys, |
808 | const struct mem_type *type) | |
516295e5 RK |
809 | { |
810 | pud_t *pud = pud_offset(pgd, addr); | |
811 | unsigned long next; | |
812 | ||
813 | do { | |
814 | next = pud_addr_end(addr, end); | |
e651eab0 | 815 | alloc_init_pmd(pud, addr, next, phys, type); |
516295e5 RK |
816 | phys += next - addr; |
817 | } while (pud++, addr = next, addr != end); | |
818 | } | |
819 | ||
1b6ba46b | 820 | #ifndef CONFIG_ARM_LPAE |
4a56c1e4 RK |
821 | static void __init create_36bit_mapping(struct map_desc *md, |
822 | const struct mem_type *type) | |
823 | { | |
97092e0c RK |
824 | unsigned long addr, length, end; |
825 | phys_addr_t phys; | |
4a56c1e4 RK |
826 | pgd_t *pgd; |
827 | ||
828 | addr = md->virtual; | |
cae6292b | 829 | phys = __pfn_to_phys(md->pfn); |
4a56c1e4 RK |
830 | length = PAGE_ALIGN(md->length); |
831 | ||
832 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
4ed89f22 | 833 | pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n", |
29a38193 | 834 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
835 | return; |
836 | } | |
837 | ||
838 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
839 | * Since domain assignments can in fact be arbitrary, the | |
840 | * 'domain == 0' check below is required to insure that ARMv6 | |
841 | * supersections are only allocated for domain 0 regardless | |
842 | * of the actual domain assignments in use. | |
843 | */ | |
844 | if (type->domain) { | |
4ed89f22 | 845 | pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n", |
29a38193 | 846 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
847 | return; |
848 | } | |
849 | ||
850 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
4ed89f22 | 851 | pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n", |
29a38193 | 852 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
853 | return; |
854 | } | |
855 | ||
856 | /* | |
857 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
858 | * (See ARMv6 spec). | |
859 | */ | |
860 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
861 | ||
862 | pgd = pgd_offset_k(addr); | |
863 | end = addr + length; | |
864 | do { | |
516295e5 RK |
865 | pud_t *pud = pud_offset(pgd, addr); |
866 | pmd_t *pmd = pmd_offset(pud, addr); | |
4a56c1e4 RK |
867 | int i; |
868 | ||
869 | for (i = 0; i < 16; i++) | |
870 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
871 | ||
872 | addr += SUPERSECTION_SIZE; | |
873 | phys += SUPERSECTION_SIZE; | |
874 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
875 | } while (addr != end); | |
876 | } | |
1b6ba46b | 877 | #endif /* !CONFIG_ARM_LPAE */ |
4a56c1e4 | 878 | |
ae8f1541 RK |
879 | /* |
880 | * Create the page directory entries and any necessary | |
881 | * page tables for the mapping specified by `md'. We | |
882 | * are able to cope here with varying sizes and address | |
883 | * offsets, and we take full advantage of sections and | |
884 | * supersections. | |
885 | */ | |
a2227120 | 886 | static void __init create_mapping(struct map_desc *md) |
ae8f1541 | 887 | { |
cae6292b WD |
888 | unsigned long addr, length, end; |
889 | phys_addr_t phys; | |
d5c98176 | 890 | const struct mem_type *type; |
24e6c699 | 891 | pgd_t *pgd; |
ae8f1541 RK |
892 | |
893 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
4ed89f22 RK |
894 | pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n", |
895 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
ae8f1541 RK |
896 | return; |
897 | } | |
898 | ||
899 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
a5f4c561 | 900 | md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START && |
0536bdf3 | 901 | (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { |
4ed89f22 RK |
902 | pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n", |
903 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
ae8f1541 RK |
904 | } |
905 | ||
d5c98176 | 906 | type = &mem_types[md->type]; |
ae8f1541 | 907 | |
1b6ba46b | 908 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
909 | /* |
910 | * Catch 36-bit addresses | |
911 | */ | |
4a56c1e4 RK |
912 | if (md->pfn >= 0x100000) { |
913 | create_36bit_mapping(md, type); | |
914 | return; | |
ae8f1541 | 915 | } |
1b6ba46b | 916 | #endif |
ae8f1541 | 917 | |
7b9c7b4d | 918 | addr = md->virtual & PAGE_MASK; |
cae6292b | 919 | phys = __pfn_to_phys(md->pfn); |
7b9c7b4d | 920 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 921 | |
24e6c699 | 922 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
4ed89f22 RK |
923 | pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n", |
924 | (long long)__pfn_to_phys(md->pfn), addr); | |
ae8f1541 RK |
925 | return; |
926 | } | |
927 | ||
24e6c699 RK |
928 | pgd = pgd_offset_k(addr); |
929 | end = addr + length; | |
930 | do { | |
931 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 932 | |
516295e5 | 933 | alloc_init_pud(pgd, addr, next, phys, type); |
ae8f1541 | 934 | |
24e6c699 RK |
935 | phys += next - addr; |
936 | addr = next; | |
937 | } while (pgd++, addr != end); | |
ae8f1541 RK |
938 | } |
939 | ||
940 | /* | |
941 | * Create the architecture specific mappings | |
942 | */ | |
943 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
944 | { | |
0536bdf3 NP |
945 | struct map_desc *md; |
946 | struct vm_struct *vm; | |
101eeda3 | 947 | struct static_vm *svm; |
0536bdf3 NP |
948 | |
949 | if (!nr) | |
950 | return; | |
ae8f1541 | 951 | |
101eeda3 | 952 | svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm)); |
0536bdf3 NP |
953 | |
954 | for (md = io_desc; nr; md++, nr--) { | |
955 | create_mapping(md); | |
101eeda3 JK |
956 | |
957 | vm = &svm->vm; | |
0536bdf3 NP |
958 | vm->addr = (void *)(md->virtual & PAGE_MASK); |
959 | vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); | |
c2794437 RH |
960 | vm->phys_addr = __pfn_to_phys(md->pfn); |
961 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; | |
576d2f25 | 962 | vm->flags |= VM_ARM_MTYPE(md->type); |
0536bdf3 | 963 | vm->caller = iotable_init; |
101eeda3 | 964 | add_static_vm_early(svm++); |
0536bdf3 | 965 | } |
ae8f1541 RK |
966 | } |
967 | ||
c2794437 RH |
968 | void __init vm_reserve_area_early(unsigned long addr, unsigned long size, |
969 | void *caller) | |
970 | { | |
971 | struct vm_struct *vm; | |
101eeda3 JK |
972 | struct static_vm *svm; |
973 | ||
974 | svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm)); | |
c2794437 | 975 | |
101eeda3 | 976 | vm = &svm->vm; |
c2794437 RH |
977 | vm->addr = (void *)addr; |
978 | vm->size = size; | |
863e99a8 | 979 | vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; |
c2794437 | 980 | vm->caller = caller; |
101eeda3 | 981 | add_static_vm_early(svm); |
c2794437 RH |
982 | } |
983 | ||
19b52abe NP |
984 | #ifndef CONFIG_ARM_LPAE |
985 | ||
986 | /* | |
987 | * The Linux PMD is made of two consecutive section entries covering 2MB | |
988 | * (see definition in include/asm/pgtable-2level.h). However a call to | |
989 | * create_mapping() may optimize static mappings by using individual | |
990 | * 1MB section mappings. This leaves the actual PMD potentially half | |
991 | * initialized if the top or bottom section entry isn't used, leaving it | |
992 | * open to problems if a subsequent ioremap() or vmalloc() tries to use | |
993 | * the virtual space left free by that unused section entry. | |
994 | * | |
995 | * Let's avoid the issue by inserting dummy vm entries covering the unused | |
996 | * PMD halves once the static mappings are in place. | |
997 | */ | |
998 | ||
999 | static void __init pmd_empty_section_gap(unsigned long addr) | |
1000 | { | |
c2794437 | 1001 | vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); |
19b52abe NP |
1002 | } |
1003 | ||
1004 | static void __init fill_pmd_gaps(void) | |
1005 | { | |
101eeda3 | 1006 | struct static_vm *svm; |
19b52abe NP |
1007 | struct vm_struct *vm; |
1008 | unsigned long addr, next = 0; | |
1009 | pmd_t *pmd; | |
1010 | ||
101eeda3 JK |
1011 | list_for_each_entry(svm, &static_vmlist, list) { |
1012 | vm = &svm->vm; | |
19b52abe NP |
1013 | addr = (unsigned long)vm->addr; |
1014 | if (addr < next) | |
1015 | continue; | |
1016 | ||
1017 | /* | |
1018 | * Check if this vm starts on an odd section boundary. | |
1019 | * If so and the first section entry for this PMD is free | |
1020 | * then we block the corresponding virtual address. | |
1021 | */ | |
1022 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
1023 | pmd = pmd_off_k(addr); | |
1024 | if (pmd_none(*pmd)) | |
1025 | pmd_empty_section_gap(addr & PMD_MASK); | |
1026 | } | |
1027 | ||
1028 | /* | |
1029 | * Then check if this vm ends on an odd section boundary. | |
1030 | * If so and the second section entry for this PMD is empty | |
1031 | * then we block the corresponding virtual address. | |
1032 | */ | |
1033 | addr += vm->size; | |
1034 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
1035 | pmd = pmd_off_k(addr) + 1; | |
1036 | if (pmd_none(*pmd)) | |
1037 | pmd_empty_section_gap(addr); | |
1038 | } | |
1039 | ||
1040 | /* no need to look at any vm entry until we hit the next PMD */ | |
1041 | next = (addr + PMD_SIZE - 1) & PMD_MASK; | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | #else | |
1046 | #define fill_pmd_gaps() do { } while (0) | |
1047 | #endif | |
1048 | ||
c2794437 RH |
1049 | #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) |
1050 | static void __init pci_reserve_io(void) | |
1051 | { | |
101eeda3 | 1052 | struct static_vm *svm; |
c2794437 | 1053 | |
101eeda3 JK |
1054 | svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); |
1055 | if (svm) | |
1056 | return; | |
c2794437 | 1057 | |
c2794437 RH |
1058 | vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); |
1059 | } | |
1060 | #else | |
1061 | #define pci_reserve_io() do { } while (0) | |
1062 | #endif | |
1063 | ||
e5c5f2ad RH |
1064 | #ifdef CONFIG_DEBUG_LL |
1065 | void __init debug_ll_io_init(void) | |
1066 | { | |
1067 | struct map_desc map; | |
1068 | ||
1069 | debug_ll_addr(&map.pfn, &map.virtual); | |
1070 | if (!map.pfn || !map.virtual) | |
1071 | return; | |
1072 | map.pfn = __phys_to_pfn(map.pfn); | |
1073 | map.virtual &= PAGE_MASK; | |
1074 | map.length = PAGE_SIZE; | |
1075 | map.type = MT_DEVICE; | |
ee4de5d9 | 1076 | iotable_init(&map, 1); |
e5c5f2ad RH |
1077 | } |
1078 | #endif | |
1079 | ||
0536bdf3 NP |
1080 | static void * __initdata vmalloc_min = |
1081 | (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); | |
6c5da7ac RK |
1082 | |
1083 | /* | |
1084 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
1085 | * bytes. This can be used to increase (or decrease) the vmalloc | |
0536bdf3 | 1086 | * area - the default is 240m. |
6c5da7ac | 1087 | */ |
2b0d8c25 | 1088 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 1089 | { |
79612395 | 1090 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
1091 | |
1092 | if (vmalloc_reserve < SZ_16M) { | |
1093 | vmalloc_reserve = SZ_16M; | |
4ed89f22 | 1094 | pr_warn("vmalloc area too small, limiting to %luMB\n", |
6c5da7ac RK |
1095 | vmalloc_reserve >> 20); |
1096 | } | |
9210807c NP |
1097 | |
1098 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
1099 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
4ed89f22 | 1100 | pr_warn("vmalloc area is too big, limiting to %luMB\n", |
9210807c NP |
1101 | vmalloc_reserve >> 20); |
1102 | } | |
79612395 RK |
1103 | |
1104 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); | |
2b0d8c25 | 1105 | return 0; |
6c5da7ac | 1106 | } |
2b0d8c25 | 1107 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 1108 | |
c7909509 | 1109 | phys_addr_t arm_lowmem_limit __initdata = 0; |
8df65168 | 1110 | |
0371d3f7 | 1111 | void __init sanity_check_meminfo(void) |
60296c71 | 1112 | { |
c65b7e98 | 1113 | phys_addr_t memblock_limit = 0; |
1c2f87c2 | 1114 | int highmem = 0; |
82f66704 | 1115 | phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1; |
1c2f87c2 | 1116 | struct memblock_region *reg; |
eeb3fee8 | 1117 | bool should_use_highmem = false; |
60296c71 | 1118 | |
1c2f87c2 LA |
1119 | for_each_memblock(memory, reg) { |
1120 | phys_addr_t block_start = reg->base; | |
1121 | phys_addr_t block_end = reg->base + reg->size; | |
1122 | phys_addr_t size_limit = reg->size; | |
77f73a2c | 1123 | |
1c2f87c2 | 1124 | if (reg->base >= vmalloc_limit) |
dde5828f | 1125 | highmem = 1; |
28d4bf7a | 1126 | else |
1c2f87c2 | 1127 | size_limit = vmalloc_limit - reg->base; |
dde5828f | 1128 | |
dde5828f | 1129 | |
1c2f87c2 LA |
1130 | if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) { |
1131 | ||
1132 | if (highmem) { | |
1133 | pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n", | |
4ed89f22 | 1134 | &block_start, &block_end); |
1c2f87c2 | 1135 | memblock_remove(reg->base, reg->size); |
eeb3fee8 | 1136 | should_use_highmem = true; |
1c2f87c2 | 1137 | continue; |
a1bbaec0 | 1138 | } |
77f73a2c | 1139 | |
1c2f87c2 LA |
1140 | if (reg->size > size_limit) { |
1141 | phys_addr_t overlap_size = reg->size - size_limit; | |
1142 | ||
1143 | pr_notice("Truncating RAM at %pa-%pa to -%pa", | |
4ed89f22 | 1144 | &block_start, &block_end, &vmalloc_limit); |
1c2f87c2 LA |
1145 | memblock_remove(vmalloc_limit, overlap_size); |
1146 | block_end = vmalloc_limit; | |
eeb3fee8 | 1147 | should_use_highmem = true; |
1c2f87c2 | 1148 | } |
a1bbaec0 | 1149 | } |
40f7bfe4 | 1150 | |
1c2f87c2 LA |
1151 | if (!highmem) { |
1152 | if (block_end > arm_lowmem_limit) { | |
1153 | if (reg->size > size_limit) | |
1154 | arm_lowmem_limit = vmalloc_limit; | |
1155 | else | |
1156 | arm_lowmem_limit = block_end; | |
1157 | } | |
c65b7e98 RK |
1158 | |
1159 | /* | |
965278dc | 1160 | * Find the first non-pmd-aligned page, and point |
c65b7e98 | 1161 | * memblock_limit at it. This relies on rounding the |
965278dc MR |
1162 | * limit down to be pmd-aligned, which happens at the |
1163 | * end of this function. | |
c65b7e98 RK |
1164 | * |
1165 | * With this algorithm, the start or end of almost any | |
965278dc MR |
1166 | * bank can be non-pmd-aligned. The only exception is |
1167 | * that the start of the bank 0 must be section- | |
c65b7e98 RK |
1168 | * aligned, since otherwise memory would need to be |
1169 | * allocated when mapping the start of bank 0, which | |
1170 | * occurs before any free memory is mapped. | |
1171 | */ | |
1172 | if (!memblock_limit) { | |
965278dc | 1173 | if (!IS_ALIGNED(block_start, PMD_SIZE)) |
1c2f87c2 | 1174 | memblock_limit = block_start; |
965278dc | 1175 | else if (!IS_ALIGNED(block_end, PMD_SIZE)) |
1c2f87c2 | 1176 | memblock_limit = arm_lowmem_limit; |
c65b7e98 | 1177 | } |
e616c591 | 1178 | |
e616c591 RK |
1179 | } |
1180 | } | |
1c2f87c2 | 1181 | |
eeb3fee8 RK |
1182 | if (should_use_highmem) |
1183 | pr_notice("Consider using a HIGHMEM enabled kernel.\n"); | |
1184 | ||
c7909509 | 1185 | high_memory = __va(arm_lowmem_limit - 1) + 1; |
c65b7e98 RK |
1186 | |
1187 | /* | |
965278dc | 1188 | * Round the memblock limit down to a pmd size. This |
c65b7e98 | 1189 | * helps to ensure that we will allocate memory from the |
965278dc | 1190 | * last full pmd, which should be mapped. |
c65b7e98 RK |
1191 | */ |
1192 | if (memblock_limit) | |
965278dc | 1193 | memblock_limit = round_down(memblock_limit, PMD_SIZE); |
c65b7e98 RK |
1194 | if (!memblock_limit) |
1195 | memblock_limit = arm_lowmem_limit; | |
1196 | ||
1197 | memblock_set_current_limit(memblock_limit); | |
60296c71 LB |
1198 | } |
1199 | ||
4b5f32ce | 1200 | static inline void prepare_page_table(void) |
d111e8f9 RK |
1201 | { |
1202 | unsigned long addr; | |
8df65168 | 1203 | phys_addr_t end; |
d111e8f9 RK |
1204 | |
1205 | /* | |
1206 | * Clear out all the mappings below the kernel image. | |
1207 | */ | |
e73fc88e | 1208 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
d111e8f9 RK |
1209 | pmd_clear(pmd_off_k(addr)); |
1210 | ||
1211 | #ifdef CONFIG_XIP_KERNEL | |
1212 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
e73fc88e | 1213 | addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; |
d111e8f9 | 1214 | #endif |
e73fc88e | 1215 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
d111e8f9 RK |
1216 | pmd_clear(pmd_off_k(addr)); |
1217 | ||
8df65168 RK |
1218 | /* |
1219 | * Find the end of the first block of lowmem. | |
1220 | */ | |
1221 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; | |
c7909509 MS |
1222 | if (end >= arm_lowmem_limit) |
1223 | end = arm_lowmem_limit; | |
8df65168 | 1224 | |
d111e8f9 RK |
1225 | /* |
1226 | * Clear out all the kernel space mappings, except for the first | |
0536bdf3 | 1227 | * memory bank, up to the vmalloc region. |
d111e8f9 | 1228 | */ |
8df65168 | 1229 | for (addr = __phys_to_virt(end); |
0536bdf3 | 1230 | addr < VMALLOC_START; addr += PMD_SIZE) |
d111e8f9 RK |
1231 | pmd_clear(pmd_off_k(addr)); |
1232 | } | |
1233 | ||
1b6ba46b CM |
1234 | #ifdef CONFIG_ARM_LPAE |
1235 | /* the first page is reserved for pgd */ | |
1236 | #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ | |
1237 | PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) | |
1238 | #else | |
e73fc88e | 1239 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
1b6ba46b | 1240 | #endif |
e73fc88e | 1241 | |
d111e8f9 | 1242 | /* |
2778f620 | 1243 | * Reserve the special regions of memory |
d111e8f9 | 1244 | */ |
2778f620 | 1245 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 1246 | { |
d111e8f9 RK |
1247 | /* |
1248 | * Reserve the page tables. These are already in use, | |
1249 | * and can only be in node 0. | |
1250 | */ | |
e73fc88e | 1251 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
d111e8f9 | 1252 | |
d111e8f9 RK |
1253 | #ifdef CONFIG_SA1111 |
1254 | /* | |
1255 | * Because of the SA1111 DMA bug, we want to preserve our | |
1256 | * precious DMA-able memory... | |
1257 | */ | |
2778f620 | 1258 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 1259 | #endif |
d111e8f9 RK |
1260 | } |
1261 | ||
1262 | /* | |
0536bdf3 | 1263 | * Set up the device mappings. Since we clear out the page tables for all |
a5f4c561 SA |
1264 | * mappings above VMALLOC_START, except early fixmap, we might remove debug |
1265 | * device mappings. This means earlycon can be used to debug this function | |
1266 | * Any other function or debugging method which may touch any device _will_ | |
1267 | * crash the kernel. | |
d111e8f9 | 1268 | */ |
ff69a4c8 | 1269 | static void __init devicemaps_init(const struct machine_desc *mdesc) |
d111e8f9 RK |
1270 | { |
1271 | struct map_desc map; | |
1272 | unsigned long addr; | |
94e5a85b | 1273 | void *vectors; |
d111e8f9 RK |
1274 | |
1275 | /* | |
1276 | * Allocate the vector page early. | |
1277 | */ | |
19accfd3 | 1278 | vectors = early_alloc(PAGE_SIZE * 2); |
94e5a85b RK |
1279 | |
1280 | early_trap_init(vectors); | |
d111e8f9 | 1281 | |
a5f4c561 SA |
1282 | /* |
1283 | * Clear page table except top pmd used by early fixmaps | |
1284 | */ | |
1285 | for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE) | |
d111e8f9 RK |
1286 | pmd_clear(pmd_off_k(addr)); |
1287 | ||
1288 | /* | |
1289 | * Map the kernel if it is XIP. | |
1290 | * It is always first in the modulearea. | |
1291 | */ | |
1292 | #ifdef CONFIG_XIP_KERNEL | |
1293 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 1294 | map.virtual = MODULES_VADDR; |
37efe642 | 1295 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
1296 | map.type = MT_ROM; |
1297 | create_mapping(&map); | |
1298 | #endif | |
1299 | ||
1300 | /* | |
1301 | * Map the cache flushing regions. | |
1302 | */ | |
1303 | #ifdef FLUSH_BASE | |
1304 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
1305 | map.virtual = FLUSH_BASE; | |
1306 | map.length = SZ_1M; | |
1307 | map.type = MT_CACHECLEAN; | |
1308 | create_mapping(&map); | |
1309 | #endif | |
1310 | #ifdef FLUSH_BASE_MINICACHE | |
1311 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
1312 | map.virtual = FLUSH_BASE_MINICACHE; | |
1313 | map.length = SZ_1M; | |
1314 | map.type = MT_MINICLEAN; | |
1315 | create_mapping(&map); | |
1316 | #endif | |
1317 | ||
1318 | /* | |
1319 | * Create a mapping for the machine vectors at the high-vectors | |
1320 | * location (0xffff0000). If we aren't using high-vectors, also | |
1321 | * create a mapping at the low-vectors virtual address. | |
1322 | */ | |
94e5a85b | 1323 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
d111e8f9 RK |
1324 | map.virtual = 0xffff0000; |
1325 | map.length = PAGE_SIZE; | |
a5463cd3 | 1326 | #ifdef CONFIG_KUSER_HELPERS |
d111e8f9 | 1327 | map.type = MT_HIGH_VECTORS; |
a5463cd3 RK |
1328 | #else |
1329 | map.type = MT_LOW_VECTORS; | |
1330 | #endif | |
d111e8f9 RK |
1331 | create_mapping(&map); |
1332 | ||
1333 | if (!vectors_high()) { | |
1334 | map.virtual = 0; | |
19accfd3 | 1335 | map.length = PAGE_SIZE * 2; |
d111e8f9 RK |
1336 | map.type = MT_LOW_VECTORS; |
1337 | create_mapping(&map); | |
1338 | } | |
1339 | ||
19accfd3 RK |
1340 | /* Now create a kernel read-only mapping */ |
1341 | map.pfn += 1; | |
1342 | map.virtual = 0xffff0000 + PAGE_SIZE; | |
1343 | map.length = PAGE_SIZE; | |
1344 | map.type = MT_LOW_VECTORS; | |
1345 | create_mapping(&map); | |
1346 | ||
d111e8f9 RK |
1347 | /* |
1348 | * Ask the machine support to map in the statically mapped devices. | |
1349 | */ | |
1350 | if (mdesc->map_io) | |
1351 | mdesc->map_io(); | |
bc37324e MR |
1352 | else |
1353 | debug_ll_io_init(); | |
19b52abe | 1354 | fill_pmd_gaps(); |
d111e8f9 | 1355 | |
c2794437 RH |
1356 | /* Reserve fixed i/o space in VMALLOC region */ |
1357 | pci_reserve_io(); | |
1358 | ||
d111e8f9 RK |
1359 | /* |
1360 | * Finally flush the caches and tlb to ensure that we're in a | |
1361 | * consistent state wrt the writebuffer. This also ensures that | |
1362 | * any write-allocated cache lines in the vector page are written | |
1363 | * back. After this point, we can start to touch devices again. | |
1364 | */ | |
1365 | local_flush_tlb_all(); | |
1366 | flush_cache_all(); | |
bbeb9209 LS |
1367 | |
1368 | /* Enable asynchronous aborts */ | |
9254970c | 1369 | early_abt_enable(); |
d111e8f9 RK |
1370 | } |
1371 | ||
d73cd428 NP |
1372 | static void __init kmap_init(void) |
1373 | { | |
1374 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
1375 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
1376 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 | 1377 | #endif |
836a2418 RH |
1378 | |
1379 | early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START, | |
1380 | _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
1381 | } |
1382 | ||
a2227120 RK |
1383 | static void __init map_lowmem(void) |
1384 | { | |
8df65168 | 1385 | struct memblock_region *reg; |
ac084688 GS |
1386 | phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE); |
1387 | phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); | |
a2227120 RK |
1388 | |
1389 | /* Map all the lowmem memory banks. */ | |
8df65168 RK |
1390 | for_each_memblock(memory, reg) { |
1391 | phys_addr_t start = reg->base; | |
1392 | phys_addr_t end = start + reg->size; | |
1393 | struct map_desc map; | |
1394 | ||
c7909509 MS |
1395 | if (end > arm_lowmem_limit) |
1396 | end = arm_lowmem_limit; | |
8df65168 RK |
1397 | if (start >= end) |
1398 | break; | |
1399 | ||
1e6b4811 | 1400 | if (end < kernel_x_start) { |
ebd4922e RK |
1401 | map.pfn = __phys_to_pfn(start); |
1402 | map.virtual = __phys_to_virt(start); | |
1403 | map.length = end - start; | |
1404 | map.type = MT_MEMORY_RWX; | |
a2227120 | 1405 | |
1e6b4811 KC |
1406 | create_mapping(&map); |
1407 | } else if (start >= kernel_x_end) { | |
1408 | map.pfn = __phys_to_pfn(start); | |
1409 | map.virtual = __phys_to_virt(start); | |
1410 | map.length = end - start; | |
1411 | map.type = MT_MEMORY_RW; | |
1412 | ||
ebd4922e RK |
1413 | create_mapping(&map); |
1414 | } else { | |
1415 | /* This better cover the entire kernel */ | |
1416 | if (start < kernel_x_start) { | |
1417 | map.pfn = __phys_to_pfn(start); | |
1418 | map.virtual = __phys_to_virt(start); | |
1419 | map.length = kernel_x_start - start; | |
1420 | map.type = MT_MEMORY_RW; | |
1421 | ||
1422 | create_mapping(&map); | |
1423 | } | |
1424 | ||
1425 | map.pfn = __phys_to_pfn(kernel_x_start); | |
1426 | map.virtual = __phys_to_virt(kernel_x_start); | |
1427 | map.length = kernel_x_end - kernel_x_start; | |
1428 | map.type = MT_MEMORY_RWX; | |
1429 | ||
1430 | create_mapping(&map); | |
1431 | ||
1432 | if (kernel_x_end < end) { | |
1433 | map.pfn = __phys_to_pfn(kernel_x_end); | |
1434 | map.virtual = __phys_to_virt(kernel_x_end); | |
1435 | map.length = end - kernel_x_end; | |
1436 | map.type = MT_MEMORY_RW; | |
1437 | ||
1438 | create_mapping(&map); | |
1439 | } | |
1440 | } | |
a2227120 RK |
1441 | } |
1442 | } | |
1443 | ||
d8dc7fbd RK |
1444 | #ifdef CONFIG_ARM_PV_FIXUP |
1445 | extern unsigned long __atags_pointer; | |
1446 | typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata); | |
1447 | pgtables_remap lpae_pgtables_remap_asm; | |
1448 | ||
a77e0c7b SS |
1449 | /* |
1450 | * early_paging_init() recreates boot time page table setup, allowing machines | |
1451 | * to switch over to a high (>4G) address space on LPAE systems | |
1452 | */ | |
1221ed10 | 1453 | void __init early_paging_init(const struct machine_desc *mdesc) |
a77e0c7b | 1454 | { |
d8dc7fbd RK |
1455 | pgtables_remap *lpae_pgtables_remap; |
1456 | unsigned long pa_pgd; | |
1457 | unsigned int cr, ttbcr; | |
c8ca2b4b | 1458 | long long offset; |
d8dc7fbd | 1459 | void *boot_data; |
a77e0c7b | 1460 | |
c0b759d8 | 1461 | if (!mdesc->pv_fixup) |
a77e0c7b SS |
1462 | return; |
1463 | ||
c0b759d8 | 1464 | offset = mdesc->pv_fixup(); |
c8ca2b4b RK |
1465 | if (offset == 0) |
1466 | return; | |
a77e0c7b | 1467 | |
d8dc7fbd RK |
1468 | /* |
1469 | * Get the address of the remap function in the 1:1 identity | |
1470 | * mapping setup by the early page table assembly code. We | |
1471 | * must get this prior to the pv update. The following barrier | |
1472 | * ensures that this is complete before we fixup any P:V offsets. | |
1473 | */ | |
1474 | lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm); | |
1475 | pa_pgd = __pa(swapper_pg_dir); | |
1476 | boot_data = __va(__atags_pointer); | |
1477 | barrier(); | |
a77e0c7b | 1478 | |
39b74fe8 RK |
1479 | pr_info("Switching physical address space to 0x%08llx\n", |
1480 | (u64)PHYS_OFFSET + offset); | |
a77e0c7b | 1481 | |
c8ca2b4b RK |
1482 | /* Re-set the phys pfn offset, and the pv offset */ |
1483 | __pv_offset += offset; | |
1484 | __pv_phys_pfn_offset += PFN_DOWN(offset); | |
a77e0c7b SS |
1485 | |
1486 | /* Run the patch stub to update the constants */ | |
1487 | fixup_pv_table(&__pv_table_begin, | |
1488 | (&__pv_table_end - &__pv_table_begin) << 2); | |
1489 | ||
1490 | /* | |
d8dc7fbd RK |
1491 | * We changing not only the virtual to physical mapping, but also |
1492 | * the physical addresses used to access memory. We need to flush | |
1493 | * all levels of cache in the system with caching disabled to | |
1494 | * ensure that all data is written back, and nothing is prefetched | |
1495 | * into the caches. We also need to prevent the TLB walkers | |
1496 | * allocating into the caches too. Note that this is ARMv7 LPAE | |
1497 | * specific. | |
3bb70de6 | 1498 | */ |
d8dc7fbd RK |
1499 | cr = get_cr(); |
1500 | set_cr(cr & ~(CR_I | CR_C)); | |
1501 | asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr)); | |
1502 | asm volatile("mcr p15, 0, %0, c2, c0, 2" | |
1503 | : : "r" (ttbcr & ~(3 << 8 | 3 << 10))); | |
a77e0c7b | 1504 | flush_cache_all(); |
3bb70de6 RK |
1505 | |
1506 | /* | |
d8dc7fbd RK |
1507 | * Fixup the page tables - this must be in the idmap region as |
1508 | * we need to disable the MMU to do this safely, and hence it | |
1509 | * needs to be assembly. It's fairly simple, as we're using the | |
1510 | * temporary tables setup by the initial assembly code. | |
3bb70de6 | 1511 | */ |
d8dc7fbd | 1512 | lpae_pgtables_remap(offset, pa_pgd, boot_data); |
3bb70de6 | 1513 | |
d8dc7fbd RK |
1514 | /* Re-enable the caches and cacheable TLB walks */ |
1515 | asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr)); | |
1516 | set_cr(cr); | |
a77e0c7b SS |
1517 | } |
1518 | ||
1519 | #else | |
1520 | ||
1221ed10 | 1521 | void __init early_paging_init(const struct machine_desc *mdesc) |
a77e0c7b | 1522 | { |
c8ca2b4b RK |
1523 | long long offset; |
1524 | ||
c0b759d8 | 1525 | if (!mdesc->pv_fixup) |
c8ca2b4b RK |
1526 | return; |
1527 | ||
c0b759d8 | 1528 | offset = mdesc->pv_fixup(); |
c8ca2b4b RK |
1529 | if (offset == 0) |
1530 | return; | |
1531 | ||
1532 | pr_crit("Physical address space modification is only to support Keystone2.\n"); | |
1533 | pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n"); | |
1534 | pr_crit("feature. Your kernel may crash now, have a good day.\n"); | |
1535 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); | |
a77e0c7b SS |
1536 | } |
1537 | ||
1538 | #endif | |
1539 | ||
a5f4c561 SA |
1540 | static void __init early_fixmap_shutdown(void) |
1541 | { | |
1542 | int i; | |
1543 | unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1); | |
1544 | ||
1545 | pte_offset_fixmap = pte_offset_late_fixmap; | |
1546 | pmd_clear(fixmap_pmd(va)); | |
1547 | local_flush_tlb_kernel_page(va); | |
1548 | ||
1549 | for (i = 0; i < __end_of_permanent_fixed_addresses; i++) { | |
1550 | pte_t *pte; | |
1551 | struct map_desc map; | |
1552 | ||
1553 | map.virtual = fix_to_virt(i); | |
1554 | pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual); | |
1555 | ||
1556 | /* Only i/o device mappings are supported ATM */ | |
1557 | if (pte_none(*pte) || | |
1558 | (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED) | |
1559 | continue; | |
1560 | ||
1561 | map.pfn = pte_pfn(*pte); | |
1562 | map.type = MT_DEVICE; | |
1563 | map.length = PAGE_SIZE; | |
1564 | ||
1565 | create_mapping(&map); | |
1566 | } | |
1567 | } | |
1568 | ||
d111e8f9 RK |
1569 | /* |
1570 | * paging_init() sets up the page tables, initialises the zone memory | |
1571 | * maps, and sets up the zero page, bad page and bad page tables. | |
1572 | */ | |
ff69a4c8 | 1573 | void __init paging_init(const struct machine_desc *mdesc) |
d111e8f9 RK |
1574 | { |
1575 | void *zero_page; | |
1576 | ||
1577 | build_mem_type_table(); | |
4b5f32ce | 1578 | prepare_page_table(); |
a2227120 | 1579 | map_lowmem(); |
3de1f52a | 1580 | memblock_set_current_limit(arm_lowmem_limit); |
c7909509 | 1581 | dma_contiguous_remap(); |
a5f4c561 | 1582 | early_fixmap_shutdown(); |
d111e8f9 | 1583 | devicemaps_init(mdesc); |
d73cd428 | 1584 | kmap_init(); |
de40614e | 1585 | tcm_init(); |
d111e8f9 RK |
1586 | |
1587 | top_pmd = pmd_off_k(0xffff0000); | |
1588 | ||
3abe9d33 RK |
1589 | /* allocate the zero page. */ |
1590 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1591 | |
8d717a52 | 1592 | bootmem_init(); |
2778f620 | 1593 | |
d111e8f9 | 1594 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1595 | __flush_dcache_page(NULL, empty_zero_page); |
d111e8f9 | 1596 | } |