[deliverable/linux.git] / arch / arm / mm / proc-arm1020.S

/*
 *  linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
 *
 *  Copyright (C) 2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm1020.
 *
 *  CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define MAX_AREA_SIZE	32768

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	16

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintenance instructions.
 */
#define CACHE_DLIMIT	32768

	.text
/*
 * cpu_arm1020_proc_init()
 */
ENTRY(cpu_arm1020_proc_init)
	mov	pc, lr

/*
 * cpu_arm1020_proc_fin()
 */
ENTRY(cpu_arm1020_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000 		@ ...i............
	bic	r0, r0, #0x000e 		@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_arm1020_reset(loc)
 *
 * Perform a soft reset of the system.	Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
	.pushsection	.idmap.text, "ax"
ENTRY(cpu_arm1020_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f 		@ ............wcam
	bic	ip, ip, #0x1100 		@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0
ENDPROC(cpu_arm1020_reset)
	.popsection

/*
 * cpu_arm1020_do_idle()
 */
	.align	5
ENTRY(cpu_arm1020_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mov	pc, lr

/* ================================= CACHE ================================ */

	.align	5

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(arm1020_flush_icache_all)
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
#endif
	mov	pc, lr
ENDPROC(arm1020_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
ENTRY(arm1020_flush_user_cache_all)
	/* FALLTHROUGH */
/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm1020_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 16 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 15 to 0
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags for this space
 */
ENTRY(arm1020_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, ip, c7, c10, 4
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020_coherent_kern_range)
	/* FALLTRHOUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020_coherent_user_range)
	mov	ip, #0
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcr	p15, 0, ip, c7, c10, 4
1:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(arm1020_flush_kern_dcache_area)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1020_dma_inv_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, ip, c7, c10, 4
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, ip, c7, c10, 4
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1020_dma_clean_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020_dma_flush_range)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcr	p15, 0, ip, c7, c10, 4
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm1020_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm1020_dma_clean_range
	bcs	arm1020_dma_inv_range
	b	arm1020_dma_flush_range
ENDPROC(arm1020_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm1020_dma_unmap_area)
	mov	pc, lr
ENDPROC(arm1020_dma_unmap_area)

	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
	define_cache_functions arm1020

	.align	5
ENTRY(cpu_arm1020_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mov	ip, #0
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm1020_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm1020_switch_mm)
#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r3, c7, c10, 4
	mov	r1, #0xF			@ 16 segments
1:	mov	r3, #0x3F			@ 64 entries
2:	mov	ip, r3, LSL #26 		@ shift up entry
	orr	ip, ip, r1, LSL #5		@ shift in/up index
	mcr	p15, 0, ip, c7, c14, 2		@ Clean & Inval DCache entry
	mov	ip, #0
	mcr	p15, 0, ip, c7, c10, 4
	subs	r3, r3, #1
	cmp	r3, #0
	bge	2b				@ entries 3F to 0
	subs	r1, r1, #1
	cmp	r1, #0
	bge	1b				@ segments 15 to 0

#endif
	mov	r1, #0
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
#endif
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs
#endif /* CONFIG_MMU */
	mov	pc, lr
        
/*
 * cpu_arm1020_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm1020_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 4
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif /* CONFIG_MMU */
	mov	pc, lr

	__CPUINIT

	.type	__arm1020_setup, #function
__arm1020_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif

	adr	r5, arm1020_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000 		@ .R.. .... .... ....
#endif
	mov	pc, lr
	.size	__arm1020_setup, . - __arm1020_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 1001 ..11 0101
	 */
	.type	arm1020_crval, #object
arm1020_crval:
	crval	clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930

	__INITDATA
	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort


	.section ".rodata"

	string	cpu_arch_name, "armv5t"
	string	cpu_elf_name, "v5"

	.type	cpu_arm1020_name, #object
cpu_arm1020_name:
	.ascii	"ARM1020"
#ifndef CONFIG_CPU_ICACHE_DISABLE
	.ascii	"i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
	.ascii	"d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	.ascii	"(wt)"
#else
	.ascii	"(wb)"
#endif
#endif
#ifndef CONFIG_CPU_BPREDICT_DISABLE
	.ascii	"B"
#endif
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	.ascii	"RR"
#endif
	.ascii	"\0"
	.size	cpu_arm1020_name, . - cpu_arm1020_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm1020_proc_info,#object
__arm1020_proc_info:
	.long	0x4104a200			@ ARM 1020T (Architecture v5T)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm1020_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm1020_name
	.long	arm1020_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm1020_cache_fns
	.size	__arm1020_proc_info, . - __arm1020_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
	3	*
	4	* Copyright (C) 2000 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	6	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*
	23	* These are the low level assembler for performing cache and TLB
	24	* functions on the arm1020.
	25	*
	26	* CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
	27	*/
	28	#include <linux/linkage.h>
1da177e4 LT	29	#include <linux/init.h>
1da177e4 LT	30	#include <asm/assembler.h>
e6ae744d	31	#include <asm/asm-offsets.h>
5ec9407d	32	#include <asm/hwcap.h>
74945c86	33	#include <asm/pgtable-hwdef.h>
1da177e4	34	#include <asm/pgtable.h>
1da177e4	35	#include <asm/ptrace.h>
1da177e4	36
00eb0f6b RK	37	#include "proc-macros.S"
00eb0f6b RK	38
1da177e4 LT	39	/*
	40	* This is the maximum size of an area which will be invalidated
	41	* using the single invalidate entry instructions. Anything larger
	42	* than this, and we go for the whole cache.
	43	*
	44	* This value should be chosen such that we choose the cheapest
	45	* alternative.
	46	*/
	47	#define MAX_AREA_SIZE 32768
	48
	49	/*
	50	* The size of one data cache line.
	51	*/
	52	#define CACHE_DLINESIZE 32
	53
	54	/*
	55	* The number of data cache segments.
	56	*/
	57	#define CACHE_DSEGMENTS 16
	58
	59	/*
	60	* The number of lines in a cache segment.
	61	*/
	62	#define CACHE_DENTRIES 64
	63
	64	/*
	65	* This is the size at which it becomes more efficient to
	66	* clean the whole cache, rather than using the individual
25985edc	67	* cache line maintenance instructions.
1da177e4 LT	68	*/
	69	#define CACHE_DLIMIT 32768
	70
	71	.text
	72	/*
	73	* cpu_arm1020_proc_init()
	74	*/
	75	ENTRY(cpu_arm1020_proc_init)
	76	mov pc, lr
	77
	78	/*
	79	* cpu_arm1020_proc_fin()
	80	*/
	81	ENTRY(cpu_arm1020_proc_fin)
1da177e4 LT	82	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	83	bic r0, r0, #0x1000 @ ...i............
	84	bic r0, r0, #0x000e @ ............wca.
	85	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	86	mov pc, lr
1da177e4 LT	87
	88	/*
	89	* cpu_arm1020_reset(loc)
	90	*
	91	* Perform a soft reset of the system. Put the CPU into the
	92	* same state as it would be if it had been reset, and branch
	93	* to what would be the reset vector.
	94	*
	95	* loc: location to jump to for soft reset
	96	*/
	97	.align 5
1a4baafa	98	.pushsection .idmap.text, "ax"
1da177e4 LT	99	ENTRY(cpu_arm1020_reset)
	100	mov ip, #0
	101	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	102	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	103	#ifdef CONFIG_MMU
1da177e4	104	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	105	#endif
1da177e4 LT	106	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	107	bic ip, ip, #0x000f @ ............wcam
	108	bic ip, ip, #0x1100 @ ...i...s........
	109	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	110	mov pc, r0
1a4baafa WD	111	ENDPROC(cpu_arm1020_reset)
1a4baafa WD	112	.popsection
1da177e4 LT	113
	114	/*
	115	* cpu_arm1020_do_idle()
	116	*/
	117	.align 5
	118	ENTRY(cpu_arm1020_do_idle)
	119	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	120	mov pc, lr
	121
	122	/* ================================= CACHE ================================ */
	123
	124	.align 5
c8c90860 MW	125
	126	/*
	127	* flush_icache_all()
	128	*
	129	* Unconditionally clean and invalidate the entire icache.
	130	*/
	131	ENTRY(arm1020_flush_icache_all)
	132	#ifndef CONFIG_CPU_ICACHE_DISABLE
	133	mov r0, #0
	134	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	135	#endif
	136	mov pc, lr
	137	ENDPROC(arm1020_flush_icache_all)
	138
1da177e4 LT	139	/*
	140	* flush_user_cache_all()
	141	*
	142	* Invalidate all cache entries in a particular address
	143	* space.
	144	*/
	145	ENTRY(arm1020_flush_user_cache_all)
	146	/* FALLTHROUGH */
	147	/*
	148	* flush_kern_cache_all()
	149	*
	150	* Clean and invalidate the entire cache.
	151	*/
	152	ENTRY(arm1020_flush_kern_cache_all)
	153	mov r2, #VM_EXEC
	154	mov ip, #0
	155	__flush_whole_cache:
	156	#ifndef CONFIG_CPU_DCACHE_DISABLE
	157	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	158	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
	159	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	160	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	161	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	162	subs r3, r3, #1 << 26
	163	bcs 2b @ entries 63 to 0
	164	subs r1, r1, #1 << 5
	165	bcs 1b @ segments 15 to 0
	166	#endif
	167	tst r2, #VM_EXEC
	168	#ifndef CONFIG_CPU_ICACHE_DISABLE
	169	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	170	#endif
	171	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	172	mov pc, lr
	173
	174	/*
	175	* flush_user_cache_range(start, end, flags)
	176	*
	177	* Invalidate a range of cache entries in the specified
	178	* address space.
	179	*
	180	* - start - start address (inclusive)
	181	* - end - end address (exclusive)
	182	* - flags - vm_flags for this space
	183	*/
	184	ENTRY(arm1020_flush_user_cache_range)
	185	mov ip, #0
	186	sub r3, r1, r0 @ calculate total size
	187	cmp r3, #CACHE_DLIMIT
	188	bhs __flush_whole_cache
	189
	190	#ifndef CONFIG_CPU_DCACHE_DISABLE
	191	mcr p15, 0, ip, c7, c10, 4
	192	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	193	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	194	add r0, r0, #CACHE_DLINESIZE
	195	cmp r0, r1
	196	blo 1b
	197	#endif
	198	tst r2, #VM_EXEC
	199	#ifndef CONFIG_CPU_ICACHE_DISABLE
	200	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	201	#endif
	202	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
203	mov pc, lr
204
205	/*
206	* coherent_kern_range(start, end)
207	*
208	* Ensure coherency between the Icache and the Dcache in the
209	* region described by start. If you have non-snooping
210	* Harvard caches, you need to implement this function.
211	*
212	* - start - virtual start address
213	* - end - virtual end address
214	*/
215	ENTRY(arm1020_coherent_kern_range)
216	/* FALLTRHOUGH */
217
218	/*
219	* coherent_user_range(start, end)
220	*
221	* Ensure coherency between the Icache and the Dcache in the
222	* region described by start. If you have non-snooping
223	* Harvard caches, you need to implement this function.
224	*
225	* - start - virtual start address
226	* - end - virtual end address
227	*/
228	ENTRY(arm1020_coherent_user_range)
229	mov ip, #0
230	bic r0, r0, #CACHE_DLINESIZE - 1
231	mcr p15, 0, ip, c7, c10, 4
232	1:
233	#ifndef CONFIG_CPU_DCACHE_DISABLE
234	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
235	mcr p15, 0, ip, c7, c10, 4 @ drain WB
236	#endif
237	#ifndef CONFIG_CPU_ICACHE_DISABLE
238	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
239	#endif
240	add r0, r0, #CACHE_DLINESIZE
241	cmp r0, r1
242	blo 1b
243	mcr p15, 0, ip, c7, c10, 4 @ drain WB
244	mov pc, lr
245
246	/*
2c9b9c84	247	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	248	*
	249	* Ensure no D cache aliasing occurs, either with itself or
	250	* the I cache
	251	*
2c9b9c84 RK	252	* - addr - kernel address
2c9b9c84 RK	253	* - size - region size
1da177e4	254	*/
2c9b9c84	255	ENTRY(arm1020_flush_kern_dcache_area)
1da177e4 LT	256	mov ip, #0
1da177e4 LT	257	#ifndef CONFIG_CPU_DCACHE_DISABLE
2c9b9c84	258	add r1, r0, r1
1da177e4 LT	259	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	260	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	261	add r0, r0, #CACHE_DLINESIZE
	262	cmp r0, r1
	263	blo 1b
	264	#endif
	265	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	266	mov pc, lr
	267
	268	/*
	269	* dma_inv_range(start, end)
	270	*
	271	* Invalidate (discard) the specified virtual address range.
	272	* May not write back any entries. If 'start' or 'end'
	273	* are not cache line aligned, those lines must be written
	274	* back.
	275	*
	276	* - start - virtual start address
	277	* - end - virtual end address
	278	*
	279	* (same as v4wb)
	280	*/
702b94bf	281	arm1020_dma_inv_range:
1da177e4 LT	282	mov ip, #0
	283	#ifndef CONFIG_CPU_DCACHE_DISABLE
	284	tst r0, #CACHE_DLINESIZE - 1
	285	bic r0, r0, #CACHE_DLINESIZE - 1
	286	mcrne p15, 0, ip, c7, c10, 4
	287	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	288	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	289	tst r1, #CACHE_DLINESIZE - 1
	290	mcrne p15, 0, ip, c7, c10, 4
	291	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	292	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	293	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	294	add r0, r0, #CACHE_DLINESIZE
	295	cmp r0, r1
	296	blo 1b
	297	#endif
	298	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	299	mov pc, lr
	300
	301	/*
	302	* dma_clean_range(start, end)
	303	*
	304	* Clean the specified virtual address range.
	305	*
	306	* - start - virtual start address
	307	* - end - virtual end address
	308	*
	309	* (same as v4wb)
	310	*/
702b94bf	311	arm1020_dma_clean_range:
1da177e4 LT	312	mov ip, #0
	313	#ifndef CONFIG_CPU_DCACHE_DISABLE
	314	bic r0, r0, #CACHE_DLINESIZE - 1
	315	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	316	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	317	add r0, r0, #CACHE_DLINESIZE
	318	cmp r0, r1
	319	blo 1b
	320	#endif
	321	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	322	mov pc, lr
	323
	324	/*
	325	* dma_flush_range(start, end)
	326	*
	327	* Clean and invalidate the specified virtual address range.
	328	*
	329	* - start - virtual start address
	330	* - end - virtual end address
	331	*/
	332	ENTRY(arm1020_dma_flush_range)
	333	mov ip, #0
	334	#ifndef CONFIG_CPU_DCACHE_DISABLE
	335	bic r0, r0, #CACHE_DLINESIZE - 1
	336	mcr p15, 0, ip, c7, c10, 4
	337	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	338	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	339	add r0, r0, #CACHE_DLINESIZE
	340	cmp r0, r1
	341	blo 1b
	342	#endif
	343	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	344	mov pc, lr
	345
a9c9147e RK	346	/*
	347	* dma_map_area(start, size, dir)
	348	* - start - kernel virtual start address
	349	* - size - size of region
	350	* - dir - DMA direction
	351	*/
	352	ENTRY(arm1020_dma_map_area)
	353	add r1, r1, r0
	354	cmp r2, #DMA_TO_DEVICE
	355	beq arm1020_dma_clean_range
	356	bcs arm1020_dma_inv_range
	357	b arm1020_dma_flush_range
	358	ENDPROC(arm1020_dma_map_area)
	359
	360	/*
	361	* dma_unmap_area(start, size, dir)
	362	* - start - kernel virtual start address
	363	* - size - size of region
	364	* - dir - DMA direction
	365	*/
	366	ENTRY(arm1020_dma_unmap_area)
	367	mov pc, lr
	368	ENDPROC(arm1020_dma_unmap_area)
	369
56d91650 DM	370	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
56d91650 DM	371	define_cache_functions arm1020
1da177e4 LT	372
	373	.align 5
	374	ENTRY(cpu_arm1020_dcache_clean_area)
	375	#ifndef CONFIG_CPU_DCACHE_DISABLE
	376	mov ip, #0
	377	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	378	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	379	add r0, r0, #CACHE_DLINESIZE
	380	subs r1, r1, #CACHE_DLINESIZE
	381	bhi 1b
	382	#endif
	383	mov pc, lr
	384
	385	/* =============================== PageTable ============================== */
	386
	387	/*
	388	* cpu_arm1020_switch_mm(pgd)
	389	*
	390	* Set the translation base pointer to be as described by pgd.
	391	*
	392	* pgd: new page tables
	393	*/
	394	.align 5
	395	ENTRY(cpu_arm1020_switch_mm)
d090ddda	396	#ifdef CONFIG_MMU
1da177e4 LT	397	#ifndef CONFIG_CPU_DCACHE_DISABLE
	398	mcr p15, 0, r3, c7, c10, 4
	399	mov r1, #0xF @ 16 segments
	400	1: mov r3, #0x3F @ 64 entries
	401	2: mov ip, r3, LSL #26 @ shift up entry
	402	orr ip, ip, r1, LSL #5 @ shift in/up index
	403	mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
	404	mov ip, #0
	405	mcr p15, 0, ip, c7, c10, 4
	406	subs r3, r3, #1
	407	cmp r3, #0
	408	bge 2b @ entries 3F to 0
	409	subs r1, r1, #1
	410	cmp r1, #0
	411	bge 1b @ segments 15 to 0
	412
	413	#endif
	414	mov r1, #0
	415	#ifndef CONFIG_CPU_ICACHE_DISABLE
	416	mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
	417	#endif
	418	mcr p15, 0, r1, c7, c10, 4 @ drain WB
	419	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	420	mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	421	#endif /* CONFIG_MMU */
1da177e4 LT	422	mov pc, lr
	423
	424	/*
	425	* cpu_arm1020_set_pte(ptep, pte)
	426	*
	427	* Set a PTE and flush it out
	428	*/
	429	.align 5
ad1ae2fe	430	ENTRY(cpu_arm1020_set_pte_ext)
d090ddda	431	#ifdef CONFIG_MMU
da091653	432	armv3_set_pte_ext
1da177e4 LT	433	mov r0, r0
	434	#ifndef CONFIG_CPU_DCACHE_DISABLE
	435	mcr p15, 0, r0, c7, c10, 4
	436	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	437	#endif
	438	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	439	#endif /* CONFIG_MMU */
1da177e4 LT	440	mov pc, lr
1da177e4 LT	441
5085f3ff	442	__CPUINIT
1da177e4 LT	443
	444	.type __arm1020_setup, #function
	445	__arm1020_setup:
	446	mov r0, #0
	447	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	448	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	449	#ifdef CONFIG_MMU
1da177e4	450	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	451	#endif
22b19086 RK	452
	453	adr r5, arm1020_crval
	454	ldmia r5, {r5, r6}
1da177e4	455	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	456	bic r0, r0, r5
22b19086	457	orr r0, r0, r6
1da177e4 LT	458	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	459	orr r0, r0, #0x4000 @ .R.. .... .... ....
	460	#endif
	461	mov pc, lr
	462	.size __arm1020_setup, . - __arm1020_setup
	463
	464	/*
	465	* R
	466	* .RVI ZFRS BLDP WCAM
abaf48a0	467	* .011 1001 ..11 0101
1da177e4	468	*/
22b19086 RK	469	.type arm1020_crval, #object
	470	arm1020_crval:
	471	crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
1da177e4 LT	472
1da177e4 LT	473	__INITDATA
56d91650 DM	474	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
56d91650 DM	475	define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
1da177e4	476
1da177e4 LT	477
	478	.section ".rodata"
	479
56d91650 DM	480	string cpu_arch_name, "armv5t"
56d91650 DM	481	string cpu_elf_name, "v5"
1da177e4 LT	482
	483	.type cpu_arm1020_name, #object
	484	cpu_arm1020_name:
	485	.ascii "ARM1020"
	486	#ifndef CONFIG_CPU_ICACHE_DISABLE
	487	.ascii "i"
	488	#endif
	489	#ifndef CONFIG_CPU_DCACHE_DISABLE
	490	.ascii "d"
	491	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	492	.ascii "(wt)"
	493	#else
	494	.ascii "(wb)"
	495	#endif
	496	#endif
	497	#ifndef CONFIG_CPU_BPREDICT_DISABLE
	498	.ascii "B"
	499	#endif
	500	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	501	.ascii "RR"
	502	#endif
	503	.ascii "\0"
	504	.size cpu_arm1020_name, . - cpu_arm1020_name
	505
	506	.align
	507
02b7dd12	508	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	509
	510	.type __arm1020_proc_info,#object
	511	__arm1020_proc_info:
	512	.long 0x4104a200 @ ARM 1020T (Architecture v5T)
	513	.long 0xff0ffff0
8799ee9f RK	514	.long PMD_TYPE_SECT \| \
	515	PMD_SECT_AP_WRITE \| \
	516	PMD_SECT_AP_READ
1da177e4 LT	517	.long PMD_TYPE_SECT \| \
	518	PMD_SECT_AP_WRITE \| \
	519	PMD_SECT_AP_READ
	520	b __arm1020_setup
	521	.long cpu_arch_name
	522	.long cpu_elf_name
	523	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	524	.long cpu_arm1020_name
	525	.long arm1020_processor_functions
	526	.long v4wbi_tlb_fns
	527	.long v4wb_user_fns
	528	.long arm1020_cache_fns
	529	.size __arm1020_proc_info, . - __arm1020_proc_info