[deliverable/linux.git] / arch / arm / mm / proc-arm6_7.S

/*
 *  linux/arch/arm/mm/proc-arm6,7.S
 *
 *  Copyright (C) 1997-2000 Russell King
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  These are the low level assembler for performing cache and TLB
 *  functions on the ARM610 & ARM710.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

ENTRY(cpu_arm6_dcache_clean_area)
ENTRY(cpu_arm7_dcache_clean_area)
		mov	pc, lr

/*
 * Function: arm6_7_data_abort ()
 *
 * Params  : r2 = pt_regs
 *	   : r4 = aborted context pc
 *	   : r5 = aborted context psr
 *
 * Purpose : obtain information about current aborted instruction
 *
 * Returns : r4-r5, r10-r11, r13 preserved
 */

ENTRY(cpu_arm7_data_abort)
	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
	ldr	r8, [r4]			@ read arm instruction
	tst	r8, #1 << 20			@ L = 0 -> write?
	orreq	r1, r1, #1 << 11		@ yes.
	and	r7, r8, #15 << 24
	add	pc, pc, r7, lsr #22		@ Now branch to the relevant processing routine
	nop

/* 0 */	b	.data_unknown
/* 1 */	b	do_DataAbort			@ swp
/* 2 */	b	.data_unknown
/* 3 */	b	.data_unknown
/* 4 */	b	.data_arm_lateldrpostconst	@ ldr	rd, [rn], #m
/* 5 */	b	.data_arm_lateldrpreconst	@ ldr	rd, [rn, #m]
/* 6 */	b	.data_arm_lateldrpostreg	@ ldr	rd, [rn], rm
/* 7 */	b	.data_arm_lateldrprereg		@ ldr	rd, [rn, rm]
/* 8 */	b	.data_arm_ldmstm		@ ldm*a	rn, <rlist>
/* 9 */	b	.data_arm_ldmstm		@ ldm*b	rn, <rlist>
/* a */	b	.data_unknown
/* b */	b	.data_unknown
/* c */	b	do_DataAbort			@ ldc	rd, [rn], #m	@ Same as ldr	rd, [rn], #m
/* d */	b	do_DataAbort			@ ldc	rd, [rn, #m]
/* e */	b	.data_unknown
/* f */
.data_unknown:	@ Part of jumptable
	mov	r0, r4
	mov	r1, r8
	b	baddataabort

ENTRY(cpu_arm6_data_abort)
	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
	ldr	r8, [r4]			@ read arm instruction
	tst	r8, #1 << 20			@ L = 0 -> write?
	orreq	r1, r1, #1 << 11		@ yes.
	and	r7, r8, #14 << 24
	teq	r7, #8 << 24			@ was it ldm/stm
	bne	do_DataAbort

.data_arm_ldmstm:
	tst	r8, #1 << 21			@ check writeback bit
	beq	do_DataAbort			@ no writeback -> no fixup
	mov	r7, #0x11
	orr	r7, r7, #0x1100
	and	r6, r8, r7
	and	r9, r8, r7, lsl #1
	add	r6, r6, r9, lsr #1
	and	r9, r8, r7, lsl #2
	add	r6, r6, r9, lsr #2
	and	r9, r8, r7, lsl #3
	add	r6, r6, r9, lsr #3
	add	r6, r6, r6, lsr #8
	add	r6, r6, r6, lsr #4
	and	r6, r6, #15			@ r6 = no. of registers to transfer.
	and	r9, r8, #15 << 16		@ Extract 'n' from instruction
	ldr	r7, [r2, r9, lsr #14]		@ Get register 'Rn'
	tst	r8, #1 << 23			@ Check U bit
	subne	r7, r7, r6, lsl #2		@ Undo increment
	addeq	r7, r7, r6, lsl #2		@ Undo decrement
	str	r7, [r2, r9, lsr #14]		@ Put register 'Rn'
	b	do_DataAbort

.data_arm_apply_r6_and_rn:
	and	r9, r8, #15 << 16		@ Extract 'n' from instruction
	ldr	r7, [r2, r9, lsr #14]		@ Get register 'Rn'
	tst	r8, #1 << 23			@ Check U bit
	subne	r7, r7, r6			@ Undo incrmenet
	addeq	r7, r7, r6			@ Undo decrement
	str	r7, [r2, r9, lsr #14]		@ Put register 'Rn'
	b	do_DataAbort

.data_arm_lateldrpreconst:
	tst	r8, #1 << 21			@ check writeback bit
	beq	do_DataAbort			@ no writeback -> no fixup
.data_arm_lateldrpostconst:
	movs	r6, r8, lsl #20			@ Get offset
	beq	do_DataAbort			@ zero -> no fixup
	and	r9, r8, #15 << 16		@ Extract 'n' from instruction
	ldr	r7, [r2, r9, lsr #14]		@ Get register 'Rn'
	tst	r8, #1 << 23			@ Check U bit
	subne	r7, r7, r6, lsr #20		@ Undo increment
	addeq	r7, r7, r6, lsr #20		@ Undo decrement
	str	r7, [r2, r9, lsr #14]		@ Put register 'Rn'
	b	do_DataAbort

.data_arm_lateldrprereg:
	tst	r8, #1 << 21			@ check writeback bit
	beq	do_DataAbort			@ no writeback -> no fixup
.data_arm_lateldrpostreg:
	and	r7, r8, #15			@ Extract 'm' from instruction
	ldr	r6, [r2, r7, lsl #2]		@ Get register 'Rm'
	mov	r9, r8, lsr #7			@ get shift count
	ands	r9, r9, #31
	and	r7, r8, #0x70			@ get shift type
	orreq	r7, r7, #8			@ shift count = 0
	add	pc, pc, r7
	nop

	mov	r6, r6, lsl r9			@ 0: LSL #!0
	b	.data_arm_apply_r6_and_rn
	b	.data_arm_apply_r6_and_rn	@ 1: LSL #0
	nop
	b	.data_unknown			@ 2: MUL?
	nop
	b	.data_unknown			@ 3: MUL?
	nop
	mov	r6, r6, lsr r9			@ 4: LSR #!0
	b	.data_arm_apply_r6_and_rn
	mov	r6, r6, lsr #32			@ 5: LSR #32
	b	.data_arm_apply_r6_and_rn
	b	.data_unknown			@ 6: MUL?
	nop
	b	.data_unknown			@ 7: MUL?
	nop
	mov	r6, r6, asr r9			@ 8: ASR #!0
	b	.data_arm_apply_r6_and_rn
	mov	r6, r6, asr #32			@ 9: ASR #32
	b	.data_arm_apply_r6_and_rn
	b	.data_unknown			@ A: MUL?
	nop
	b	.data_unknown			@ B: MUL?
	nop
	mov	r6, r6, ror r9			@ C: ROR #!0
	b	.data_arm_apply_r6_and_rn
	mov	r6, r6, rrx			@ D: RRX
	b	.data_arm_apply_r6_and_rn
	b	.data_unknown			@ E: MUL?
	nop
	b	.data_unknown			@ F: MUL?

/*
 * Function: arm6_7_proc_init (void)
 *	   : arm6_7_proc_fin (void)
 *
 * Notes   : This processor does not require these
 */
ENTRY(cpu_arm6_proc_init)
ENTRY(cpu_arm7_proc_init)
		mov	pc, lr

ENTRY(cpu_arm6_proc_fin)
ENTRY(cpu_arm7_proc_fin)
		mov	r0, #0x31			@ ....S..DP...M
		mcr	p15, 0, r0, c1, c0, 0		@ disable caches
		mov	pc, lr

ENTRY(cpu_arm6_do_idle)
ENTRY(cpu_arm7_do_idle)
		mov	pc, lr

/*
 * Function: arm6_7_switch_mm(unsigned long pgd_phys)
 * Params  : pgd_phys	Physical address of page table
 * Purpose : Perform a task switch, saving the old processes state, and restoring
 *	     the new.
 */
ENTRY(cpu_arm6_switch_mm)
ENTRY(cpu_arm7_switch_mm)
#ifdef CONFIG_MMU
		mov	r1, #0
		mcr	p15, 0, r1, c7, c0, 0		@ flush cache
		mcr	p15, 0, r0, c2, c0, 0		@ update page table ptr
		mcr	p15, 0, r1, c5, c0, 0		@ flush TLBs
#endif
		mov	pc, lr

/*
 * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
 * Params  : r0 = Address to set
 *	   : r1 = value to set
 * Purpose : Set a PTE and flush it out of any WB cache
 */
	.align	5
ENTRY(cpu_arm6_set_pte_ext)
ENTRY(cpu_arm7_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext wc_disable=0
#endif /* CONFIG_MMU */
	mov	pc, lr

/*
 * Function: _arm6_7_reset
 * Params  : r0 = address to jump to
 * Notes   : This sets up everything for a reset
 */
		.pushsection	.idmap.text, "ax"
ENTRY(cpu_arm6_reset)
ENTRY(cpu_arm7_reset)
		mov	r1, #0
		mcr	p15, 0, r1, c7, c0, 0		@ flush cache
#ifdef CONFIG_MMU
		mcr	p15, 0, r1, c5, c0, 0		@ flush TLB
#endif
		mov	r1, #0x30
		mcr	p15, 0, r1, c1, c0, 0		@ turn off MMU etc
		mov	pc, r0
ENDPROC(cpu_arm6_reset)
ENDPROC(cpu_arm7_reset)
		.popsection

		__CPUINIT

		.type	__arm6_setup, #function
__arm6_setup:	mov	r0, #0
		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
#ifdef CONFIG_MMU
		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
		mov	r0, #0x3d			@ . ..RS BLDP WCAM
		orr	r0, r0, #0x100			@ . ..01 0011 1101
#else
		mov	r0, #0x3c			@ . ..RS BLDP WCA.
#endif
		mov	pc, lr
		.size	__arm6_setup, . - __arm6_setup

		.type	__arm7_setup, #function
__arm7_setup:	mov	r0, #0
		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
#ifdef CONFIG_MMU
		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
		mcr	p15, 0, r0, c3, c0		@ load domain access register
		mov	r0, #0x7d			@ . ..RS BLDP WCAM
		orr	r0, r0, #0x100			@ . ..01 0111 1101
#else
		mov	r0, #0x7c			@ . ..RS BLDP WCA.
#endif
		mov	pc, lr
		.size	__arm7_setup, . - __arm7_setup

		__INITDATA

		@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
		define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
		define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort

		.section ".rodata"

		string	cpu_arch_name, "armv3"
		string	cpu_elf_name, "v3"
		string	cpu_arm6_name, "ARM6"
		string	cpu_arm610_name, "ARM610"
		string	cpu_arm7_name, "ARM7"
		string	cpu_arm710_name, "ARM710"

		.align

		.section ".proc.info.init", #alloc, #execinstr

.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
	cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
		.type	__\name\()_proc_info, #object
__\name\()_proc_info:
		.long	\cpu_val
		.long	\cpu_mask
		.long	\cpu_mm_mmu_flags
		.long   PMD_TYPE_SECT | \
			PMD_BIT4 | \
			PMD_SECT_AP_WRITE | \
			PMD_SECT_AP_READ
		b	\cpu_flush
		.long	cpu_arch_name
		.long	cpu_elf_name
		.long	HWCAP_SWP | HWCAP_26BIT
		.long	\cpu_name
		.long	\cpu_proc_funcs
		.long	v3_tlb_fns
		.long	v3_user_fns
		.long	v3_cache_fns
		.size	__\name\()_proc_info, . - __\name\()_proc_info
.endm

	arm67_proc_info	arm6,	0x41560600, 0xfffffff0, cpu_arm6_name, \
		0x00000c1e, __arm6_setup, arm6_processor_functions
	arm67_proc_info	arm610,	0x41560610, 0xfffffff0, cpu_arm610_name, \
		0x00000c1e, __arm6_setup, arm6_processor_functions
	arm67_proc_info	arm7,	0x41007000, 0xffffff00, cpu_arm7_name, \
		0x00000c1e, __arm7_setup, arm7_processor_functions
	arm67_proc_info	arm710,	0x41007100, 0xfff8ff00, cpu_arm710_name, \
			PMD_TYPE_SECT | \
			PMD_SECT_BUFFERABLE | \
			PMD_SECT_CACHEABLE | \
			PMD_BIT4 | \
			PMD_SECT_AP_WRITE | \
			PMD_SECT_AP_READ, \
		__arm7_setup, arm7_processor_functions
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm6,7.S
	3	*
	4	* Copyright (C) 1997-2000 Russell King
d090ddda	5	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* These are the low level assembler for performing cache and TLB
	12	* functions on the ARM610 & ARM710.
	13	*/
	14	#include <linux/linkage.h>
	15	#include <linux/init.h>
	16	#include <asm/assembler.h>
e6ae744d	17	#include <asm/asm-offsets.h>
5ec9407d	18	#include <asm/hwcap.h>
74945c86	19	#include <asm/pgtable-hwdef.h>
1da177e4	20	#include <asm/pgtable.h>
1da177e4 LT	21	#include <asm/ptrace.h>
1da177e4 LT	22
da091653 RK	23	#include "proc-macros.S"
da091653 RK	24
1da177e4 LT	25	ENTRY(cpu_arm6_dcache_clean_area)
	26	ENTRY(cpu_arm7_dcache_clean_area)
	27	mov pc, lr
	28
	29	/*
	30	* Function: arm6_7_data_abort ()
	31	*
da740472 RK	32	* Params : r2 = pt_regs
da740472 RK	33	* : r4 = aborted context pc
3e287bec	34	* : r5 = aborted context psr
1da177e4 LT	35	*
	36	* Purpose : obtain information about current aborted instruction
	37	*
40f0b90a	38	* Returns : r4-r5, r10-r11, r13 preserved
1da177e4 LT	39	*/
	40
	41	ENTRY(cpu_arm7_data_abort)
	42	mrc p15, 0, r1, c5, c0, 0 @ get FSR
	43	mrc p15, 0, r0, c6, c0, 0 @ get FAR
3e287bec	44	ldr r8, [r4] @ read arm instruction
ca6ca91d TB	45	tst r8, #1 << 20 @ L = 0 -> write?
ca6ca91d TB	46	orreq r1, r1, #1 << 11 @ yes.
1da177e4 LT	47	and r7, r8, #15 << 24
	48	add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
	49	nop
	50
	51	/* 0 */ b .data_unknown
da740472	52	/* 1 */ b do_DataAbort @ swp
1da177e4 LT	53	/* 2 */ b .data_unknown
	54	/* 3 */ b .data_unknown
	55	/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
	56	/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
	57	/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
	58	/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
	59	/* 8 / b .data_arm_ldmstm @ ldma rn, <rlist>
	60	/* 9 / b .data_arm_ldmstm @ ldmb rn, <rlist>
	61	/* a */ b .data_unknown
	62	/* b */ b .data_unknown
da740472 RK	63	/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
da740472 RK	64	/* d */ b do_DataAbort @ ldc rd, [rn, #m]
1da177e4 LT	65	/* e */ b .data_unknown
	66	/* f */
	67	.data_unknown: @ Part of jumptable
3e287bec	68	mov r0, r4
1da177e4	69	mov r1, r8
da740472	70	b baddataabort
1da177e4 LT	71
	72	ENTRY(cpu_arm6_data_abort)
	73	mrc p15, 0, r1, c5, c0, 0 @ get FSR
	74	mrc p15, 0, r0, c6, c0, 0 @ get FAR
3e287bec	75	ldr r8, [r4] @ read arm instruction
ca6ca91d TB	76	tst r8, #1 << 20 @ L = 0 -> write?
ca6ca91d TB	77	orreq r1, r1, #1 << 11 @ yes.
1da177e4 LT	78	and r7, r8, #14 << 24
1da177e4 LT	79	teq r7, #8 << 24 @ was it ldm/stm
da740472	80	bne do_DataAbort
1da177e4 LT	81
	82	.data_arm_ldmstm:
	83	tst r8, #1 << 21 @ check writeback bit
da740472	84	beq do_DataAbort @ no writeback -> no fixup
1da177e4 LT	85	mov r7, #0x11
	86	orr r7, r7, #0x1100
	87	and r6, r8, r7
0d147db0 RK	88	and r9, r8, r7, lsl #1
	89	add r6, r6, r9, lsr #1
	90	and r9, r8, r7, lsl #2
	91	add r6, r6, r9, lsr #2
	92	and r9, r8, r7, lsl #3
	93	add r6, r6, r9, lsr #3
1da177e4 LT	94	add r6, r6, r6, lsr #8
	95	add r6, r6, r6, lsr #4
	96	and r6, r6, #15 @ r6 = no. of registers to transfer.
40f0b90a RK	97	and r9, r8, #15 << 16 @ Extract 'n' from instruction
40f0b90a RK	98	ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
1da177e4 LT	99	tst r8, #1 << 23 @ Check U bit
	100	subne r7, r7, r6, lsl #2 @ Undo increment
	101	addeq r7, r7, r6, lsl #2 @ Undo decrement
40f0b90a	102	str r7, [r2, r9, lsr #14] @ Put register 'Rn'
da740472	103	b do_DataAbort
1da177e4 LT	104
1da177e4 LT	105	.data_arm_apply_r6_and_rn:
40f0b90a RK	106	and r9, r8, #15 << 16 @ Extract 'n' from instruction
40f0b90a RK	107	ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
1da177e4 LT	108	tst r8, #1 << 23 @ Check U bit
	109	subne r7, r7, r6 @ Undo incrmenet
	110	addeq r7, r7, r6 @ Undo decrement
40f0b90a	111	str r7, [r2, r9, lsr #14] @ Put register 'Rn'
da740472	112	b do_DataAbort
1da177e4 LT	113
	114	.data_arm_lateldrpreconst:
	115	tst r8, #1 << 21 @ check writeback bit
da740472	116	beq do_DataAbort @ no writeback -> no fixup
1da177e4	117	.data_arm_lateldrpostconst:
108f6af0	118	movs r6, r8, lsl #20 @ Get offset
da740472	119	beq do_DataAbort @ zero -> no fixup
40f0b90a RK	120	and r9, r8, #15 << 16 @ Extract 'n' from instruction
40f0b90a RK	121	ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
1da177e4	122	tst r8, #1 << 23 @ Check U bit
108f6af0 RK	123	subne r7, r7, r6, lsr #20 @ Undo increment
108f6af0 RK	124	addeq r7, r7, r6, lsr #20 @ Undo decrement
40f0b90a	125	str r7, [r2, r9, lsr #14] @ Put register 'Rn'
da740472	126	b do_DataAbort
1da177e4 LT	127
	128	.data_arm_lateldrprereg:
	129	tst r8, #1 << 21 @ check writeback bit
da740472	130	beq do_DataAbort @ no writeback -> no fixup
1da177e4 LT	131	.data_arm_lateldrpostreg:
1da177e4 LT	132	and r7, r8, #15 @ Extract 'm' from instruction
e22c12f9	133	ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
40f0b90a RK	134	mov r9, r8, lsr #7 @ get shift count
40f0b90a RK	135	ands r9, r9, #31
1da177e4 LT	136	and r7, r8, #0x70 @ get shift type
	137	orreq r7, r7, #8 @ shift count = 0
	138	add pc, pc, r7
	139	nop
	140
40f0b90a	141	mov r6, r6, lsl r9 @ 0: LSL #!0
1da177e4 LT	142	b .data_arm_apply_r6_and_rn
	143	b .data_arm_apply_r6_and_rn @ 1: LSL #0
	144	nop
	145	b .data_unknown @ 2: MUL?
	146	nop
	147	b .data_unknown @ 3: MUL?
	148	nop
40f0b90a	149	mov r6, r6, lsr r9 @ 4: LSR #!0
1da177e4 LT	150	b .data_arm_apply_r6_and_rn
	151	mov r6, r6, lsr #32 @ 5: LSR #32
	152	b .data_arm_apply_r6_and_rn
	153	b .data_unknown @ 6: MUL?
	154	nop
	155	b .data_unknown @ 7: MUL?
	156	nop
40f0b90a	157	mov r6, r6, asr r9 @ 8: ASR #!0
1da177e4 LT	158	b .data_arm_apply_r6_and_rn
	159	mov r6, r6, asr #32 @ 9: ASR #32
	160	b .data_arm_apply_r6_and_rn
	161	b .data_unknown @ A: MUL?
	162	nop
	163	b .data_unknown @ B: MUL?
	164	nop
40f0b90a	165	mov r6, r6, ror r9 @ C: ROR #!0
1da177e4 LT	166	b .data_arm_apply_r6_and_rn
	167	mov r6, r6, rrx @ D: RRX
	168	b .data_arm_apply_r6_and_rn
	169	b .data_unknown @ E: MUL?
	170	nop
	171	b .data_unknown @ F: MUL?
	172
	173	/*
	174	* Function: arm6_7_proc_init (void)
	175	* : arm6_7_proc_fin (void)
	176	*
	177	* Notes : This processor does not require these
	178	*/
	179	ENTRY(cpu_arm6_proc_init)
	180	ENTRY(cpu_arm7_proc_init)
	181	mov pc, lr
	182
	183	ENTRY(cpu_arm6_proc_fin)
	184	ENTRY(cpu_arm7_proc_fin)
1da177e4 LT	185	mov r0, #0x31 @ ....S..DP...M
	186	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	187	mov pc, lr
	188
	189	ENTRY(cpu_arm6_do_idle)
	190	ENTRY(cpu_arm7_do_idle)
	191	mov pc, lr
	192
	193	/*
	194	* Function: arm6_7_switch_mm(unsigned long pgd_phys)
	195	* Params : pgd_phys Physical address of page table
	196	* Purpose : Perform a task switch, saving the old processes state, and restoring
	197	* the new.
	198	*/
	199	ENTRY(cpu_arm6_switch_mm)
	200	ENTRY(cpu_arm7_switch_mm)
d090ddda	201	#ifdef CONFIG_MMU
1da177e4 LT	202	mov r1, #0
	203	mcr p15, 0, r1, c7, c0, 0 @ flush cache
	204	mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
	205	mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
d090ddda	206	#endif
1da177e4 LT	207	mov pc, lr
	208
	209	/*
ad1ae2fe	210	* Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
1da177e4 LT	211	* Params : r0 = Address to set
	212	* : r1 = value to set
	213	* Purpose : Set a PTE and flush it out of any WB cache
	214	*/
da091653	215	.align 5
ad1ae2fe RK	216	ENTRY(cpu_arm6_set_pte_ext)
ad1ae2fe RK	217	ENTRY(cpu_arm7_set_pte_ext)
d090ddda	218	#ifdef CONFIG_MMU
da091653	219	armv3_set_pte_ext wc_disable=0
d090ddda	220	#endif /* CONFIG_MMU */
da091653	221	mov pc, lr
1da177e4 LT	222
	223	/*
	224	* Function: _arm6_7_reset
	225	* Params : r0 = address to jump to
	226	* Notes : This sets up everything for a reset
	227	*/
1a4baafa	228	.pushsection .idmap.text, "ax"
1da177e4 LT	229	ENTRY(cpu_arm6_reset)
	230	ENTRY(cpu_arm7_reset)
	231	mov r1, #0
	232	mcr p15, 0, r1, c7, c0, 0 @ flush cache
d090ddda	233	#ifdef CONFIG_MMU
1da177e4	234	mcr p15, 0, r1, c5, c0, 0 @ flush TLB
d090ddda	235	#endif
1da177e4 LT	236	mov r1, #0x30
	237	mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
	238	mov pc, r0
1a4baafa WD	239	ENDPROC(cpu_arm6_reset)
	240	ENDPROC(cpu_arm7_reset)
	241	.popsection
1da177e4	242
5085f3ff	243	__CPUINIT
1da177e4 LT	244
	245	.type __arm6_setup, #function
	246	__arm6_setup: mov r0, #0
	247	mcr p15, 0, r0, c7, c0 @ flush caches on v3
d090ddda	248	#ifdef CONFIG_MMU
1da177e4 LT	249	mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
	250	mov r0, #0x3d @ . ..RS BLDP WCAM
	251	orr r0, r0, #0x100 @ . ..01 0011 1101
d090ddda HC	252	#else
	253	mov r0, #0x3c @ . ..RS BLDP WCA.
	254	#endif
1da177e4 LT	255	mov pc, lr
	256	.size __arm6_setup, . - __arm6_setup
	257
	258	.type __arm7_setup, #function
	259	__arm7_setup: mov r0, #0
	260	mcr p15, 0, r0, c7, c0 @ flush caches on v3
d090ddda	261	#ifdef CONFIG_MMU
1da177e4 LT	262	mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
	263	mcr p15, 0, r0, c3, c0 @ load domain access register
	264	mov r0, #0x7d @ . ..RS BLDP WCAM
	265	orr r0, r0, #0x100 @ . ..01 0111 1101
d090ddda HC	266	#else
	267	mov r0, #0x7c @ . ..RS BLDP WCA.
	268	#endif
1da177e4 LT	269	mov pc, lr
	270	.size __arm7_setup, . - __arm7_setup
	271
	272	__INITDATA
	273
c3be06eb DM	274	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	275	define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
	276	define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort
1da177e4 LT	277
	278	.section ".rodata"
	279
c3be06eb DM	280	string cpu_arch_name, "armv3"
	281	string cpu_elf_name, "v3"
	282	string cpu_arm6_name, "ARM6"
	283	string cpu_arm610_name, "ARM610"
	284	string cpu_arm7_name, "ARM7"
	285	string cpu_arm710_name, "ARM710"
1da177e4 LT	286
	287	.align
	288
02b7dd12	289	.section ".proc.info.init", #alloc, #execinstr
1da177e4	290
c3be06eb DM	291	.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
	292	cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
	293	.type __\name\()_proc_info, #object
	294	__\name\()_proc_info:
	295	.long \cpu_val
	296	.long \cpu_mask
	297	.long \cpu_mm_mmu_flags
8799ee9f RK	298	.long PMD_TYPE_SECT \| \
	299	PMD_BIT4 \| \
	300	PMD_SECT_AP_WRITE \| \
	301	PMD_SECT_AP_READ
c3be06eb	302	b \cpu_flush
1da177e4 LT	303	.long cpu_arch_name
	304	.long cpu_elf_name
	305	.long HWCAP_SWP \| HWCAP_26BIT
c3be06eb DM	306	.long \cpu_name
c3be06eb DM	307	.long \cpu_proc_funcs
1da177e4 LT	308	.long v3_tlb_fns
	309	.long v3_user_fns
	310	.long v3_cache_fns
c3be06eb DM	311	.size __\name\()_proc_info, . - __\name\()_proc_info
	312	.endm
	313
	314	arm67_proc_info arm6, 0x41560600, 0xfffffff0, cpu_arm6_name, \
	315	0x00000c1e, __arm6_setup, arm6_processor_functions
	316	arm67_proc_info arm610, 0x41560610, 0xfffffff0, cpu_arm610_name, \
	317	0x00000c1e, __arm6_setup, arm6_processor_functions
	318	arm67_proc_info arm7, 0x41007000, 0xffffff00, cpu_arm7_name, \
	319	0x00000c1e, __arm7_setup, arm7_processor_functions
	320	arm67_proc_info arm710, 0x41007100, 0xfff8ff00, cpu_arm710_name, \
	321	PMD_TYPE_SECT \| \
1da177e4 LT	322	PMD_SECT_BUFFERABLE \| \
	323	PMD_SECT_CACHEABLE \| \
	324	PMD_BIT4 \| \
	325	PMD_SECT_AP_WRITE \| \
c3be06eb DM	326	PMD_SECT_AP_READ, \
c3be06eb DM	327	__arm7_setup, arm7_processor_functions