[deliverable/linux.git] / arch / arm / mm / proc-arm720.S

/*
 *  linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
 *
 *  Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
 *                     Rob Scott (rscott@mtrob.fdns.net)
 *  Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2004.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the ARM720T.  The ARM720T has a writethrough IDC
 * cache, so we don't need to clean it.
 *
 *  Changelog:
 *   05-09-2000 SJH	Created by moving 720 specific functions
 *			out of 'proc-arm6,7.S' per RMK discussion
 *   07-25-2000 SJH	Added idle function.
 *   08-25-2000	DBS	Updated for integration of ARM Ltd version.
 *   04-20-2004 HSC	modified for non-paged memory management mode.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

/*
 * Function: arm720_proc_init (void)
 *	   : arm720_proc_fin (void)
 *
 * Notes   : This processor does not require these
 */
ENTRY(cpu_arm720_dcache_clean_area)
ENTRY(cpu_arm720_proc_init)
		mov	pc, lr

ENTRY(cpu_arm720_proc_fin)
		mrc	p15, 0, r0, c1, c0, 0
		bic	r0, r0, #0x1000			@ ...i............
		bic	r0, r0, #0x000e			@ ............wca.
		mcr	p15, 0, r0, c1, c0, 0		@ disable caches
		mov	pc, lr

/*
 * Function: arm720_proc_do_idle(void)
 * Params  : r0 = unused
 * Purpose : put the processor in proper idle mode
 */
ENTRY(cpu_arm720_do_idle)
		mov	pc, lr

/*
 * Function: arm720_switch_mm(unsigned long pgd_phys)
 * Params  : pgd_phys	Physical address of page table
 * Purpose : Perform a task switch, saving the old process' state and restoring
 *	     the new.
 */
ENTRY(cpu_arm720_switch_mm)
#ifdef CONFIG_MMU
		mov	r1, #0
		mcr	p15, 0, r1, c7, c7, 0		@ invalidate cache
		mcr	p15, 0, r0, c2, c0, 0		@ update page table ptr
		mcr	p15, 0, r1, c8, c7, 0		@ flush TLB (v4)
#endif
		mov	pc, lr

/*
 * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
 * Params  : r0 = Address to set
 *	   : r1 = value to set
 * Purpose : Set a PTE and flush it out of any WB cache
 */
	.align	5
ENTRY(cpu_arm720_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext wc_disable=0
#endif
	mov	pc, lr

/*
 * Function: arm720_reset
 * Params  : r0 = address to jump to
 * Notes   : This sets up everything for a reset
 */
		.pushsection	.idmap.text, "ax"
ENTRY(cpu_arm720_reset)
		mov	ip, #0
		mcr	p15, 0, ip, c7, c7, 0		@ invalidate cache
#ifdef CONFIG_MMU
		mcr	p15, 0, ip, c8, c7, 0		@ flush TLB (v4)
#endif
		mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
		bic	ip, ip, #0x000f			@ ............wcam
		bic	ip, ip, #0x2100			@ ..v....s........
		mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
		mov	pc, r0
ENDPROC(cpu_arm720_reset)
		.popsection

	__CPUINIT

	.type	__arm710_setup, #function
__arm710_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
#endif
	mrc	p15, 0, r0, c1, c0		@ get control register
	ldr	r5, arm710_cr1_clear
	bic	r0, r0, r5
	ldr	r5, arm710_cr1_set
	orr	r0, r0, r5
	mov	pc, lr				@ __ret (head.S)
	.size	__arm710_setup, . - __arm710_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .... 0001 ..11 1101
	 * 
	 */
	.type	arm710_cr1_clear, #object
	.type	arm710_cr1_set, #object
arm710_cr1_clear:
	.word	0x0f3f
arm710_cr1_set:
	.word	0x013d

	.type	__arm720_setup, #function
__arm720_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
#endif
	adr	r5, arm720_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register
	bic	r0, r0, r5
	orr	r0, r0, r6
	mov	pc, lr				@ __ret (head.S)
	.size	__arm720_setup, . - __arm720_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * ..1. 1001 ..11 1101
	 * 
	 */
	.type	arm720_crval, #object
arm720_crval:
	crval	clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130

		__INITDATA
	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm720, dabort=v4t_late_abort, pabort=legacy_pabort

		.section ".rodata"

	string	cpu_arch_name, "armv4t"
	string	cpu_elf_name, "v4"
	string	cpu_arm710_name, "ARM710T"
	string	cpu_arm720_name, "ARM720T"

		.align

/*
 * See <asm/procinfo.h> for a definition of this structure.
 */
	
		.section ".proc.info.init", #alloc, #execinstr

.macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
		.type	__\name\()_proc_info,#object
__\name\()_proc_info:
		.long	\cpu_val
		.long	\cpu_mask
		.long   PMD_TYPE_SECT | \
			PMD_SECT_BUFFERABLE | \
			PMD_SECT_CACHEABLE | \
			PMD_BIT4 | \
			PMD_SECT_AP_WRITE | \
			PMD_SECT_AP_READ
		.long   PMD_TYPE_SECT | \
			PMD_BIT4 | \
			PMD_SECT_AP_WRITE | \
			PMD_SECT_AP_READ
		b	\cpu_flush				@ cpu_flush
		.long	cpu_arch_name				@ arch_name
		.long	cpu_elf_name				@ elf_name
		.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB	@ elf_hwcap
		.long	\cpu_name
		.long	arm720_processor_functions
		.long	v4_tlb_fns
		.long	v4wt_user_fns
		.long	v4_cache_fns
		.size	__\name\()_proc_info, . - __\name\()_proc_info
.endm

	arm720_proc_info arm710, 0x41807100, 0xffffff00, cpu_arm710_name, __arm710_setup
	arm720_proc_info arm720, 0x41807200, 0xffffff00, cpu_arm720_name, __arm720_setup
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
	3	*
	4	* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
	5	* Rob Scott (rscott@mtrob.fdns.net)
	6	* Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
d090ddda	7	* hacked for non-paged-MM by Hyok S. Choi, 2004.
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	*
	24	* These are the low level assembler for performing cache and TLB
	25	* functions on the ARM720T. The ARM720T has a writethrough IDC
	26	* cache, so we don't need to clean it.
	27	*
	28	* Changelog:
	29	* 05-09-2000 SJH Created by moving 720 specific functions
	30	* out of 'proc-arm6,7.S' per RMK discussion
	31	* 07-25-2000 SJH Added idle function.
	32	* 08-25-2000 DBS Updated for integration of ARM Ltd version.
d090ddda	33	* 04-20-2004 HSC modified for non-paged memory management mode.
1da177e4 LT	34	*/
	35	#include <linux/linkage.h>
	36	#include <linux/init.h>
	37	#include <asm/assembler.h>
e6ae744d	38	#include <asm/asm-offsets.h>
5ec9407d	39	#include <asm/hwcap.h>
74945c86	40	#include <asm/pgtable-hwdef.h>
1da177e4	41	#include <asm/pgtable.h>
1da177e4	42	#include <asm/ptrace.h>
1da177e4	43
bb8d5a55 TG	44	#include "proc-macros.S"
bb8d5a55 TG	45
1da177e4 LT	46	/*
	47	* Function: arm720_proc_init (void)
	48	* : arm720_proc_fin (void)
	49	*
	50	* Notes : This processor does not require these
	51	*/
	52	ENTRY(cpu_arm720_dcache_clean_area)
	53	ENTRY(cpu_arm720_proc_init)
	54	mov pc, lr
	55
	56	ENTRY(cpu_arm720_proc_fin)
1da177e4 LT	57	mrc p15, 0, r0, c1, c0, 0
	58	bic r0, r0, #0x1000 @ ...i............
	59	bic r0, r0, #0x000e @ ............wca.
	60	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	61	mov pc, lr
1da177e4 LT	62
	63	/*
	64	* Function: arm720_proc_do_idle(void)
	65	* Params : r0 = unused
25985edc	66	* Purpose : put the processor in proper idle mode
1da177e4 LT	67	*/
	68	ENTRY(cpu_arm720_do_idle)
	69	mov pc, lr
	70
	71	/*
	72	* Function: arm720_switch_mm(unsigned long pgd_phys)
	73	* Params : pgd_phys Physical address of page table
	74	* Purpose : Perform a task switch, saving the old process' state and restoring
	75	* the new.
	76	*/
	77	ENTRY(cpu_arm720_switch_mm)
d090ddda	78	#ifdef CONFIG_MMU
1da177e4 LT	79	mov r1, #0
	80	mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
	81	mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
	82	mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
d090ddda	83	#endif
1da177e4 LT	84	mov pc, lr
	85
	86	/*
ad1ae2fe	87	* Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
1da177e4 LT	88	* Params : r0 = Address to set
	89	* : r1 = value to set
	90	* Purpose : Set a PTE and flush it out of any WB cache
	91	*/
da091653	92	.align 5
ad1ae2fe	93	ENTRY(cpu_arm720_set_pte_ext)
d090ddda	94	#ifdef CONFIG_MMU
da091653	95	armv3_set_pte_ext wc_disable=0
d090ddda	96	#endif
da091653	97	mov pc, lr
1da177e4 LT	98
	99	/*
	100	* Function: arm720_reset
	101	* Params : r0 = address to jump to
	102	* Notes : This sets up everything for a reset
	103	*/
1a4baafa	104	.pushsection .idmap.text, "ax"
1da177e4 LT	105	ENTRY(cpu_arm720_reset)
	106	mov ip, #0
	107	mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
d090ddda	108	#ifdef CONFIG_MMU
1da177e4	109	mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
d090ddda	110	#endif
1da177e4 LT	111	mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
	112	bic ip, ip, #0x000f @ ............wcam
	113	bic ip, ip, #0x2100 @ ..v....s........
	114	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	115	mov pc, r0
1a4baafa WD	116	ENDPROC(cpu_arm720_reset)
1a4baafa WD	117	.popsection
1da177e4	118
5085f3ff	119	__CPUINIT
1da177e4 LT	120
	121	.type __arm710_setup, #function
	122	__arm710_setup:
	123	mov r0, #0
	124	mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
d090ddda	125	#ifdef CONFIG_MMU
1da177e4	126	mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
d090ddda	127	#endif
1da177e4 LT	128	mrc p15, 0, r0, c1, c0 @ get control register
	129	ldr r5, arm710_cr1_clear
	130	bic r0, r0, r5
	131	ldr r5, arm710_cr1_set
	132	orr r0, r0, r5
	133	mov pc, lr @ __ret (head.S)
	134	.size __arm710_setup, . - __arm710_setup
	135
	136	/*
	137	* R
	138	* .RVI ZFRS BLDP WCAM
	139	* .... 0001 ..11 1101
	140	*
	141	*/
	142	.type arm710_cr1_clear, #object
	143	.type arm710_cr1_set, #object
	144	arm710_cr1_clear:
	145	.word 0x0f3f
	146	arm710_cr1_set:
	147	.word 0x013d
	148
	149	.type __arm720_setup, #function
	150	__arm720_setup:
	151	mov r0, #0
	152	mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
d090ddda	153	#ifdef CONFIG_MMU
1da177e4	154	mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
d090ddda	155	#endif
22b19086 RK	156	adr r5, arm720_crval
22b19086 RK	157	ldmia r5, {r5, r6}
1da177e4	158	mrc p15, 0, r0, c1, c0 @ get control register
1da177e4	159	bic r0, r0, r5
22b19086	160	orr r0, r0, r6
1da177e4 LT	161	mov pc, lr @ __ret (head.S)
	162	.size __arm720_setup, . - __arm720_setup
	163
	164	/*
	165	* R
	166	* .RVI ZFRS BLDP WCAM
	167	* ..1. 1001 ..11 1101
	168	*
	169	*/
22b19086 RK	170	.type arm720_crval, #object
	171	arm720_crval:
	172	crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
1da177e4 LT	173
1da177e4 LT	174	__INITDATA
449870b1 DM	175	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
449870b1 DM	176	define_processor_functions arm720, dabort=v4t_late_abort, pabort=legacy_pabort
1da177e4 LT	177
	178	.section ".rodata"
	179
449870b1 DM	180	string cpu_arch_name, "armv4t"
	181	string cpu_elf_name, "v4"
	182	string cpu_arm710_name, "ARM710T"
	183	string cpu_arm720_name, "ARM720T"
1da177e4 LT	184
	185	.align
	186
	187	/*
4baa9922	188	* See <asm/procinfo.h> for a definition of this structure.
1da177e4 LT	189	*/
1da177e4 LT	190
02b7dd12	191	.section ".proc.info.init", #alloc, #execinstr
1da177e4	192
449870b1 DM	193	.macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
	194	.type __\name\()_proc_info,#object
	195	__\name\()_proc_info:
	196	.long \cpu_val
	197	.long \cpu_mask
1da177e4 LT	198	.long PMD_TYPE_SECT \| \
	199	PMD_SECT_BUFFERABLE \| \
	200	PMD_SECT_CACHEABLE \| \
	201	PMD_BIT4 \| \
	202	PMD_SECT_AP_WRITE \| \
	203	PMD_SECT_AP_READ
8799ee9f RK	204	.long PMD_TYPE_SECT \| \
	205	PMD_BIT4 \| \
	206	PMD_SECT_AP_WRITE \| \
	207	PMD_SECT_AP_READ
449870b1	208	b \cpu_flush @ cpu_flush
1da177e4 LT	209	.long cpu_arch_name @ arch_name
	210	.long cpu_elf_name @ elf_name
	211	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB @ elf_hwcap
449870b1	212	.long \cpu_name
1da177e4 LT	213	.long arm720_processor_functions
	214	.long v4_tlb_fns
	215	.long v4wt_user_fns
	216	.long v4_cache_fns
449870b1 DM	217	.size __\name\()_proc_info, . - __\name\()_proc_info
449870b1 DM	218	.endm
1da177e4	219
449870b1 DM	220	arm720_proc_info arm710, 0x41807100, 0xffffff00, cpu_arm710_name, __arm710_setup
449870b1 DM	221	arm720_proc_info arm720, 0x41807200, 0xffffff00, cpu_arm720_name, __arm720_setup