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b731c311 HC |
1 | /* |
2 | * linux/arch/arm/mm/arm740.S: utility functions for ARM740 | |
3 | * | |
4 | * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | #include <linux/linkage.h> | |
12 | #include <linux/init.h> | |
13 | #include <asm/assembler.h> | |
14 | #include <asm/asm-offsets.h> | |
5ec9407d | 15 | #include <asm/hwcap.h> |
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16 | #include <asm/pgtable-hwdef.h> |
17 | #include <asm/pgtable.h> | |
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18 | #include <asm/ptrace.h> |
19 | ||
4cc1f0fa DM |
20 | #include "proc-macros.S" |
21 | ||
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22 | .text |
23 | /* | |
24 | * cpu_arm740_proc_init() | |
25 | * cpu_arm740_do_idle() | |
26 | * cpu_arm740_dcache_clean_area() | |
27 | * cpu_arm740_switch_mm() | |
28 | * | |
29 | * These are not required. | |
30 | */ | |
31 | ENTRY(cpu_arm740_proc_init) | |
32 | ENTRY(cpu_arm740_do_idle) | |
33 | ENTRY(cpu_arm740_dcache_clean_area) | |
34 | ENTRY(cpu_arm740_switch_mm) | |
35 | mov pc, lr | |
36 | ||
37 | /* | |
38 | * cpu_arm740_proc_fin() | |
39 | */ | |
40 | ENTRY(cpu_arm740_proc_fin) | |
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41 | mrc p15, 0, r0, c1, c0, 0 |
42 | bic r0, r0, #0x3f000000 @ bank/f/lock/s | |
43 | bic r0, r0, #0x0000000c @ w-buffer/cache | |
44 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 45 | mov pc, lr |
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46 | |
47 | /* | |
48 | * cpu_arm740_reset(loc) | |
49 | * Params : r0 = address to jump to | |
50 | * Notes : This sets up everything for a reset | |
51 | */ | |
1a4baafa | 52 | .pushsection .idmap.text, "ax" |
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53 | ENTRY(cpu_arm740_reset) |
54 | mov ip, #0 | |
55 | mcr p15, 0, ip, c7, c0, 0 @ invalidate cache | |
56 | mrc p15, 0, ip, c1, c0, 0 @ get ctrl register | |
57 | bic ip, ip, #0x0000000c @ ............wc.. | |
58 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
59 | mov pc, r0 | |
1a4baafa WD |
60 | ENDPROC(cpu_arm740_reset) |
61 | .popsection | |
b731c311 | 62 | |
5085f3ff | 63 | __CPUINIT |
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64 | |
65 | .type __arm740_setup, #function | |
66 | __arm740_setup: | |
67 | mov r0, #0 | |
68 | mcr p15, 0, r0, c7, c0, 0 @ invalidate caches | |
69 | ||
70 | mcr p15, 0, r0, c6, c3 @ disable area 3~7 | |
71 | mcr p15, 0, r0, c6, c4 | |
72 | mcr p15, 0, r0, c6, c5 | |
73 | mcr p15, 0, r0, c6, c6 | |
74 | mcr p15, 0, r0, c6, c7 | |
75 | ||
76 | mov r0, #0x0000003F @ base = 0, size = 4GB | |
77 | mcr p15, 0, r0, c6, c0 @ set area 0, default | |
78 | ||
79 | ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM | |
3ef52f2a WD |
80 | ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB) |
81 | mov r4, #10 @ 11 is the minimum (4KB) | |
82 | 1: add r4, r4, #1 @ area size *= 2 | |
83 | movs r3, r3, lsr #1 | |
b731c311 | 84 | bne 1b @ count not zero r-shift |
3ef52f2a | 85 | orr r0, r0, r4, lsl #1 @ the area register value |
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86 | orr r0, r0, #1 @ set enable bit |
87 | mcr p15, 0, r0, c6, c1 @ set area 1, RAM | |
88 | ||
89 | ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH | |
3ef52f2a WD |
90 | ldr r3, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB) |
91 | cmp r3, #0 | |
92 | moveq r0, #0 | |
93 | beq 2f | |
94 | mov r4, #10 @ 11 is the minimum (4KB) | |
95 | 1: add r4, r4, #1 @ area size *= 2 | |
96 | movs r3, r3, lsr #1 | |
b731c311 | 97 | bne 1b @ count not zero r-shift |
3ef52f2a | 98 | orr r0, r0, r4, lsl #1 @ the area register value |
b731c311 | 99 | orr r0, r0, #1 @ set enable bit |
3ef52f2a | 100 | 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH |
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101 | |
102 | mov r0, #0x06 | |
103 | mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable | |
104 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
105 | mov r0, #0x00 @ disable whole write buffer | |
106 | #else | |
107 | mov r0, #0x02 @ Region 1 write bufferred | |
108 | #endif | |
109 | mcr p15, 0, r0, c3, c0 | |
110 | ||
111 | mov r0, #0x10000 | |
112 | sub r0, r0, #1 @ r0 = 0xffff | |
113 | mcr p15, 0, r0, c5, c0 @ all read/write access | |
114 | ||
115 | mrc p15, 0, r0, c1, c0 @ get control register | |
116 | bic r0, r0, #0x3F000000 @ set to standard caching mode | |
117 | @ need some benchmark | |
118 | orr r0, r0, #0x0000000d @ MPU/Cache/WB | |
119 | ||
120 | mov pc, lr | |
121 | ||
122 | .size __arm740_setup, . - __arm740_setup | |
123 | ||
124 | __INITDATA | |
125 | ||
4cc1f0fa DM |
126 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
127 | define_processor_functions arm740, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1 | |
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128 | |
129 | .section ".rodata" | |
130 | ||
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131 | string cpu_arch_name, "armv4" |
132 | string cpu_elf_name, "v4" | |
133 | string cpu_arm740_name, "ARM740T" | |
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134 | |
135 | .align | |
136 | ||
137 | .section ".proc.info.init", #alloc, #execinstr | |
138 | .type __arm740_proc_info,#object | |
139 | __arm740_proc_info: | |
140 | .long 0x41807400 | |
141 | .long 0xfffffff0 | |
142 | .long 0 | |
3ef52f2a | 143 | .long 0 |
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144 | b __arm740_setup |
145 | .long cpu_arch_name | |
146 | .long cpu_elf_name | |
3ef52f2a | 147 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_26BIT |
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148 | .long cpu_arm740_name |
149 | .long arm740_processor_functions | |
150 | .long 0 | |
151 | .long 0 | |
82d9b0d0 | 152 | .long v4_cache_fns @ cache model |
b731c311 | 153 | .size __arm740_proc_info, . - __arm740_proc_info |