[deliverable/linux.git] / arch / arm / mm / proc-arm925.S

/*
 *  linux/arch/arm/mm/arm925.S: MMU functions for ARM925
 *
 *  Copyright (C) 1999,2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  Copyright (C) 2002 RidgeRun, Inc.
 *  Copyright (C) 2002-2003 MontaVista Software, Inc.
 *
 *  Update for Linux-2.6 and cache flush improvements
 *  Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
 *
 *  hacked for non-paged-MM by Hyok S. Choi, 2004.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm925.
 *
 *  CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
 *
 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
 *
 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
 *	  entry mode" must be 0 to flush the entries in both segments
 *	  at once. This is the default value. See TRM 2-20 and 2-24 for
 *	  more information.
 *
 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
 *	  like the "Transparent mode" must be on for partial cache flushes
 *	  to work in this mode. This mode only works with 16-bit external
 *	  memory. See TRM 2-24 for more information.
 *
 * NOTE3: Write-back cache flushing seems to be flakey with devices using
 *        direct memory access, such as USB OHCI. The workaround is to use
 *        write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
 *        the default for OMAP-1510).
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	16

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	2

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	256

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintenance instructions.
 */
#define CACHE_DLIMIT	8192

	.text
/*
 * cpu_arm925_proc_init()
 */
ENTRY(cpu_arm925_proc_init)
	mov	pc, lr

/*
 * cpu_arm925_proc_fin()
 */
ENTRY(cpu_arm925_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_arm925_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm925_reset)
	/* Send software reset to MPU and DSP */
	mov	ip, #0xff000000
	orr	ip, ip, #0x00fe0000
	orr	ip, ip, #0x0000ce00
	mov	r4, #1
	strh	r4, [ip, #0x10]

	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm925_do_idle()
 *
 * Called with IRQs disabled
 */
	.align	10
ENTRY(cpu_arm925_do_idle)
	mov	r0, #0
	mrc	p15, 0, r1, c1, c0, 0		@ Read control register
	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
	bic	r2, r1, #1 << 12
	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mcr	p15, 0, r1, c1, c0, 0		@ Restore ICache enable
	mov	pc, lr

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(arm925_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mov	pc, lr
ENDPROC(arm925_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Clean and invalidate all cache entries in a particular
 *	address space.
 */
ENTRY(arm925_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm925_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
	/* Flush entries in both segments at once, see NOTE1 above */
	mov	r3, #(CACHE_DENTRIES - 1) << 4	@ 256 entries in segment
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	subs	r3, r3, #1 << 4
	bcs	2b				@ entries 255 to 0
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
ENTRY(arm925_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bgt	__flush_whole_cache
1:	tst	r2, #VM_EXEC
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#else
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#endif
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm925_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm925_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(arm925_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm925_dma_inv_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
#endif
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm925_dma_clean_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm925_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
#else
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm925_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm925_dma_clean_range
	bcs	arm925_dma_inv_range
	b	arm925_dma_flush_range
ENDPROC(arm925_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm925_dma_unmap_area)
	mov	pc, lr
ENDPROC(arm925_dma_unmap_area)

	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
	define_cache_functions arm925

ENTRY(cpu_arm925_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm925_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm925_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
	/* Flush entries in bothe segments at once, see NOTE1 above */
	mov	r3, #(CACHE_DENTRIES - 1) << 4	@ 256 entries in segment
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
	subs	r3, r3, #1 << 4
	bcs	2b				@ entries 255 to 0
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mov	pc, lr

/*
 * cpu_arm925_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm925_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif /* CONFIG_MMU */
	mov	pc, lr

	__CPUINIT

	.type	__arm925_setup, #function
__arm925_setup:
	mov	r0, #0
#if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
        orr     r0,r0,#1 << 7
#endif

	/* Transparent on, D-cache clean & flush mode. See  NOTE2 above */
        orr     r0,r0,#1 << 1			@ transparent mode on
        mcr     p15, 0, r0, c15, c1, 0          @ write TI config register

	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #4				@ disable write-back on caches explicitly
	mcr	p15, 7, r0, c15, c0, 0
#endif

	adr	r5, arm925_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000			@ .1.. .... .... ....
#endif
	mov	pc, lr
	.size	__arm925_setup, . - __arm925_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 0001 ..11 1101
	 * 
	 */
	.type	arm925_crval, #object
arm925_crval:
	crval	clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130

	__INITDATA
	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm925, dabort=v4t_early_abort, pabort=legacy_pabort

	.section ".rodata"

	string	cpu_arch_name, "armv4t"
	string	cpu_elf_name, "v4"
	string	cpu_arm925_name, "ARM925T"

	.align

	.section ".proc.info.init", #alloc, #execinstr

.macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
	.type	__\name\()_proc_info,#object
__\name\()_proc_info:
	.long	\cpu_val
	.long	\cpu_mask
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm925_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm925_name
	.long	arm925_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm925_cache_fns
	.size	__\name\()_proc_info, . - __\name\()_proc_info
.endm

	arm925_proc_info arm925, 0x54029250, 0xfffffff0, cpu_arm925_name
	arm925_proc_info arm915, 0x54029150, 0xfffffff0, cpu_arm925_name
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/arm925.S: MMU functions for ARM925
	3	*
	4	* Copyright (C) 1999,2000 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	6	* Copyright (C) 2002 RidgeRun, Inc.
	7	* Copyright (C) 2002-2003 MontaVista Software, Inc.
	8	*
	9	* Update for Linux-2.6 and cache flush improvements
	10	* Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
	11	*
d090ddda HC	12	* hacked for non-paged-MM by Hyok S. Choi, 2004.
d090ddda HC	13	*
1da177e4 LT	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	27	*
	28	*
	29	* These are the low level assembler for performing cache and TLB
	30	* functions on the arm925.
	31	*
	32	* CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
	33	*
	34	* Some additional notes based on deciphering the TI TRM on OMAP-5910:
	35	*
	36	* NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
	37	* entry mode" must be 0 to flush the entries in both segments
	38	* at once. This is the default value. See TRM 2-20 and 2-24 for
	39	* more information.
	40	*
	41	* NOTE2: Default is the "D-cache clean and flush entry mode". It looks
	42	* like the "Transparent mode" must be on for partial cache flushes
	43	* to work in this mode. This mode only works with 16-bit external
	44	* memory. See TRM 2-24 for more information.
	45	*
	46	* NOTE3: Write-back cache flushing seems to be flakey with devices using
	47	* direct memory access, such as USB OHCI. The workaround is to use
	48	* write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
	49	* the default for OMAP-1510).
	50	*/
	51
	52	#include <linux/linkage.h>
1da177e4 LT	53	#include <linux/init.h>
1da177e4 LT	54	#include <asm/assembler.h>
5ec9407d	55	#include <asm/hwcap.h>
74945c86	56	#include <asm/pgtable-hwdef.h>
1da177e4	57	#include <asm/pgtable.h>
1da177e4 LT	58	#include <asm/page.h>
	59	#include <asm/ptrace.h>
	60	#include "proc-macros.S"
	61
	62	/*
	63	* The size of one data cache line.
	64	*/
	65	#define CACHE_DLINESIZE 16
	66
	67	/*
	68	* The number of data cache segments.
	69	*/
	70	#define CACHE_DSEGMENTS 2
	71
	72	/*
	73	* The number of lines in a cache segment.
	74	*/
	75	#define CACHE_DENTRIES 256
	76
	77	/*
	78	* This is the size at which it becomes more efficient to
	79	* clean the whole cache, rather than using the individual
25985edc	80	* cache line maintenance instructions.
1da177e4 LT	81	*/
	82	#define CACHE_DLIMIT 8192
	83
	84	.text
	85	/*
	86	* cpu_arm925_proc_init()
	87	*/
	88	ENTRY(cpu_arm925_proc_init)
	89	mov pc, lr
	90
	91	/*
	92	* cpu_arm925_proc_fin()
	93	*/
	94	ENTRY(cpu_arm925_proc_fin)
1da177e4 LT	95	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	96	bic r0, r0, #0x1000 @ ...i............
	97	bic r0, r0, #0x000e @ ............wca.
	98	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	99	mov pc, lr
1da177e4 LT	100
	101	/*
	102	* cpu_arm925_reset(loc)
	103	*
	104	* Perform a soft reset of the system. Put the CPU into the
	105	* same state as it would be if it had been reset, and branch
	106	* to what would be the reset vector.
	107	*
	108	* loc: location to jump to for soft reset
	109	*/
	110	.align 5
	111	ENTRY(cpu_arm925_reset)
	112	/* Send software reset to MPU and DSP */
	113	mov ip, #0xff000000
	114	orr ip, ip, #0x00fe0000
	115	orr ip, ip, #0x0000ce00
	116	mov r4, #1
	117	strh r4, [ip, #0x10]
	118
	119	mov ip, #0
	120	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	121	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	122	#ifdef CONFIG_MMU
1da177e4	123	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	124	#endif
1da177e4 LT	125	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	126	bic ip, ip, #0x000f @ ............wcam
	127	bic ip, ip, #0x1100 @ ...i...s........
	128	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	129	mov pc, r0
	130
	131	/*
	132	* cpu_arm925_do_idle()
	133	*
	134	* Called with IRQs disabled
	135	*/
	136	.align 10
	137	ENTRY(cpu_arm925_do_idle)
	138	mov r0, #0
	139	mrc p15, 0, r1, c1, c0, 0 @ Read control register
	140	mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
	141	bic r2, r1, #1 << 12
	142	mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
	143	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	144	mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
	145	mov pc, lr
	146
c8c90860 MW	147	/*
	148	* flush_icache_all()
	149	*
	150	* Unconditionally clean and invalidate the entire icache.
	151	*/
	152	ENTRY(arm925_flush_icache_all)
	153	mov r0, #0
	154	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	155	mov pc, lr
	156	ENDPROC(arm925_flush_icache_all)
	157
1da177e4 LT	158	/*
	159	* flush_user_cache_all()
	160	*
	161	* Clean and invalidate all cache entries in a particular
	162	* address space.
	163	*/
	164	ENTRY(arm925_flush_user_cache_all)
	165	/* FALLTHROUGH */
	166
	167	/*
	168	* flush_kern_cache_all()
	169	*
	170	* Clean and invalidate the entire cache.
	171	*/
	172	ENTRY(arm925_flush_kern_cache_all)
	173	mov r2, #VM_EXEC
	174	mov ip, #0
	175	__flush_whole_cache:
	176	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	177	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	178	#else
	179	/* Flush entries in both segments at once, see NOTE1 above */
	180	mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
	181	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	182	subs r3, r3, #1 << 4
	183	bcs 2b @ entries 255 to 0
	184	#endif
	185	tst r2, #VM_EXEC
	186	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	187	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	188	mov pc, lr
	189
	190	/*
	191	* flush_user_cache_range(start, end, flags)
	192	*
	193	* Clean and invalidate a range of cache entries in the
	194	* specified address range.
	195	*
	196	* - start - start address (inclusive)
	197	* - end - end address (exclusive)
	198	* - flags - vm_flags describing address space
	199	*/
	200	ENTRY(arm925_flush_user_cache_range)
	201	mov ip, #0
	202	sub r3, r1, r0 @ calculate total size
	203	cmp r3, #CACHE_DLIMIT
	204	bgt __flush_whole_cache
	205	1: tst r2, #VM_EXEC
	206	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	207	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	208	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	209	add r0, r0, #CACHE_DLINESIZE
	210	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	211	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	212	add r0, r0, #CACHE_DLINESIZE
	213	#else
	214	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	215	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	216	add r0, r0, #CACHE_DLINESIZE
	217	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	218	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	219	add r0, r0, #CACHE_DLINESIZE
	220	#endif
	221	cmp r0, r1
222	blo 1b
223	tst r2, #VM_EXEC
224	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
225	mov pc, lr
226
227	/*
228	* coherent_kern_range(start, end)
229	*
230	* Ensure coherency between the Icache and the Dcache in the
231	* region described by start, end. If you have non-snooping
232	* Harvard caches, you need to implement this function.
233	*
234	* - start - virtual start address
235	* - end - virtual end address
236	*/
237	ENTRY(arm925_coherent_kern_range)
238	/* FALLTHROUGH */
239
240	/*
241	* coherent_user_range(start, end)
242	*
243	* Ensure coherency between the Icache and the Dcache in the
244	* region described by start, end. If you have non-snooping
245	* Harvard caches, you need to implement this function.
246	*
247	* - start - virtual start address
248	* - end - virtual end address
249	*/
250	ENTRY(arm925_coherent_user_range)
251	bic r0, r0, #CACHE_DLINESIZE - 1
252	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
253	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
254	add r0, r0, #CACHE_DLINESIZE
255	cmp r0, r1
256	blo 1b
257	mcr p15, 0, r0, c7, c10, 4 @ drain WB
258	mov pc, lr
259
260	/*
2c9b9c84	261	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	262	*
	263	* Ensure no D cache aliasing occurs, either with itself or
	264	* the I cache
	265	*
2c9b9c84 RK	266	* - addr - kernel address
2c9b9c84 RK	267	* - size - region size
1da177e4	268	*/
2c9b9c84 RK	269	ENTRY(arm925_flush_kern_dcache_area)
2c9b9c84 RK	270	add r1, r0, r1
1da177e4 LT	271	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	272	add r0, r0, #CACHE_DLINESIZE
	273	cmp r0, r1
	274	blo 1b
	275	mov r0, #0
	276	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	277	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	278	mov pc, lr
	279
	280	/*
	281	* dma_inv_range(start, end)
	282	*
	283	* Invalidate (discard) the specified virtual address range.
	284	* May not write back any entries. If 'start' or 'end'
	285	* are not cache line aligned, those lines must be written
	286	* back.
	287	*
	288	* - start - virtual start address
	289	* - end - virtual end address
	290	*
	291	* (same as v4wb)
	292	*/
702b94bf	293	arm925_dma_inv_range:
1da177e4 LT	294	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	295	tst r0, #CACHE_DLINESIZE - 1
	296	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	297	tst r1, #CACHE_DLINESIZE - 1
	298	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	299	#endif
	300	bic r0, r0, #CACHE_DLINESIZE - 1
	301	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	302	add r0, r0, #CACHE_DLINESIZE
	303	cmp r0, r1
	304	blo 1b
	305	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	306	mov pc, lr
	307
	308	/*
	309	* dma_clean_range(start, end)
	310	*
	311	* Clean the specified virtual address range.
	312	*
	313	* - start - virtual start address
	314	* - end - virtual end address
	315	*
	316	* (same as v4wb)
	317	*/
702b94bf	318	arm925_dma_clean_range:
1da177e4 LT	319	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	320	bic r0, r0, #CACHE_DLINESIZE - 1
	321	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	322	add r0, r0, #CACHE_DLINESIZE
	323	cmp r0, r1
	324	blo 1b
	325	#endif
	326	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	327	mov pc, lr
	328
	329	/*
	330	* dma_flush_range(start, end)
	331	*
	332	* Clean and invalidate the specified virtual address range.
	333	*
	334	* - start - virtual start address
	335	* - end - virtual end address
	336	*/
	337	ENTRY(arm925_dma_flush_range)
	338	bic r0, r0, #CACHE_DLINESIZE - 1
	339	1:
	340	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	341	mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	342	#else
b3a8b751	343	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
1da177e4 LT	344	#endif
	345	add r0, r0, #CACHE_DLINESIZE
	346	cmp r0, r1
	347	blo 1b
	348	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	349	mov pc, lr
	350
a9c9147e RK	351	/*
	352	* dma_map_area(start, size, dir)
	353	* - start - kernel virtual start address
	354	* - size - size of region
	355	* - dir - DMA direction
	356	*/
	357	ENTRY(arm925_dma_map_area)
	358	add r1, r1, r0
	359	cmp r2, #DMA_TO_DEVICE
	360	beq arm925_dma_clean_range
	361	bcs arm925_dma_inv_range
	362	b arm925_dma_flush_range
	363	ENDPROC(arm925_dma_map_area)
	364
	365	/*
	366	* dma_unmap_area(start, size, dir)
	367	* - start - kernel virtual start address
	368	* - size - size of region
	369	* - dir - DMA direction
	370	*/
	371	ENTRY(arm925_dma_unmap_area)
	372	mov pc, lr
	373	ENDPROC(arm925_dma_unmap_area)
	374
6c240aec DM	375	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
6c240aec DM	376	define_cache_functions arm925
1da177e4 LT	377
	378	ENTRY(cpu_arm925_dcache_clean_area)
	379	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	380	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	381	add r0, r0, #CACHE_DLINESIZE
	382	subs r1, r1, #CACHE_DLINESIZE
	383	bhi 1b
	384	#endif
	385	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	386	mov pc, lr
	387
	388	/* =============================== PageTable ============================== */
	389
	390	/*
	391	* cpu_arm925_switch_mm(pgd)
	392	*
	393	* Set the translation base pointer to be as described by pgd.
	394	*
	395	* pgd: new page tables
	396	*/
	397	.align 5
	398	ENTRY(cpu_arm925_switch_mm)
d090ddda	399	#ifdef CONFIG_MMU
1da177e4 LT	400	mov ip, #0
	401	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	402	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	403	#else
	404	/* Flush entries in bothe segments at once, see NOTE1 above */
	405	mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
	406	2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
	407	subs r3, r3, #1 << 4
	408	bcs 2b @ entries 255 to 0
	409	#endif
	410	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	411	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	412	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	413	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	414	#endif
1da177e4 LT	415	mov pc, lr
	416
	417	/*
ad1ae2fe	418	* cpu_arm925_set_pte_ext(ptep, pte, ext)
1da177e4 LT	419	*
	420	* Set a PTE and flush it out
	421	*/
	422	.align 5
ad1ae2fe	423	ENTRY(cpu_arm925_set_pte_ext)
d090ddda	424	#ifdef CONFIG_MMU
da091653	425	armv3_set_pte_ext
1da177e4 LT	426	mov r0, r0
	427	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	428	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	429	#endif
	430	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	431	#endif /* CONFIG_MMU */
1da177e4 LT	432	mov pc, lr
1da177e4 LT	433
5085f3ff	434	__CPUINIT
1da177e4 LT	435
	436	.type __arm925_setup, #function
	437	__arm925_setup:
	438	mov r0, #0
	439	#if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
	440	orr r0,r0,#1 << 7
	441	#endif
	442
	443	/* Transparent on, D-cache clean & flush mode. See NOTE2 above */
	444	orr r0,r0,#1 << 1 @ transparent mode on
	445	mcr p15, 0, r0, c15, c1, 0 @ write TI config register
	446
	447	mov r0, #0
	448	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	449	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	450	#ifdef CONFIG_MMU
1da177e4	451	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	452	#endif
1da177e4 LT	453
	454	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	455	mov r0, #4 @ disable write-back on caches explicitly
	456	mcr p15, 7, r0, c15, c0, 0
	457	#endif
	458
906243d0 RK	459	adr r5, arm925_crval
906243d0 RK	460	ldmia r5, {r5, r6}
1da177e4	461	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	462	bic r0, r0, r5
22b19086	463	orr r0, r0, r6
1da177e4 LT	464	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	465	orr r0, r0, #0x4000 @ .1.. .... .... ....
	466	#endif
	467	mov pc, lr
	468	.size __arm925_setup, . - __arm925_setup
	469
	470	/*
	471	* R
	472	* .RVI ZFRS BLDP WCAM
	473	* .011 0001 ..11 1101
	474	*
	475	*/
22b19086 RK	476	.type arm925_crval, #object
	477	arm925_crval:
	478	crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
1da177e4 LT	479
1da177e4 LT	480	__INITDATA
6c240aec DM	481	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
6c240aec DM	482	define_processor_functions arm925, dabort=v4t_early_abort, pabort=legacy_pabort
1da177e4 LT	483
	484	.section ".rodata"
	485
6c240aec DM	486	string cpu_arch_name, "armv4t"
	487	string cpu_elf_name, "v4"
	488	string cpu_arm925_name, "ARM925T"
1da177e4 LT	489
	490	.align
	491
02b7dd12	492	.section ".proc.info.init", #alloc, #execinstr
1da177e4	493
6c240aec DM	494	.macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
	495	.type __\name\()_proc_info,#object
	496	__\name\()_proc_info:
	497	.long \cpu_val
	498	.long \cpu_mask
8799ee9f RK	499	.long PMD_TYPE_SECT \| \
	500	PMD_BIT4 \| \
	501	PMD_SECT_AP_WRITE \| \
	502	PMD_SECT_AP_READ
1da177e4 LT	503	.long PMD_TYPE_SECT \| \
	504	PMD_BIT4 \| \
	505	PMD_SECT_AP_WRITE \| \
	506	PMD_SECT_AP_READ
	507	b __arm925_setup
	508	.long cpu_arch_name
	509	.long cpu_elf_name
	510	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	511	.long cpu_arm925_name
	512	.long arm925_processor_functions
	513	.long v4wbi_tlb_fns
	514	.long v4wb_user_fns
	515	.long arm925_cache_fns
6c240aec DM	516	.size __\name\()_proc_info, . - __\name\()_proc_info
6c240aec DM	517	.endm
1da177e4	518
6c240aec DM	519	arm925_proc_info arm925, 0x54029250, 0xfffffff0, cpu_arm925_name
6c240aec DM	520	arm925_proc_info arm915, 0x54029150, 0xfffffff0, cpu_arm925_name