[deliverable/linux.git] / arch / arm / mm / proc-arm925.S

/*
 *  linux/arch/arm/mm/arm925.S: MMU functions for ARM925
 *
 *  Copyright (C) 1999,2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  Copyright (C) 2002 RidgeRun, Inc.
 *  Copyright (C) 2002-2003 MontaVista Software, Inc.
 *
 *  Update for Linux-2.6 and cache flush improvements
 *  Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
 *
 *  hacked for non-paged-MM by Hyok S. Choi, 2004.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm925.
 *
 *  CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
 *
 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
 *
 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
 *	  entry mode" must be 0 to flush the entries in both segments
 *	  at once. This is the default value. See TRM 2-20 and 2-24 for
 *	  more information.
 *
 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
 *	  like the "Transparent mode" must be on for partial cache flushes
 *	  to work in this mode. This mode only works with 16-bit external
 *	  memory. See TRM 2-24 for more information.
 *
 * NOTE3: Write-back cache flushing seems to be flakey with devices using
 *        direct memory access, such as USB OHCI. The workaround is to use
 *        write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
 *        the default for OMAP-1510).
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/elf.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	16

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	2

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	256

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintainence instructions.
 */
#define CACHE_DLIMIT	8192

	.text
/*
 * cpu_arm925_proc_init()
 */
ENTRY(cpu_arm925_proc_init)
	mov	pc, lr

/*
 * cpu_arm925_proc_fin()
 */
ENTRY(cpu_arm925_proc_fin)
	stmfd	sp!, {lr}
	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
	msr	cpsr_c, ip
	bl	arm925_flush_kern_cache_all
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ldmfd	sp!, {pc}

/*
 * cpu_arm925_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm925_reset)
	/* Send software reset to MPU and DSP */
	mov	ip, #0xff000000
	orr	ip, ip, #0x00fe0000
	orr	ip, ip, #0x0000ce00
	mov	r4, #1
	strh	r4, [ip, #0x10]

	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm925_do_idle()
 *
 * Called with IRQs disabled
 */
	.align	10
ENTRY(cpu_arm925_do_idle)
	mov	r0, #0
	mrc	p15, 0, r1, c1, c0, 0		@ Read control register
	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
	bic	r2, r1, #1 << 12
	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mcr	p15, 0, r1, c1, c0, 0		@ Restore ICache enable
	mov	pc, lr

/*
 *	flush_user_cache_all()
 *
 *	Clean and invalidate all cache entries in a particular
 *	address space.
 */
ENTRY(arm925_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm925_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
	/* Flush entries in both segments at once, see NOTE1 above */
	mov	r3, #(CACHE_DENTRIES - 1) << 4	@ 256 entries in segment
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	subs	r3, r3, #1 << 4
	bcs	2b				@ entries 255 to 0
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
ENTRY(arm925_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bgt	__flush_whole_cache
1:	tst	r2, #VM_EXEC
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#else
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#endif
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm925_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm925_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_page(void *page)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- page aligned address
 */
ENTRY(arm925_flush_kern_dcache_page)
	add	r1, r0, #PAGE_SZ
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
ENTRY(arm925_dma_inv_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
#endif
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
ENTRY(arm925_dma_clean_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm925_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
#else
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

ENTRY(arm925_cache_fns)
	.long	arm925_flush_kern_cache_all
	.long	arm925_flush_user_cache_all
	.long	arm925_flush_user_cache_range
	.long	arm925_coherent_kern_range
	.long	arm925_coherent_user_range
	.long	arm925_flush_kern_dcache_page
	.long	arm925_dma_inv_range
	.long	arm925_dma_clean_range
	.long	arm925_dma_flush_range

ENTRY(cpu_arm925_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm925_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm925_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
	/* Flush entries in bothe segments at once, see NOTE1 above */
	mov	r3, #(CACHE_DENTRIES - 1) << 4	@ 256 entries in segment
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
	subs	r3, r3, #1 << 4
	bcs	2b				@ entries 255 to 0
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mov	pc, lr

/*
 * cpu_arm925_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm925_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif /* CONFIG_MMU */
	mov	pc, lr

	__INIT

	.type	__arm925_setup, #function
__arm925_setup:
	mov	r0, #0
#if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
        orr     r0,r0,#1 << 7
#endif

	/* Transparent on, D-cache clean & flush mode. See  NOTE2 above */
        orr     r0,r0,#1 << 1			@ transparent mode on
        mcr     p15, 0, r0, c15, c1, 0          @ write TI config register

	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #4				@ disable write-back on caches explicitly
	mcr	p15, 7, r0, c15, c0, 0
#endif

	adr	r5, arm925_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000			@ .1.. .... .... ....
#endif
	mov	pc, lr
	.size	__arm925_setup, . - __arm925_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 0001 ..11 1101
	 * 
	 */
	.type	arm925_crval, #object
arm925_crval:
	crval	clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm925_processor_functions, #object
arm925_processor_functions:
	.word	v4t_early_abort
	.word	pabort_noifar
	.word	cpu_arm925_proc_init
	.word	cpu_arm925_proc_fin
	.word	cpu_arm925_reset
	.word   cpu_arm925_do_idle
	.word	cpu_arm925_dcache_clean_area
	.word	cpu_arm925_switch_mm
	.word	cpu_arm925_set_pte_ext
	.size	arm925_processor_functions, . - arm925_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv4t"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v4"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_arm925_name, #object
cpu_arm925_name:
	.asciz	"ARM925T"
	.size	cpu_arm925_name, . - cpu_arm925_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm925_proc_info,#object
__arm925_proc_info:
	.long	0x54029250
	.long	0xfffffff0
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm925_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm925_name
	.long	arm925_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm925_cache_fns
	.size	__arm925_proc_info, . - __arm925_proc_info

	.type	__arm915_proc_info,#object
__arm915_proc_info:
	.long	0x54029150
	.long	0xfffffff0
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm925_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm925_name
	.long	arm925_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm925_cache_fns
	.size	__arm925_proc_info, . - __arm925_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/arm925.S: MMU functions for ARM925
	3	*
	4	* Copyright (C) 1999,2000 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	6	* Copyright (C) 2002 RidgeRun, Inc.
	7	* Copyright (C) 2002-2003 MontaVista Software, Inc.
	8	*
	9	* Update for Linux-2.6 and cache flush improvements
	10	* Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
	11	*
d090ddda HC	12	* hacked for non-paged-MM by Hyok S. Choi, 2004.
d090ddda HC	13	*
1da177e4 LT	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	27	*
	28	*
	29	* These are the low level assembler for performing cache and TLB
	30	* functions on the arm925.
	31	*
	32	* CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
	33	*
	34	* Some additional notes based on deciphering the TI TRM on OMAP-5910:
	35	*
	36	* NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
	37	* entry mode" must be 0 to flush the entries in both segments
	38	* at once. This is the default value. See TRM 2-20 and 2-24 for
	39	* more information.
	40	*
	41	* NOTE2: Default is the "D-cache clean and flush entry mode". It looks
	42	* like the "Transparent mode" must be on for partial cache flushes
	43	* to work in this mode. This mode only works with 16-bit external
	44	* memory. See TRM 2-24 for more information.
	45	*
	46	* NOTE3: Write-back cache flushing seems to be flakey with devices using
	47	* direct memory access, such as USB OHCI. The workaround is to use
	48	* write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
	49	* the default for OMAP-1510).
	50	*/
	51
	52	#include <linux/linkage.h>
1da177e4 LT	53	#include <linux/init.h>
1da177e4 LT	54	#include <asm/assembler.h>
ee90dabc	55	#include <asm/elf.h>
74945c86	56	#include <asm/pgtable-hwdef.h>
1da177e4	57	#include <asm/pgtable.h>
1da177e4 LT	58	#include <asm/page.h>
	59	#include <asm/ptrace.h>
	60	#include "proc-macros.S"
	61
	62	/*
	63	* The size of one data cache line.
	64	*/
	65	#define CACHE_DLINESIZE 16
	66
	67	/*
	68	* The number of data cache segments.
	69	*/
	70	#define CACHE_DSEGMENTS 2
	71
	72	/*
	73	* The number of lines in a cache segment.
	74	*/
	75	#define CACHE_DENTRIES 256
	76
	77	/*
	78	* This is the size at which it becomes more efficient to
	79	* clean the whole cache, rather than using the individual
	80	* cache line maintainence instructions.
	81	*/
	82	#define CACHE_DLIMIT 8192
	83
	84	.text
	85	/*
	86	* cpu_arm925_proc_init()
	87	*/
	88	ENTRY(cpu_arm925_proc_init)
	89	mov pc, lr
	90
	91	/*
	92	* cpu_arm925_proc_fin()
	93	*/
	94	ENTRY(cpu_arm925_proc_fin)
	95	stmfd sp!, {lr}
	96	mov ip, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE
	97	msr cpsr_c, ip
	98	bl arm925_flush_kern_cache_all
	99	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	100	bic r0, r0, #0x1000 @ ...i............
	101	bic r0, r0, #0x000e @ ............wca.
	102	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	103	ldmfd sp!, {pc}
	104
	105	/*
	106	* cpu_arm925_reset(loc)
	107	*
	108	* Perform a soft reset of the system. Put the CPU into the
	109	* same state as it would be if it had been reset, and branch
	110	* to what would be the reset vector.
	111	*
	112	* loc: location to jump to for soft reset
	113	*/
	114	.align 5
	115	ENTRY(cpu_arm925_reset)
	116	/* Send software reset to MPU and DSP */
	117	mov ip, #0xff000000
	118	orr ip, ip, #0x00fe0000
	119	orr ip, ip, #0x0000ce00
	120	mov r4, #1
	121	strh r4, [ip, #0x10]
122
123	mov ip, #0
124	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
125	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	126	#ifdef CONFIG_MMU
1da177e4	127	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	128	#endif
1da177e4 LT	129	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	130	bic ip, ip, #0x000f @ ............wcam
	131	bic ip, ip, #0x1100 @ ...i...s........
	132	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	133	mov pc, r0
	134
	135	/*
	136	* cpu_arm925_do_idle()
	137	*
	138	* Called with IRQs disabled
	139	*/
	140	.align 10
	141	ENTRY(cpu_arm925_do_idle)
	142	mov r0, #0
	143	mrc p15, 0, r1, c1, c0, 0 @ Read control register
	144	mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
	145	bic r2, r1, #1 << 12
	146	mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
	147	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	148	mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
	149	mov pc, lr
	150
	151	/*
	152	* flush_user_cache_all()
	153	*
	154	* Clean and invalidate all cache entries in a particular
	155	* address space.
	156	*/
	157	ENTRY(arm925_flush_user_cache_all)
	158	/* FALLTHROUGH */
	159
	160	/*
	161	* flush_kern_cache_all()
	162	*
	163	* Clean and invalidate the entire cache.
	164	*/
	165	ENTRY(arm925_flush_kern_cache_all)
	166	mov r2, #VM_EXEC
	167	mov ip, #0
	168	__flush_whole_cache:
	169	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	170	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	171	#else
	172	/* Flush entries in both segments at once, see NOTE1 above */
	173	mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
	174	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	175	subs r3, r3, #1 << 4
	176	bcs 2b @ entries 255 to 0
	177	#endif
	178	tst r2, #VM_EXEC
	179	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	180	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	181	mov pc, lr
	182
	183	/*
	184	* flush_user_cache_range(start, end, flags)
	185	*
	186	* Clean and invalidate a range of cache entries in the
	187	* specified address range.
	188	*
	189	* - start - start address (inclusive)
	190	* - end - end address (exclusive)
	191	* - flags - vm_flags describing address space
	192	*/
193	ENTRY(arm925_flush_user_cache_range)
194	mov ip, #0
195	sub r3, r1, r0 @ calculate total size
196	cmp r3, #CACHE_DLIMIT
197	bgt __flush_whole_cache
198	1: tst r2, #VM_EXEC
199	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
200	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
201	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
202	add r0, r0, #CACHE_DLINESIZE
203	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
204	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
205	add r0, r0, #CACHE_DLINESIZE
206	#else
207	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
208	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
209	add r0, r0, #CACHE_DLINESIZE
210	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
211	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
212	add r0, r0, #CACHE_DLINESIZE
213	#endif
214	cmp r0, r1
215	blo 1b
216	tst r2, #VM_EXEC
217	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
218	mov pc, lr
219
220	/*
221	* coherent_kern_range(start, end)
222	*
223	* Ensure coherency between the Icache and the Dcache in the
224	* region described by start, end. If you have non-snooping
225	* Harvard caches, you need to implement this function.
226	*
227	* - start - virtual start address
228	* - end - virtual end address
229	*/
230	ENTRY(arm925_coherent_kern_range)
231	/* FALLTHROUGH */
232
233	/*
234	* coherent_user_range(start, end)
235	*
236	* Ensure coherency between the Icache and the Dcache in the
237	* region described by start, end. If you have non-snooping
238	* Harvard caches, you need to implement this function.
239	*
240	* - start - virtual start address
241	* - end - virtual end address
242	*/
243	ENTRY(arm925_coherent_user_range)
244	bic r0, r0, #CACHE_DLINESIZE - 1
245	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
246	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
247	add r0, r0, #CACHE_DLINESIZE
248	cmp r0, r1
249	blo 1b
250	mcr p15, 0, r0, c7, c10, 4 @ drain WB
251	mov pc, lr
252
253	/*
254	* flush_kern_dcache_page(void *page)
255	*
256	* Ensure no D cache aliasing occurs, either with itself or
257	* the I cache
258	*
259	* - addr - page aligned address
260	*/
261	ENTRY(arm925_flush_kern_dcache_page)
262	add r1, r0, #PAGE_SZ
263	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
264	add r0, r0, #CACHE_DLINESIZE
265	cmp r0, r1
266	blo 1b
267	mov r0, #0
268	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
269	mcr p15, 0, r0, c7, c10, 4 @ drain WB
270	mov pc, lr
271
272	/*
273	* dma_inv_range(start, end)
274	*
275	* Invalidate (discard) the specified virtual address range.
276	* May not write back any entries. If 'start' or 'end'
277	* are not cache line aligned, those lines must be written
278	* back.
279	*
280	* - start - virtual start address
281	* - end - virtual end address
282	*
283	* (same as v4wb)
284	*/
285	ENTRY(arm925_dma_inv_range)
286	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
287	tst r0, #CACHE_DLINESIZE - 1
288	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
289	tst r1, #CACHE_DLINESIZE - 1
290	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
291	#endif
292	bic r0, r0, #CACHE_DLINESIZE - 1
293	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
294	add r0, r0, #CACHE_DLINESIZE
295	cmp r0, r1
296	blo 1b
297	mcr p15, 0, r0, c7, c10, 4 @ drain WB
298	mov pc, lr
299
300	/*
301	* dma_clean_range(start, end)
302	*
303	* Clean the specified virtual address range.
304	*
305	* - start - virtual start address
306	* - end - virtual end address
307	*
308	* (same as v4wb)
309	*/
310	ENTRY(arm925_dma_clean_range)
311	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
312	bic r0, r0, #CACHE_DLINESIZE - 1
313	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
314	add r0, r0, #CACHE_DLINESIZE
315	cmp r0, r1
316	blo 1b
317	#endif
318	mcr p15, 0, r0, c7, c10, 4 @ drain WB
319	mov pc, lr
320
321	/*
322	* dma_flush_range(start, end)
323	*
324	* Clean and invalidate the specified virtual address range.
325	*
326	* - start - virtual start address
327	* - end - virtual end address
328	*/
329	ENTRY(arm925_dma_flush_range)
330	bic r0, r0, #CACHE_DLINESIZE - 1
331	1:
332	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
333	mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
334	#else
b3a8b751	335	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
1da177e4 LT	336	#endif
	337	add r0, r0, #CACHE_DLINESIZE
	338	cmp r0, r1
	339	blo 1b
	340	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	341	mov pc, lr
	342
	343	ENTRY(arm925_cache_fns)
	344	.long arm925_flush_kern_cache_all
	345	.long arm925_flush_user_cache_all
	346	.long arm925_flush_user_cache_range
	347	.long arm925_coherent_kern_range
	348	.long arm925_coherent_user_range
	349	.long arm925_flush_kern_dcache_page
	350	.long arm925_dma_inv_range
	351	.long arm925_dma_clean_range
	352	.long arm925_dma_flush_range
	353
	354	ENTRY(cpu_arm925_dcache_clean_area)
	355	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	356	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	357	add r0, r0, #CACHE_DLINESIZE
	358	subs r1, r1, #CACHE_DLINESIZE
	359	bhi 1b
	360	#endif
	361	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	362	mov pc, lr
	363
	364	/* =============================== PageTable ============================== */
	365
	366	/*
	367	* cpu_arm925_switch_mm(pgd)
	368	*
	369	* Set the translation base pointer to be as described by pgd.
	370	*
	371	* pgd: new page tables
	372	*/
	373	.align 5
	374	ENTRY(cpu_arm925_switch_mm)
d090ddda	375	#ifdef CONFIG_MMU
1da177e4 LT	376	mov ip, #0
	377	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	378	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	379	#else
	380	/* Flush entries in bothe segments at once, see NOTE1 above */
	381	mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
	382	2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
	383	subs r3, r3, #1 << 4
	384	bcs 2b @ entries 255 to 0
	385	#endif
	386	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	387	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	388	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	389	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	390	#endif
1da177e4 LT	391	mov pc, lr
	392
	393	/*
ad1ae2fe	394	* cpu_arm925_set_pte_ext(ptep, pte, ext)
1da177e4 LT	395	*
	396	* Set a PTE and flush it out
	397	*/
	398	.align 5
ad1ae2fe	399	ENTRY(cpu_arm925_set_pte_ext)
d090ddda	400	#ifdef CONFIG_MMU
da091653	401	armv3_set_pte_ext
1da177e4 LT	402	mov r0, r0
	403	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	404	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	405	#endif
	406	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	407	#endif /* CONFIG_MMU */
1da177e4 LT	408	mov pc, lr
	409
	410	__INIT
	411
	412	.type __arm925_setup, #function
	413	__arm925_setup:
	414	mov r0, #0
	415	#if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
	416	orr r0,r0,#1 << 7
	417	#endif
	418
	419	/* Transparent on, D-cache clean & flush mode. See NOTE2 above */
	420	orr r0,r0,#1 << 1 @ transparent mode on
	421	mcr p15, 0, r0, c15, c1, 0 @ write TI config register
	422
	423	mov r0, #0
	424	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	425	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	426	#ifdef CONFIG_MMU
1da177e4	427	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	428	#endif
1da177e4 LT	429
	430	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	431	mov r0, #4 @ disable write-back on caches explicitly
	432	mcr p15, 7, r0, c15, c0, 0
	433	#endif
	434
906243d0 RK	435	adr r5, arm925_crval
906243d0 RK	436	ldmia r5, {r5, r6}
1da177e4	437	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	438	bic r0, r0, r5
22b19086	439	orr r0, r0, r6
1da177e4 LT	440	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	441	orr r0, r0, #0x4000 @ .1.. .... .... ....
	442	#endif
	443	mov pc, lr
	444	.size __arm925_setup, . - __arm925_setup
	445
	446	/*
	447	* R
	448	* .RVI ZFRS BLDP WCAM
	449	* .011 0001 ..11 1101
	450	*
	451	*/
22b19086 RK	452	.type arm925_crval, #object
	453	arm925_crval:
	454	crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
1da177e4 LT	455
	456	__INITDATA
	457
	458	/*
	459	* Purpose : Function pointers used to access above functions - all calls
	460	* come through these
	461	*/
	462	.type arm925_processor_functions, #object
	463	arm925_processor_functions:
	464	.word v4t_early_abort
4a1fd556	465	.word pabort_noifar
1da177e4 LT	466	.word cpu_arm925_proc_init
	467	.word cpu_arm925_proc_fin
	468	.word cpu_arm925_reset
	469	.word cpu_arm925_do_idle
	470	.word cpu_arm925_dcache_clean_area
	471	.word cpu_arm925_switch_mm
ad1ae2fe	472	.word cpu_arm925_set_pte_ext
1da177e4 LT	473	.size arm925_processor_functions, . - arm925_processor_functions
	474
	475	.section ".rodata"
	476
	477	.type cpu_arch_name, #object
	478	cpu_arch_name:
	479	.asciz "armv4t"
	480	.size cpu_arch_name, . - cpu_arch_name
	481
	482	.type cpu_elf_name, #object
	483	cpu_elf_name:
	484	.asciz "v4"
	485	.size cpu_elf_name, . - cpu_elf_name
	486
	487	.type cpu_arm925_name, #object
	488	cpu_arm925_name:
264edb35	489	.asciz "ARM925T"
1da177e4 LT	490	.size cpu_arm925_name, . - cpu_arm925_name
	491
	492	.align
	493
02b7dd12	494	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	495
	496	.type __arm925_proc_info,#object
	497	__arm925_proc_info:
	498	.long 0x54029250
	499	.long 0xfffffff0
8799ee9f RK	500	.long PMD_TYPE_SECT \| \
	501	PMD_BIT4 \| \
	502	PMD_SECT_AP_WRITE \| \
	503	PMD_SECT_AP_READ
1da177e4 LT	504	.long PMD_TYPE_SECT \| \
	505	PMD_BIT4 \| \
	506	PMD_SECT_AP_WRITE \| \
	507	PMD_SECT_AP_READ
	508	b __arm925_setup
	509	.long cpu_arch_name
	510	.long cpu_elf_name
	511	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	512	.long cpu_arm925_name
	513	.long arm925_processor_functions
	514	.long v4wbi_tlb_fns
	515	.long v4wb_user_fns
	516	.long arm925_cache_fns
	517	.size __arm925_proc_info, . - __arm925_proc_info
	518
	519	.type __arm915_proc_info,#object
	520	__arm915_proc_info:
	521	.long 0x54029150
	522	.long 0xfffffff0
8799ee9f RK	523	.long PMD_TYPE_SECT \| \
	524	PMD_BIT4 \| \
	525	PMD_SECT_AP_WRITE \| \
	526	PMD_SECT_AP_READ
1da177e4 LT	527	.long PMD_TYPE_SECT \| \
	528	PMD_BIT4 \| \
	529	PMD_SECT_AP_WRITE \| \
	530	PMD_SECT_AP_READ
	531	b __arm925_setup
	532	.long cpu_arch_name
	533	.long cpu_elf_name
	534	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	535	.long cpu_arm925_name
	536	.long arm925_processor_functions
	537	.long v4wbi_tlb_fns
	538	.long v4wb_user_fns
	539	.long arm925_cache_fns
	540	.size __arm925_proc_info, . - __arm925_proc_info