[deliverable/linux.git] / arch / arm / mm / proc-arm926.S

/*
 *  linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
 *
 *  Copyright (C) 1999-2001 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm926.
 *
 *  CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/elf.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define CACHE_DLIMIT	16384

/*
 * the cache line size of the I and D cache
 */
#define CACHE_DLINESIZE	32

	.text
/*
 * cpu_arm926_proc_init()
 */
ENTRY(cpu_arm926_proc_init)
	mov	pc, lr

/*
 * cpu_arm926_proc_fin()
 */
ENTRY(cpu_arm926_proc_fin)
	stmfd	sp!, {lr}
	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
	msr	cpsr_c, ip
	bl	arm926_flush_kern_cache_all
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ldmfd	sp!, {pc}

/*
 * cpu_arm926_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm926_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm926_do_idle()
 *
 * Called with IRQs disabled
 */
	.align	10
ENTRY(cpu_arm926_do_idle)
	mov	r0, #0
	mrc	p15, 0, r1, c1, c0, 0		@ Read control register
	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
	bic	r2, r1, #1 << 12
	mrs	r3, cpsr			@ Disable FIQs while Icache
	orr	ip, r3, #PSR_F_BIT		@ is disabled
	msr	cpsr_c, ip
	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mcr	p15, 0, r1, c1, c0, 0		@ Restore ICache enable
	msr	cpsr_c, r3			@ Restore FIQ state
	mov	pc, lr

/*
 *	flush_user_cache_all()
 *
 *	Clean and invalidate all cache entries in a particular
 *	address space.
 */
ENTRY(arm926_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm926_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
ENTRY(arm926_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bgt	__flush_whole_cache
1:	tst	r2, #VM_EXEC
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#else
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#endif
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_page(void *page)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- page aligned address
 */
ENTRY(arm926_flush_kern_dcache_page)
	add	r1, r0, #PAGE_SZ
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
ENTRY(arm926_dma_inv_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
#endif
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
ENTRY(arm926_dma_clean_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
#else
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

ENTRY(arm926_cache_fns)
	.long	arm926_flush_kern_cache_all
	.long	arm926_flush_user_cache_all
	.long	arm926_flush_user_cache_range
	.long	arm926_coherent_kern_range
	.long	arm926_coherent_user_range
	.long	arm926_flush_kern_dcache_page
	.long	arm926_dma_inv_range
	.long	arm926_dma_clean_range
	.long	arm926_dma_flush_range

ENTRY(cpu_arm926_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm926_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm926_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mov	pc, lr

/*
 * cpu_arm926_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm926_set_pte_ext)
#ifdef CONFIG_MMU
	str	r1, [r0], #-2048		@ linux version

	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY

	bic	r2, r1, #PTE_SMALL_AP_MASK
	bic	r2, r2, #PTE_TYPE_MASK
	orr	r2, r2, #PTE_TYPE_SMALL

	tst	r1, #L_PTE_USER			@ User?
	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW

	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW

	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
	movne	r2, #0

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	eor	r3, r2, #0x0a			@ C & small page?
	tst	r3, #0x0b
	biceq	r2, r2, #4
#endif
	str	r2, [r0]			@ hardware version
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif
	mov	pc, lr

	__INIT

	.type	__arm926_setup, #function
__arm926_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif


#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #4				@ disable write-back on caches explicitly
	mcr	p15, 7, r0, c15, c0, 0
#endif 

	adr	r5, arm926_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000			@ .1.. .... .... ....
#endif
	mov	pc, lr
	.size	__arm926_setup, . - __arm926_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 0001 ..11 0101
	 * 
	 */
	.type	arm926_crval, #object
arm926_crval:
	crval	clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm926_processor_functions, #object
arm926_processor_functions:
	.word	v5tj_early_abort
	.word	pabort_noifar
	.word	cpu_arm926_proc_init
	.word	cpu_arm926_proc_fin
	.word	cpu_arm926_reset
	.word	cpu_arm926_do_idle
	.word	cpu_arm926_dcache_clean_area
	.word	cpu_arm926_switch_mm
	.word	cpu_arm926_set_pte_ext
	.size	arm926_processor_functions, . - arm926_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv5tej"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v5"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_arm926_name, #object
cpu_arm926_name:
	.asciz	"ARM926EJ-S"
	.size	cpu_arm926_name, . - cpu_arm926_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm926_proc_info,#object
__arm926_proc_info:
	.long	0x41069260			@ ARM926EJ-S (v5TEJ)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm926_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
	.long	cpu_arm926_name
	.long	arm926_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm926_cache_fns
	.size	__arm926_proc_info, . - __arm926_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
	3	*
	4	* Copyright (C) 1999-2001 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	6	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*
	23	* These are the low level assembler for performing cache and TLB
	24	* functions on the arm926.
	25	*
	26	* CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
	27	*/
	28	#include <linux/linkage.h>
1da177e4 LT	29	#include <linux/init.h>
1da177e4 LT	30	#include <asm/assembler.h>
ee90dabc	31	#include <asm/elf.h>
74945c86	32	#include <asm/pgtable-hwdef.h>
1da177e4	33	#include <asm/pgtable.h>
1da177e4 LT	34	#include <asm/page.h>
	35	#include <asm/ptrace.h>
	36	#include "proc-macros.S"
	37
	38	/*
	39	* This is the maximum size of an area which will be invalidated
	40	* using the single invalidate entry instructions. Anything larger
	41	* than this, and we go for the whole cache.
	42	*
	43	* This value should be chosen such that we choose the cheapest
	44	* alternative.
	45	*/
	46	#define CACHE_DLIMIT 16384
	47
	48	/*
	49	* the cache line size of the I and D cache
	50	*/
	51	#define CACHE_DLINESIZE 32
	52
	53	.text
	54	/*
	55	* cpu_arm926_proc_init()
	56	*/
	57	ENTRY(cpu_arm926_proc_init)
	58	mov pc, lr
	59
	60	/*
	61	* cpu_arm926_proc_fin()
	62	*/
	63	ENTRY(cpu_arm926_proc_fin)
	64	stmfd sp!, {lr}
	65	mov ip, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE
	66	msr cpsr_c, ip
	67	bl arm926_flush_kern_cache_all
	68	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	69	bic r0, r0, #0x1000 @ ...i............
	70	bic r0, r0, #0x000e @ ............wca.
	71	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	72	ldmfd sp!, {pc}
	73
	74	/*
	75	* cpu_arm926_reset(loc)
	76	*
	77	* Perform a soft reset of the system. Put the CPU into the
	78	* same state as it would be if it had been reset, and branch
	79	* to what would be the reset vector.
	80	*
	81	* loc: location to jump to for soft reset
	82	*/
	83	.align 5
	84	ENTRY(cpu_arm926_reset)
	85	mov ip, #0
	86	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	87	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	88	#ifdef CONFIG_MMU
1da177e4	89	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	90	#endif
1da177e4 LT	91	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	92	bic ip, ip, #0x000f @ ............wcam
	93	bic ip, ip, #0x1100 @ ...i...s........
	94	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	95	mov pc, r0
	96
	97	/*
	98	* cpu_arm926_do_idle()
	99	*
	100	* Called with IRQs disabled
	101	*/
	102	.align 10
	103	ENTRY(cpu_arm926_do_idle)
	104	mov r0, #0
	105	mrc p15, 0, r1, c1, c0, 0 @ Read control register
	106	mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
	107	bic r2, r1, #1 << 12
0214f922 RK	108	mrs r3, cpsr @ Disable FIQs while Icache
	109	orr ip, r3, #PSR_F_BIT @ is disabled
	110	msr cpsr_c, ip
1da177e4 LT	111	mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
	112	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	113	mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
0214f922	114	msr cpsr_c, r3 @ Restore FIQ state
1da177e4 LT	115	mov pc, lr
	116
	117	/*
	118	* flush_user_cache_all()
	119	*
	120	* Clean and invalidate all cache entries in a particular
	121	* address space.
	122	*/
	123	ENTRY(arm926_flush_user_cache_all)
	124	/* FALLTHROUGH */
	125
	126	/*
	127	* flush_kern_cache_all()
	128	*
	129	* Clean and invalidate the entire cache.
	130	*/
	131	ENTRY(arm926_flush_kern_cache_all)
	132	mov r2, #VM_EXEC
	133	mov ip, #0
	134	__flush_whole_cache:
	135	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	136	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	137	#else
	138	1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
	139	bne 1b
	140	#endif
	141	tst r2, #VM_EXEC
	142	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	143	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	144	mov pc, lr
	145
	146	/*
	147	* flush_user_cache_range(start, end, flags)
	148	*
	149	* Clean and invalidate a range of cache entries in the
	150	* specified address range.
	151	*
	152	* - start - start address (inclusive)
	153	* - end - end address (exclusive)
	154	* - flags - vm_flags describing address space
	155	*/
	156	ENTRY(arm926_flush_user_cache_range)
	157	mov ip, #0
	158	sub r3, r1, r0 @ calculate total size
	159	cmp r3, #CACHE_DLIMIT
	160	bgt __flush_whole_cache
	161	1: tst r2, #VM_EXEC
	162	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	163	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	164	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	165	add r0, r0, #CACHE_DLINESIZE
	166	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	167	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	168	add r0, r0, #CACHE_DLINESIZE
	169	#else
	170	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	171	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	172	add r0, r0, #CACHE_DLINESIZE
	173	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	174	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	175	add r0, r0, #CACHE_DLINESIZE
	176	#endif
	177	cmp r0, r1
	178	blo 1b
179	tst r2, #VM_EXEC
180	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
181	mov pc, lr
182
183	/*
184	* coherent_kern_range(start, end)
185	*
186	* Ensure coherency between the Icache and the Dcache in the
187	* region described by start, end. If you have non-snooping
188	* Harvard caches, you need to implement this function.
189	*
190	* - start - virtual start address
191	* - end - virtual end address
192	*/
193	ENTRY(arm926_coherent_kern_range)
194	/* FALLTHROUGH */
195
196	/*
197	* coherent_user_range(start, end)
198	*
199	* Ensure coherency between the Icache and the Dcache in the
200	* region described by start, end. If you have non-snooping
201	* Harvard caches, you need to implement this function.
202	*
203	* - start - virtual start address
204	* - end - virtual end address
205	*/
206	ENTRY(arm926_coherent_user_range)
207	bic r0, r0, #CACHE_DLINESIZE - 1
208	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
209	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
210	add r0, r0, #CACHE_DLINESIZE
211	cmp r0, r1
212	blo 1b
213	mcr p15, 0, r0, c7, c10, 4 @ drain WB
214	mov pc, lr
215
216	/*
217	* flush_kern_dcache_page(void *page)
218	*
219	* Ensure no D cache aliasing occurs, either with itself or
220	* the I cache
221	*
222	* - addr - page aligned address
223	*/
224	ENTRY(arm926_flush_kern_dcache_page)
225	add r1, r0, #PAGE_SZ
226	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
227	add r0, r0, #CACHE_DLINESIZE
228	cmp r0, r1
229	blo 1b
230	mov r0, #0
231	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
232	mcr p15, 0, r0, c7, c10, 4 @ drain WB
233	mov pc, lr
234
235	/*
236	* dma_inv_range(start, end)
237	*
238	* Invalidate (discard) the specified virtual address range.
239	* May not write back any entries. If 'start' or 'end'
240	* are not cache line aligned, those lines must be written
241	* back.
242	*
243	* - start - virtual start address
244	* - end - virtual end address
245	*
246	* (same as v4wb)
247	*/
248	ENTRY(arm926_dma_inv_range)
249	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
250	tst r0, #CACHE_DLINESIZE - 1
251	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
252	tst r1, #CACHE_DLINESIZE - 1
253	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
254	#endif
255	bic r0, r0, #CACHE_DLINESIZE - 1
256	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
257	add r0, r0, #CACHE_DLINESIZE
258	cmp r0, r1
259	blo 1b
260	mcr p15, 0, r0, c7, c10, 4 @ drain WB
261	mov pc, lr
262
263	/*
264	* dma_clean_range(start, end)
265	*
266	* Clean the specified virtual address range.
267	*
268	* - start - virtual start address
269	* - end - virtual end address
270	*
271	* (same as v4wb)
272	*/
273	ENTRY(arm926_dma_clean_range)
274	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
275	bic r0, r0, #CACHE_DLINESIZE - 1
276	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
277	add r0, r0, #CACHE_DLINESIZE
278	cmp r0, r1
279	blo 1b
280	#endif
281	mcr p15, 0, r0, c7, c10, 4 @ drain WB
282	mov pc, lr
283
284	/*
285	* dma_flush_range(start, end)
286	*
287	* Clean and invalidate the specified virtual address range.
288	*
289	* - start - virtual start address
290	* - end - virtual end address
291	*/
292	ENTRY(arm926_dma_flush_range)
293	bic r0, r0, #CACHE_DLINESIZE - 1
294	1:
295	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
296	mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
297	#else
b3a8b751	298	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
1da177e4 LT	299	#endif
	300	add r0, r0, #CACHE_DLINESIZE
	301	cmp r0, r1
	302	blo 1b
	303	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	304	mov pc, lr
	305
	306	ENTRY(arm926_cache_fns)
	307	.long arm926_flush_kern_cache_all
	308	.long arm926_flush_user_cache_all
	309	.long arm926_flush_user_cache_range
	310	.long arm926_coherent_kern_range
	311	.long arm926_coherent_user_range
	312	.long arm926_flush_kern_dcache_page
	313	.long arm926_dma_inv_range
	314	.long arm926_dma_clean_range
	315	.long arm926_dma_flush_range
	316
	317	ENTRY(cpu_arm926_dcache_clean_area)
	318	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	319	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	320	add r0, r0, #CACHE_DLINESIZE
	321	subs r1, r1, #CACHE_DLINESIZE
	322	bhi 1b
	323	#endif
	324	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	325	mov pc, lr
	326
	327	/* =============================== PageTable ============================== */
	328
	329	/*
	330	* cpu_arm926_switch_mm(pgd)
	331	*
	332	* Set the translation base pointer to be as described by pgd.
	333	*
	334	* pgd: new page tables
	335	*/
	336	.align 5
	337	ENTRY(cpu_arm926_switch_mm)
d090ddda	338	#ifdef CONFIG_MMU
1da177e4 LT	339	mov ip, #0
	340	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	341	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	342	#else
	343	@ && 'Clean & Invalidate whole DCache'
	344	1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
	345	bne 1b
	346	#endif
	347	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	348	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	349	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	350	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	351	#endif
1da177e4 LT	352	mov pc, lr
	353
	354	/*
ad1ae2fe	355	* cpu_arm926_set_pte_ext(ptep, pte, ext)
1da177e4 LT	356	*
	357	* Set a PTE and flush it out
	358	*/
	359	.align 5
ad1ae2fe	360	ENTRY(cpu_arm926_set_pte_ext)
d090ddda	361	#ifdef CONFIG_MMU
1da177e4 LT	362	str r1, [r0], #-2048 @ linux version
	363
	364	eor r1, r1, #L_PTE_PRESENT \| L_PTE_YOUNG \| L_PTE_WRITE \| L_PTE_DIRTY
	365
	366	bic r2, r1, #PTE_SMALL_AP_MASK
	367	bic r2, r2, #PTE_TYPE_MASK
	368	orr r2, r2, #PTE_TYPE_SMALL
	369
	370	tst r1, #L_PTE_USER @ User?
	371	orrne r2, r2, #PTE_SMALL_AP_URO_SRW
	372
	373	tst r1, #L_PTE_WRITE \| L_PTE_DIRTY @ Write and Dirty?
	374	orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
	375
	376	tst r1, #L_PTE_PRESENT \| L_PTE_YOUNG @ Present and Young?
	377	movne r2, #0
	378
	379	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	380	eor r3, r2, #0x0a @ C & small page?
	381	tst r3, #0x0b
	382	biceq r2, r2, #4
	383	#endif
	384	str r2, [r0] @ hardware version
	385	mov r0, r0
	386	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	387	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	388	#endif
	389	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	390	#endif
1da177e4 LT	391	mov pc, lr
	392
	393	__INIT
	394
	395	.type __arm926_setup, #function
	396	__arm926_setup:
	397	mov r0, #0
	398	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	399	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	400	#ifdef CONFIG_MMU
1da177e4	401	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	402	#endif
1da177e4 LT	403
	404
	405	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	406	mov r0, #4 @ disable write-back on caches explicitly
	407	mcr p15, 7, r0, c15, c0, 0
	408	#endif
	409
22b19086 RK	410	adr r5, arm926_crval
22b19086 RK	411	ldmia r5, {r5, r6}
1da177e4	412	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	413	bic r0, r0, r5
22b19086	414	orr r0, r0, r6
1da177e4 LT	415	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	416	orr r0, r0, #0x4000 @ .1.. .... .... ....
	417	#endif
	418	mov pc, lr
	419	.size __arm926_setup, . - __arm926_setup
	420
	421	/*
	422	* R
	423	* .RVI ZFRS BLDP WCAM
	424	* .011 0001 ..11 0101
	425	*
	426	*/
22b19086 RK	427	.type arm926_crval, #object
	428	arm926_crval:
	429	crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
1da177e4 LT	430
	431	__INITDATA
	432
	433	/*
	434	* Purpose : Function pointers used to access above functions - all calls
	435	* come through these
	436	*/
	437	.type arm926_processor_functions, #object
	438	arm926_processor_functions:
	439	.word v5tj_early_abort
4a1fd556	440	.word pabort_noifar
1da177e4 LT	441	.word cpu_arm926_proc_init
	442	.word cpu_arm926_proc_fin
	443	.word cpu_arm926_reset
	444	.word cpu_arm926_do_idle
	445	.word cpu_arm926_dcache_clean_area
	446	.word cpu_arm926_switch_mm
ad1ae2fe	447	.word cpu_arm926_set_pte_ext
1da177e4 LT	448	.size arm926_processor_functions, . - arm926_processor_functions
	449
	450	.section ".rodata"
	451
	452	.type cpu_arch_name, #object
	453	cpu_arch_name:
	454	.asciz "armv5tej"
	455	.size cpu_arch_name, . - cpu_arch_name
	456
	457	.type cpu_elf_name, #object
	458	cpu_elf_name:
	459	.asciz "v5"
	460	.size cpu_elf_name, . - cpu_elf_name
	461
	462	.type cpu_arm926_name, #object
	463	cpu_arm926_name:
264edb35	464	.asciz "ARM926EJ-S"
1da177e4 LT	465	.size cpu_arm926_name, . - cpu_arm926_name
	466
	467	.align
	468
02b7dd12	469	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	470
	471	.type __arm926_proc_info,#object
	472	__arm926_proc_info:
	473	.long 0x41069260 @ ARM926EJ-S (v5TEJ)
	474	.long 0xff0ffff0
	475	.long PMD_TYPE_SECT \| \
	476	PMD_SECT_BUFFERABLE \| \
	477	PMD_SECT_CACHEABLE \| \
	478	PMD_BIT4 \| \
	479	PMD_SECT_AP_WRITE \| \
	480	PMD_SECT_AP_READ
8799ee9f RK	481	.long PMD_TYPE_SECT \| \
	482	PMD_BIT4 \| \
	483	PMD_SECT_AP_WRITE \| \
	484	PMD_SECT_AP_READ
1da177e4 LT	485	b __arm926_setup
	486	.long cpu_arch_name
	487	.long cpu_elf_name
efe90d27	488	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_JAVA
1da177e4 LT	489	.long cpu_arm926_name
	490	.long arm926_processor_functions
	491	.long v4wbi_tlb_fns
	492	.long v4wb_user_fns
	493	.long arm926_cache_fns
	494	.size __arm926_proc_info, . - __arm926_proc_info