[deliverable/linux.git] / arch / arm / mm / proc-arm926.S

/*
 *  linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
 *
 *  Copyright (C) 1999-2001 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm926.
 *
 *  CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define CACHE_DLIMIT	16384

/*
 * the cache line size of the I and D cache
 */
#define CACHE_DLINESIZE	32

	.text
/*
 * cpu_arm926_proc_init()
 */
ENTRY(cpu_arm926_proc_init)
	mov	pc, lr

/*
 * cpu_arm926_proc_fin()
 */
ENTRY(cpu_arm926_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_arm926_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm926_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm926_do_idle()
 *
 * Called with IRQs disabled
 */
	.align	10
ENTRY(cpu_arm926_do_idle)
	mov	r0, #0
	mrc	p15, 0, r1, c1, c0, 0		@ Read control register
	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
	bic	r2, r1, #1 << 12
	mrs	r3, cpsr			@ Disable FIQs while Icache
	orr	ip, r3, #PSR_F_BIT		@ is disabled
	msr	cpsr_c, ip
	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mcr	p15, 0, r1, c1, c0, 0		@ Restore ICache enable
	msr	cpsr_c, r3			@ Restore FIQ state
	mov	pc, lr

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(arm926_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mov	pc, lr
ENDPROC(arm926_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Clean and invalidate all cache entries in a particular
 *	address space.
 */
ENTRY(arm926_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm926_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
ENTRY(arm926_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bgt	__flush_whole_cache
1:	tst	r2, #VM_EXEC
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#else
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#endif
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(arm926_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm926_dma_inv_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
#endif
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm926_dma_clean_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
#else
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm926_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm926_dma_clean_range
	bcs	arm926_dma_inv_range
	b	arm926_dma_flush_range
ENDPROC(arm926_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm926_dma_unmap_area)
	mov	pc, lr
ENDPROC(arm926_dma_unmap_area)

	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
	define_cache_functions arm926

ENTRY(cpu_arm926_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm926_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm926_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mov	pc, lr

/*
 * cpu_arm926_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm926_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif
	mov	pc, lr

/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
.globl	cpu_arm926_suspend_size
.equ	cpu_arm926_suspend_size, 4 * 4
#ifdef CONFIG_PM_SLEEP
ENTRY(cpu_arm926_do_suspend)
	stmfd	sp!, {r4 - r7, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ PID
	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r6, c2, c0, 0	@ TTB address
	mrc	p15, 0, r7, c1, c0, 0	@ Control register
	stmia	r0, {r4 - r7}
	ldmfd	sp!, {r4 - r7, pc}
ENDPROC(cpu_arm926_do_suspend)

ENTRY(cpu_arm926_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs
	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches
	ldmia	r0, {r4 - r7}
	mcr	p15, 0, r4, c13, c0, 0	@ PID
	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
	mcr	p15, 0, r6, c2, c0, 0	@ TTB address
	mov	r0, r7			@ control register
	mov	r2, r6, lsr #14		@ get TTB0 base
	mov	r2, r2, lsl #14
	ldr	r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
		     PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
	b	cpu_resume_mmu
ENDPROC(cpu_arm926_do_resume)
#endif

	__CPUINIT

	.type	__arm926_setup, #function
__arm926_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif


#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #4				@ disable write-back on caches explicitly
	mcr	p15, 7, r0, c15, c0, 0
#endif 

	adr	r5, arm926_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000			@ .1.. .... .... ....
#endif
	mov	pc, lr
	.size	__arm926_setup, . - __arm926_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 0001 ..11 0101
	 * 
	 */
	.type	arm926_crval, #object
arm926_crval:
	crval	clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1

	.section ".rodata"

	string	cpu_arch_name, "armv5tej"
	string	cpu_elf_name, "v5"
	string	cpu_arm926_name, "ARM926EJ-S"

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm926_proc_info,#object
__arm926_proc_info:
	.long	0x41069260			@ ARM926EJ-S (v5TEJ)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm926_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
	.long	cpu_arm926_name
	.long	arm926_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm926_cache_fns
	.size	__arm926_proc_info, . - __arm926_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
	3	*
	4	* Copyright (C) 1999-2001 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	6	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*
	23	* These are the low level assembler for performing cache and TLB
	24	* functions on the arm926.
	25	*
	26	* CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
	27	*/
	28	#include <linux/linkage.h>
1da177e4 LT	29	#include <linux/init.h>
1da177e4 LT	30	#include <asm/assembler.h>
5ec9407d	31	#include <asm/hwcap.h>
74945c86	32	#include <asm/pgtable-hwdef.h>
1da177e4	33	#include <asm/pgtable.h>
1da177e4 LT	34	#include <asm/page.h>
	35	#include <asm/ptrace.h>
	36	#include "proc-macros.S"
	37
	38	/*
	39	* This is the maximum size of an area which will be invalidated
	40	* using the single invalidate entry instructions. Anything larger
	41	* than this, and we go for the whole cache.
	42	*
	43	* This value should be chosen such that we choose the cheapest
	44	* alternative.
	45	*/
	46	#define CACHE_DLIMIT 16384
	47
	48	/*
	49	* the cache line size of the I and D cache
	50	*/
	51	#define CACHE_DLINESIZE 32
	52
	53	.text
	54	/*
	55	* cpu_arm926_proc_init()
	56	*/
	57	ENTRY(cpu_arm926_proc_init)
	58	mov pc, lr
	59
	60	/*
	61	* cpu_arm926_proc_fin()
	62	*/
	63	ENTRY(cpu_arm926_proc_fin)
1da177e4 LT	64	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	65	bic r0, r0, #0x1000 @ ...i............
	66	bic r0, r0, #0x000e @ ............wca.
	67	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	68	mov pc, lr
1da177e4 LT	69
	70	/*
	71	* cpu_arm926_reset(loc)
	72	*
	73	* Perform a soft reset of the system. Put the CPU into the
	74	* same state as it would be if it had been reset, and branch
	75	* to what would be the reset vector.
	76	*
	77	* loc: location to jump to for soft reset
	78	*/
	79	.align 5
	80	ENTRY(cpu_arm926_reset)
	81	mov ip, #0
	82	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	83	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	84	#ifdef CONFIG_MMU
1da177e4	85	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	86	#endif
1da177e4 LT	87	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	88	bic ip, ip, #0x000f @ ............wcam
	89	bic ip, ip, #0x1100 @ ...i...s........
	90	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	91	mov pc, r0
	92
	93	/*
	94	* cpu_arm926_do_idle()
	95	*
	96	* Called with IRQs disabled
	97	*/
	98	.align 10
	99	ENTRY(cpu_arm926_do_idle)
	100	mov r0, #0
	101	mrc p15, 0, r1, c1, c0, 0 @ Read control register
	102	mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
	103	bic r2, r1, #1 << 12
0214f922 RK	104	mrs r3, cpsr @ Disable FIQs while Icache
	105	orr ip, r3, #PSR_F_BIT @ is disabled
	106	msr cpsr_c, ip
1da177e4 LT	107	mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
	108	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	109	mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
0214f922	110	msr cpsr_c, r3 @ Restore FIQ state
1da177e4 LT	111	mov pc, lr
1da177e4 LT	112
c8c90860 MW	113	/*
	114	* flush_icache_all()
	115	*
	116	* Unconditionally clean and invalidate the entire icache.
	117	*/
	118	ENTRY(arm926_flush_icache_all)
	119	mov r0, #0
	120	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	121	mov pc, lr
	122	ENDPROC(arm926_flush_icache_all)
	123
1da177e4 LT	124	/*
	125	* flush_user_cache_all()
	126	*
	127	* Clean and invalidate all cache entries in a particular
	128	* address space.
	129	*/
	130	ENTRY(arm926_flush_user_cache_all)
	131	/* FALLTHROUGH */
	132
	133	/*
	134	* flush_kern_cache_all()
	135	*
	136	* Clean and invalidate the entire cache.
	137	*/
	138	ENTRY(arm926_flush_kern_cache_all)
	139	mov r2, #VM_EXEC
	140	mov ip, #0
	141	__flush_whole_cache:
	142	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	143	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	144	#else
	145	1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
	146	bne 1b
	147	#endif
	148	tst r2, #VM_EXEC
	149	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	150	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	151	mov pc, lr
	152
	153	/*
	154	* flush_user_cache_range(start, end, flags)
	155	*
	156	* Clean and invalidate a range of cache entries in the
	157	* specified address range.
	158	*
	159	* - start - start address (inclusive)
	160	* - end - end address (exclusive)
	161	* - flags - vm_flags describing address space
	162	*/
	163	ENTRY(arm926_flush_user_cache_range)
	164	mov ip, #0
	165	sub r3, r1, r0 @ calculate total size
	166	cmp r3, #CACHE_DLIMIT
	167	bgt __flush_whole_cache
	168	1: tst r2, #VM_EXEC
	169	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	170	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	171	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	172	add r0, r0, #CACHE_DLINESIZE
	173	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	174	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	175	add r0, r0, #CACHE_DLINESIZE
	176	#else
	177	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	178	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	179	add r0, r0, #CACHE_DLINESIZE
	180	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	181	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	182	add r0, r0, #CACHE_DLINESIZE
	183	#endif
	184	cmp r0, r1
	185	blo 1b
	186	tst r2, #VM_EXEC
	187	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188	mov pc, lr
189
190	/*
191	* coherent_kern_range(start, end)
192	*
193	* Ensure coherency between the Icache and the Dcache in the
194	* region described by start, end. If you have non-snooping
195	* Harvard caches, you need to implement this function.
196	*
197	* - start - virtual start address
198	* - end - virtual end address
199	*/
200	ENTRY(arm926_coherent_kern_range)
201	/* FALLTHROUGH */
202
203	/*
204	* coherent_user_range(start, end)
205	*
206	* Ensure coherency between the Icache and the Dcache in the
207	* region described by start, end. If you have non-snooping
208	* Harvard caches, you need to implement this function.
209	*
210	* - start - virtual start address
211	* - end - virtual end address
212	*/
213	ENTRY(arm926_coherent_user_range)
214	bic r0, r0, #CACHE_DLINESIZE - 1
215	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
216	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
217	add r0, r0, #CACHE_DLINESIZE
218	cmp r0, r1
219	blo 1b
220	mcr p15, 0, r0, c7, c10, 4 @ drain WB
221	mov pc, lr
222
223	/*
2c9b9c84	224	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	225	*
	226	* Ensure no D cache aliasing occurs, either with itself or
	227	* the I cache
	228	*
2c9b9c84 RK	229	* - addr - kernel address
2c9b9c84 RK	230	* - size - region size
1da177e4	231	*/
2c9b9c84 RK	232	ENTRY(arm926_flush_kern_dcache_area)
2c9b9c84 RK	233	add r1, r0, r1
1da177e4 LT	234	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	235	add r0, r0, #CACHE_DLINESIZE
	236	cmp r0, r1
	237	blo 1b
	238	mov r0, #0
	239	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	240	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	241	mov pc, lr
	242
	243	/*
	244	* dma_inv_range(start, end)
	245	*
	246	* Invalidate (discard) the specified virtual address range.
	247	* May not write back any entries. If 'start' or 'end'
	248	* are not cache line aligned, those lines must be written
	249	* back.
	250	*
	251	* - start - virtual start address
	252	* - end - virtual end address
	253	*
	254	* (same as v4wb)
	255	*/
702b94bf	256	arm926_dma_inv_range:
1da177e4 LT	257	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	258	tst r0, #CACHE_DLINESIZE - 1
	259	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	260	tst r1, #CACHE_DLINESIZE - 1
	261	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	262	#endif
	263	bic r0, r0, #CACHE_DLINESIZE - 1
	264	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	265	add r0, r0, #CACHE_DLINESIZE
	266	cmp r0, r1
	267	blo 1b
	268	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	269	mov pc, lr
	270
	271	/*
	272	* dma_clean_range(start, end)
	273	*
	274	* Clean the specified virtual address range.
	275	*
	276	* - start - virtual start address
	277	* - end - virtual end address
	278	*
	279	* (same as v4wb)
	280	*/
702b94bf	281	arm926_dma_clean_range:
1da177e4 LT	282	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	283	bic r0, r0, #CACHE_DLINESIZE - 1
	284	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	285	add r0, r0, #CACHE_DLINESIZE
	286	cmp r0, r1
	287	blo 1b
	288	#endif
	289	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	290	mov pc, lr
	291
	292	/*
	293	* dma_flush_range(start, end)
	294	*
	295	* Clean and invalidate the specified virtual address range.
	296	*
	297	* - start - virtual start address
	298	* - end - virtual end address
	299	*/
	300	ENTRY(arm926_dma_flush_range)
	301	bic r0, r0, #CACHE_DLINESIZE - 1
	302	1:
	303	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	304	mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	305	#else
b3a8b751	306	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
1da177e4 LT	307	#endif
	308	add r0, r0, #CACHE_DLINESIZE
	309	cmp r0, r1
	310	blo 1b
	311	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	312	mov pc, lr
	313
a9c9147e RK	314	/*
	315	* dma_map_area(start, size, dir)
	316	* - start - kernel virtual start address
	317	* - size - size of region
	318	* - dir - DMA direction
	319	*/
	320	ENTRY(arm926_dma_map_area)
	321	add r1, r1, r0
	322	cmp r2, #DMA_TO_DEVICE
	323	beq arm926_dma_clean_range
	324	bcs arm926_dma_inv_range
	325	b arm926_dma_flush_range
	326	ENDPROC(arm926_dma_map_area)
	327
	328	/*
	329	* dma_unmap_area(start, size, dir)
	330	* - start - kernel virtual start address
	331	* - size - size of region
	332	* - dir - DMA direction
	333	*/
	334	ENTRY(arm926_dma_unmap_area)
	335	mov pc, lr
	336	ENDPROC(arm926_dma_unmap_area)
	337
be90da45 DM	338	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
be90da45 DM	339	define_cache_functions arm926
1da177e4 LT	340
	341	ENTRY(cpu_arm926_dcache_clean_area)
	342	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	343	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	344	add r0, r0, #CACHE_DLINESIZE
	345	subs r1, r1, #CACHE_DLINESIZE
	346	bhi 1b
	347	#endif
	348	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	349	mov pc, lr
	350
	351	/* =============================== PageTable ============================== */
	352
	353	/*
	354	* cpu_arm926_switch_mm(pgd)
	355	*
	356	* Set the translation base pointer to be as described by pgd.
	357	*
	358	* pgd: new page tables
	359	*/
	360	.align 5
	361	ENTRY(cpu_arm926_switch_mm)
d090ddda	362	#ifdef CONFIG_MMU
1da177e4 LT	363	mov ip, #0
	364	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	365	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	366	#else
	367	@ && 'Clean & Invalidate whole DCache'
	368	1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
	369	bne 1b
	370	#endif
	371	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	372	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	373	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	374	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	375	#endif
1da177e4 LT	376	mov pc, lr
	377
	378	/*
ad1ae2fe	379	* cpu_arm926_set_pte_ext(ptep, pte, ext)
1da177e4 LT	380	*
	381	* Set a PTE and flush it out
	382	*/
	383	.align 5
ad1ae2fe	384	ENTRY(cpu_arm926_set_pte_ext)
d090ddda	385	#ifdef CONFIG_MMU
da091653	386	armv3_set_pte_ext
1da177e4 LT	387	mov r0, r0
	388	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	389	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	390	#endif
	391	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	392	#endif
1da177e4 LT	393	mov pc, lr
1da177e4 LT	394
f6b0fa02 RK	395	/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
f6b0fa02 RK	396	.globl cpu_arm926_suspend_size
1c0270cd	397	.equ cpu_arm926_suspend_size, 4 * 4
29ea23ff	398	#ifdef CONFIG_PM_SLEEP
f6b0fa02 RK	399	ENTRY(cpu_arm926_do_suspend)
	400	stmfd sp!, {r4 - r7, lr}
	401	mrc p15, 0, r4, c13, c0, 0 @ PID
	402	mrc p15, 0, r5, c3, c0, 0 @ Domain ID
	403	mrc p15, 0, r6, c2, c0, 0 @ TTB address
	404	mrc p15, 0, r7, c1, c0, 0 @ Control register
	405	stmia r0, {r4 - r7}
	406	ldmfd sp!, {r4 - r7, pc}
	407	ENDPROC(cpu_arm926_do_suspend)
	408
	409	ENTRY(cpu_arm926_do_resume)
	410	mov ip, #0
	411	mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
	412	mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
	413	ldmia r0, {r4 - r7}
	414	mcr p15, 0, r4, c13, c0, 0 @ PID
	415	mcr p15, 0, r5, c3, c0, 0 @ Domain ID
	416	mcr p15, 0, r6, c2, c0, 0 @ TTB address
	417	mov r0, r7 @ control register
	418	mov r2, r6, lsr #14 @ get TTB0 base
	419	mov r2, r2, lsl #14
	420	ldr r3, =PMD_TYPE_SECT \| PMD_SECT_BUFFERABLE \| \
	421	PMD_SECT_CACHEABLE \| PMD_BIT4 \| PMD_SECT_AP_WRITE
	422	b cpu_resume_mmu
	423	ENDPROC(cpu_arm926_do_resume)
f6b0fa02 RK	424	#endif
f6b0fa02 RK	425
5085f3ff	426	__CPUINIT
1da177e4 LT	427
	428	.type __arm926_setup, #function
	429	__arm926_setup:
	430	mov r0, #0
	431	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	432	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	433	#ifdef CONFIG_MMU
1da177e4	434	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	435	#endif
1da177e4 LT	436
	437
	438	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	439	mov r0, #4 @ disable write-back on caches explicitly
	440	mcr p15, 7, r0, c15, c0, 0
	441	#endif
	442
22b19086 RK	443	adr r5, arm926_crval
22b19086 RK	444	ldmia r5, {r5, r6}
1da177e4	445	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	446	bic r0, r0, r5
22b19086	447	orr r0, r0, r6
1da177e4 LT	448	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	449	orr r0, r0, #0x4000 @ .1.. .... .... ....
	450	#endif
	451	mov pc, lr
	452	.size __arm926_setup, . - __arm926_setup
	453
	454	/*
	455	* R
	456	* .RVI ZFRS BLDP WCAM
	457	* .011 0001 ..11 0101
	458	*
	459	*/
22b19086 RK	460	.type arm926_crval, #object
	461	arm926_crval:
	462	crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
1da177e4 LT	463
	464	__INITDATA
	465
be90da45 DM	466	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
be90da45 DM	467	define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1
1da177e4 LT	468
	469	.section ".rodata"
	470
be90da45 DM	471	string cpu_arch_name, "armv5tej"
	472	string cpu_elf_name, "v5"
	473	string cpu_arm926_name, "ARM926EJ-S"
1da177e4 LT	474
	475	.align
	476
02b7dd12	477	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	478
	479	.type __arm926_proc_info,#object
	480	__arm926_proc_info:
	481	.long 0x41069260 @ ARM926EJ-S (v5TEJ)
	482	.long 0xff0ffff0
	483	.long PMD_TYPE_SECT \| \
	484	PMD_SECT_BUFFERABLE \| \
	485	PMD_SECT_CACHEABLE \| \
	486	PMD_BIT4 \| \
	487	PMD_SECT_AP_WRITE \| \
	488	PMD_SECT_AP_READ
8799ee9f RK	489	.long PMD_TYPE_SECT \| \
	490	PMD_BIT4 \| \
	491	PMD_SECT_AP_WRITE \| \
	492	PMD_SECT_AP_READ
1da177e4 LT	493	b __arm926_setup
	494	.long cpu_arch_name
	495	.long cpu_elf_name
efe90d27	496	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_JAVA
1da177e4 LT	497	.long cpu_arm926_name
	498	.long arm926_processor_functions
	499	.long v4wbi_tlb_fns
	500	.long v4wb_user_fns
	501	.long arm926_cache_fns
	502	.size __arm926_proc_info, . - __arm926_proc_info