[deliverable/linux.git] / arch / arm / mm / proc-arm926.S

/*
 *  linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
 *
 *  Copyright (C) 1999-2001 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm926.
 *
 *  CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/config.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/procinfo.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define CACHE_DLIMIT	16384

/*
 * the cache line size of the I and D cache
 */
#define CACHE_DLINESIZE	32

	.text
/*
 * cpu_arm926_proc_init()
 */
ENTRY(cpu_arm926_proc_init)
	mov	pc, lr

/*
 * cpu_arm926_proc_fin()
 */
ENTRY(cpu_arm926_proc_fin)
	stmfd	sp!, {lr}
	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
	msr	cpsr_c, ip
	bl	arm926_flush_kern_cache_all
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ldmfd	sp!, {pc}

/*
 * cpu_arm926_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm926_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm926_do_idle()
 *
 * Called with IRQs disabled
 */
	.align	10
ENTRY(cpu_arm926_do_idle)
	mov	r0, #0
	mrc	p15, 0, r1, c1, c0, 0		@ Read control register
	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
	bic	r2, r1, #1 << 12
	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mcr	p15, 0, r1, c1, c0, 0		@ Restore ICache enable
	mov	pc, lr

/*
 *	flush_user_cache_all()
 *
 *	Clean and invalidate all cache entries in a particular
 *	address space.
 */
ENTRY(arm926_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm926_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
ENTRY(arm926_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bgt	__flush_whole_cache
1:	tst	r2, #VM_EXEC
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#else
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#endif
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_page(void *page)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- page aligned address
 */
ENTRY(arm926_flush_kern_dcache_page)
	add	r1, r0, #PAGE_SZ
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
ENTRY(arm926_dma_inv_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
#endif
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
ENTRY(arm926_dma_clean_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
#else
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

ENTRY(arm926_cache_fns)
	.long	arm926_flush_kern_cache_all
	.long	arm926_flush_user_cache_all
	.long	arm926_flush_user_cache_range
	.long	arm926_coherent_kern_range
	.long	arm926_coherent_user_range
	.long	arm926_flush_kern_dcache_page
	.long	arm926_dma_inv_range
	.long	arm926_dma_clean_range
	.long	arm926_dma_flush_range

ENTRY(cpu_arm926_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm926_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm926_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mov	pc, lr

/*
 * cpu_arm926_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm926_set_pte)
#ifdef CONFIG_MMU
	str	r1, [r0], #-2048		@ linux version

	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY

	bic	r2, r1, #PTE_SMALL_AP_MASK
	bic	r2, r2, #PTE_TYPE_MASK
	orr	r2, r2, #PTE_TYPE_SMALL

	tst	r1, #L_PTE_USER			@ User?
	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW

	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW

	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
	movne	r2, #0

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	eor	r3, r2, #0x0a			@ C & small page?
	tst	r3, #0x0b
	biceq	r2, r2, #4
#endif
	str	r2, [r0]			@ hardware version
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif
	mov	pc, lr

	__INIT

	.type	__arm926_setup, #function
__arm926_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif


#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #4				@ disable write-back on caches explicitly
	mcr	p15, 7, r0, c15, c0, 0
#endif 

	mrc	p15, 0, r0, c1, c0		@ get control register v4
	ldr	r5, arm926_cr1_clear
	bic	r0, r0, r5
	ldr	r5, arm926_cr1_set
	orr	r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000			@ .1.. .... .... ....
#endif
	mov	pc, lr
	.size	__arm926_setup, . - __arm926_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 0001 ..11 0101
	 * 
	 */
	.type	arm926_cr1_clear, #object
	.type	arm926_cr1_set, #object
arm926_cr1_clear:
	.word	0x7f3f
arm926_cr1_set:
	.word	0x3135

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm926_processor_functions, #object
arm926_processor_functions:
	.word	v5tj_early_abort
	.word	cpu_arm926_proc_init
	.word	cpu_arm926_proc_fin
	.word	cpu_arm926_reset
	.word	cpu_arm926_do_idle
	.word	cpu_arm926_dcache_clean_area
	.word	cpu_arm926_switch_mm
	.word	cpu_arm926_set_pte
	.size	arm926_processor_functions, . - arm926_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv5tej"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v5"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_arm926_name, #object
cpu_arm926_name:
	.ascii	"ARM926EJ-S"
#ifndef CONFIG_CPU_ICACHE_DISABLE
	.ascii	"i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
	.ascii	"d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	.ascii	"(wt)"
#else
	.ascii	"(wb)"
#endif
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	.ascii	"RR"
#endif
#endif
	.ascii	"\0"
	.size	cpu_arm926_name, . - cpu_arm926_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm926_proc_info,#object
__arm926_proc_info:
	.long	0x41069260			@ ARM926EJ-S (v5TEJ)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm926_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
	.long	cpu_arm926_name
	.long	arm926_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm926_cache_fns
	.size	__arm926_proc_info, . - __arm926_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
	3	*
	4	* Copyright (C) 1999-2001 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	6	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*
	23	* These are the low level assembler for performing cache and TLB
	24	* functions on the arm926.
	25	*
	26	* CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
	27	*/
	28	#include <linux/linkage.h>
	29	#include <linux/config.h>
	30	#include <linux/init.h>
	31	#include <asm/assembler.h>
74945c86	32	#include <asm/pgtable-hwdef.h>
1da177e4 LT	33	#include <asm/pgtable.h>
1da177e4 LT	34	#include <asm/procinfo.h>
1da177e4 LT	35	#include <asm/page.h>
	36	#include <asm/ptrace.h>
	37	#include "proc-macros.S"
	38
	39	/*
	40	* This is the maximum size of an area which will be invalidated
	41	* using the single invalidate entry instructions. Anything larger
	42	* than this, and we go for the whole cache.
	43	*
	44	* This value should be chosen such that we choose the cheapest
	45	* alternative.
	46	*/
	47	#define CACHE_DLIMIT 16384
	48
	49	/*
	50	* the cache line size of the I and D cache
	51	*/
	52	#define CACHE_DLINESIZE 32
	53
	54	.text
	55	/*
	56	* cpu_arm926_proc_init()
	57	*/
	58	ENTRY(cpu_arm926_proc_init)
	59	mov pc, lr
	60
	61	/*
	62	* cpu_arm926_proc_fin()
	63	*/
	64	ENTRY(cpu_arm926_proc_fin)
	65	stmfd sp!, {lr}
	66	mov ip, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE
	67	msr cpsr_c, ip
	68	bl arm926_flush_kern_cache_all
	69	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	70	bic r0, r0, #0x1000 @ ...i............
	71	bic r0, r0, #0x000e @ ............wca.
	72	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	73	ldmfd sp!, {pc}
	74
	75	/*
	76	* cpu_arm926_reset(loc)
	77	*
	78	* Perform a soft reset of the system. Put the CPU into the
	79	* same state as it would be if it had been reset, and branch
	80	* to what would be the reset vector.
	81	*
	82	* loc: location to jump to for soft reset
	83	*/
	84	.align 5
	85	ENTRY(cpu_arm926_reset)
	86	mov ip, #0
	87	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	88	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	89	#ifdef CONFIG_MMU
1da177e4	90	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	91	#endif
1da177e4 LT	92	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	93	bic ip, ip, #0x000f @ ............wcam
	94	bic ip, ip, #0x1100 @ ...i...s........
	95	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	96	mov pc, r0
	97
	98	/*
	99	* cpu_arm926_do_idle()
	100	*
	101	* Called with IRQs disabled
	102	*/
	103	.align 10
	104	ENTRY(cpu_arm926_do_idle)
	105	mov r0, #0
	106	mrc p15, 0, r1, c1, c0, 0 @ Read control register
	107	mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
	108	bic r2, r1, #1 << 12
	109	mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
	110	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	111	mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
	112	mov pc, lr
	113
	114	/*
	115	* flush_user_cache_all()
	116	*
	117	* Clean and invalidate all cache entries in a particular
	118	* address space.
	119	*/
	120	ENTRY(arm926_flush_user_cache_all)
	121	/* FALLTHROUGH */
	122
	123	/*
	124	* flush_kern_cache_all()
	125	*
	126	* Clean and invalidate the entire cache.
	127	*/
	128	ENTRY(arm926_flush_kern_cache_all)
	129	mov r2, #VM_EXEC
	130	mov ip, #0
	131	__flush_whole_cache:
	132	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	133	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	134	#else
	135	1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
	136	bne 1b
	137	#endif
	138	tst r2, #VM_EXEC
	139	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	140	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	141	mov pc, lr
	142
	143	/*
	144	* flush_user_cache_range(start, end, flags)
	145	*
	146	* Clean and invalidate a range of cache entries in the
	147	* specified address range.
	148	*
	149	* - start - start address (inclusive)
	150	* - end - end address (exclusive)
	151	* - flags - vm_flags describing address space
	152	*/
	153	ENTRY(arm926_flush_user_cache_range)
	154	mov ip, #0
	155	sub r3, r1, r0 @ calculate total size
156	cmp r3, #CACHE_DLIMIT
157	bgt __flush_whole_cache
158	1: tst r2, #VM_EXEC
159	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
160	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
161	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
162	add r0, r0, #CACHE_DLINESIZE
163	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
164	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
165	add r0, r0, #CACHE_DLINESIZE
166	#else
167	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
168	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
169	add r0, r0, #CACHE_DLINESIZE
170	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
171	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
172	add r0, r0, #CACHE_DLINESIZE
173	#endif
174	cmp r0, r1
175	blo 1b
176	tst r2, #VM_EXEC
177	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
178	mov pc, lr
179
180	/*
181	* coherent_kern_range(start, end)
182	*
183	* Ensure coherency between the Icache and the Dcache in the
184	* region described by start, end. If you have non-snooping
185	* Harvard caches, you need to implement this function.
186	*
187	* - start - virtual start address
188	* - end - virtual end address
189	*/
190	ENTRY(arm926_coherent_kern_range)
191	/* FALLTHROUGH */
192
193	/*
194	* coherent_user_range(start, end)
195	*
196	* Ensure coherency between the Icache and the Dcache in the
197	* region described by start, end. If you have non-snooping
198	* Harvard caches, you need to implement this function.
199	*
200	* - start - virtual start address
201	* - end - virtual end address
202	*/
203	ENTRY(arm926_coherent_user_range)
204	bic r0, r0, #CACHE_DLINESIZE - 1
205	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
206	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
207	add r0, r0, #CACHE_DLINESIZE
208	cmp r0, r1
209	blo 1b
210	mcr p15, 0, r0, c7, c10, 4 @ drain WB
211	mov pc, lr
212
213	/*
214	* flush_kern_dcache_page(void *page)
215	*
216	* Ensure no D cache aliasing occurs, either with itself or
217	* the I cache
218	*
219	* - addr - page aligned address
220	*/
221	ENTRY(arm926_flush_kern_dcache_page)
222	add r1, r0, #PAGE_SZ
223	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
224	add r0, r0, #CACHE_DLINESIZE
225	cmp r0, r1
226	blo 1b
227	mov r0, #0
228	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
229	mcr p15, 0, r0, c7, c10, 4 @ drain WB
230	mov pc, lr
231
232	/*
233	* dma_inv_range(start, end)
234	*
235	* Invalidate (discard) the specified virtual address range.
236	* May not write back any entries. If 'start' or 'end'
237	* are not cache line aligned, those lines must be written
238	* back.
239	*
240	* - start - virtual start address
241	* - end - virtual end address
242	*
243	* (same as v4wb)
244	*/
245	ENTRY(arm926_dma_inv_range)
246	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
247	tst r0, #CACHE_DLINESIZE - 1
248	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
249	tst r1, #CACHE_DLINESIZE - 1
250	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
251	#endif
252	bic r0, r0, #CACHE_DLINESIZE - 1
253	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
254	add r0, r0, #CACHE_DLINESIZE
255	cmp r0, r1
256	blo 1b
257	mcr p15, 0, r0, c7, c10, 4 @ drain WB
258	mov pc, lr
259
260	/*
261	* dma_clean_range(start, end)
262	*
263	* Clean the specified virtual address range.
264	*
265	* - start - virtual start address
266	* - end - virtual end address
267	*
268	* (same as v4wb)
269	*/
270	ENTRY(arm926_dma_clean_range)
271	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
272	bic r0, r0, #CACHE_DLINESIZE - 1
273	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
274	add r0, r0, #CACHE_DLINESIZE
275	cmp r0, r1
276	blo 1b
277	#endif
278	mcr p15, 0, r0, c7, c10, 4 @ drain WB
279	mov pc, lr
280
281	/*
282	* dma_flush_range(start, end)
283	*
284	* Clean and invalidate the specified virtual address range.
285	*
286	* - start - virtual start address
287	* - end - virtual end address
288	*/
289	ENTRY(arm926_dma_flush_range)
290	bic r0, r0, #CACHE_DLINESIZE - 1
291	1:
292	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
293	mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
294	#else
295	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
296	#endif
297	add r0, r0, #CACHE_DLINESIZE
298	cmp r0, r1
299	blo 1b
300	mcr p15, 0, r0, c7, c10, 4 @ drain WB
301	mov pc, lr
302
303	ENTRY(arm926_cache_fns)
304	.long arm926_flush_kern_cache_all
305	.long arm926_flush_user_cache_all
306	.long arm926_flush_user_cache_range
307	.long arm926_coherent_kern_range
308	.long arm926_coherent_user_range
309	.long arm926_flush_kern_dcache_page
310	.long arm926_dma_inv_range
311	.long arm926_dma_clean_range
312	.long arm926_dma_flush_range
313
314	ENTRY(cpu_arm926_dcache_clean_area)
315	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
316	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
317	add r0, r0, #CACHE_DLINESIZE
318	subs r1, r1, #CACHE_DLINESIZE
319	bhi 1b
320	#endif
321	mcr p15, 0, r0, c7, c10, 4 @ drain WB
322	mov pc, lr
323
324	/* =============================== PageTable ============================== */
325
326	/*
327	* cpu_arm926_switch_mm(pgd)
328	*
329	* Set the translation base pointer to be as described by pgd.
330	*
331	* pgd: new page tables
332	*/
333	.align 5
334	ENTRY(cpu_arm926_switch_mm)
d090ddda	335	#ifdef CONFIG_MMU
1da177e4 LT	336	mov ip, #0
	337	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	338	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	339	#else
	340	@ && 'Clean & Invalidate whole DCache'
	341	1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
	342	bne 1b
	343	#endif
	344	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	345	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	346	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	347	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	348	#endif
1da177e4 LT	349	mov pc, lr
	350
	351	/*
	352	* cpu_arm926_set_pte(ptep, pte)
	353	*
	354	* Set a PTE and flush it out
	355	*/
	356	.align 5
	357	ENTRY(cpu_arm926_set_pte)
d090ddda	358	#ifdef CONFIG_MMU
1da177e4 LT	359	str r1, [r0], #-2048 @ linux version
	360
	361	eor r1, r1, #L_PTE_PRESENT \| L_PTE_YOUNG \| L_PTE_WRITE \| L_PTE_DIRTY
	362
	363	bic r2, r1, #PTE_SMALL_AP_MASK
	364	bic r2, r2, #PTE_TYPE_MASK
	365	orr r2, r2, #PTE_TYPE_SMALL
	366
	367	tst r1, #L_PTE_USER @ User?
	368	orrne r2, r2, #PTE_SMALL_AP_URO_SRW
	369
	370	tst r1, #L_PTE_WRITE \| L_PTE_DIRTY @ Write and Dirty?
	371	orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
	372
	373	tst r1, #L_PTE_PRESENT \| L_PTE_YOUNG @ Present and Young?
	374	movne r2, #0
	375
	376	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	377	eor r3, r2, #0x0a @ C & small page?
	378	tst r3, #0x0b
	379	biceq r2, r2, #4
	380	#endif
	381	str r2, [r0] @ hardware version
	382	mov r0, r0
	383	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	384	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	385	#endif
	386	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	387	#endif
1da177e4 LT	388	mov pc, lr
	389
	390	__INIT
	391
	392	.type __arm926_setup, #function
	393	__arm926_setup:
	394	mov r0, #0
	395	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	396	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	397	#ifdef CONFIG_MMU
1da177e4	398	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	399	#endif
1da177e4 LT	400
	401
	402	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	403	mov r0, #4 @ disable write-back on caches explicitly
	404	mcr p15, 7, r0, c15, c0, 0
	405	#endif
	406
	407	mrc p15, 0, r0, c1, c0 @ get control register v4
	408	ldr r5, arm926_cr1_clear
	409	bic r0, r0, r5
	410	ldr r5, arm926_cr1_set
	411	orr r0, r0, r5
	412	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	413	orr r0, r0, #0x4000 @ .1.. .... .... ....
	414	#endif
	415	mov pc, lr
	416	.size __arm926_setup, . - __arm926_setup
	417
	418	/*
	419	* R
	420	* .RVI ZFRS BLDP WCAM
	421	* .011 0001 ..11 0101
	422	*
	423	*/
	424	.type arm926_cr1_clear, #object
	425	.type arm926_cr1_set, #object
	426	arm926_cr1_clear:
	427	.word 0x7f3f
	428	arm926_cr1_set:
	429	.word 0x3135
	430
	431	__INITDATA
	432
	433	/*
	434	* Purpose : Function pointers used to access above functions - all calls
	435	* come through these
	436	*/
	437	.type arm926_processor_functions, #object
	438	arm926_processor_functions:
	439	.word v5tj_early_abort
	440	.word cpu_arm926_proc_init
	441	.word cpu_arm926_proc_fin
	442	.word cpu_arm926_reset
	443	.word cpu_arm926_do_idle
	444	.word cpu_arm926_dcache_clean_area
	445	.word cpu_arm926_switch_mm
	446	.word cpu_arm926_set_pte
	447	.size arm926_processor_functions, . - arm926_processor_functions
	448
	449	.section ".rodata"
	450
	451	.type cpu_arch_name, #object
	452	cpu_arch_name:
	453	.asciz "armv5tej"
	454	.size cpu_arch_name, . - cpu_arch_name
	455
	456	.type cpu_elf_name, #object
	457	cpu_elf_name:
	458	.asciz "v5"
	459	.size cpu_elf_name, . - cpu_elf_name
	460
	461	.type cpu_arm926_name, #object
	462	cpu_arm926_name:
	463	.ascii "ARM926EJ-S"
464	#ifndef CONFIG_CPU_ICACHE_DISABLE
465	.ascii "i"
466	#endif
467	#ifndef CONFIG_CPU_DCACHE_DISABLE
468	.ascii "d"
469	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
470	.ascii "(wt)"
471	#else
472	.ascii "(wb)"
473	#endif
474	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
475	.ascii "RR"
476	#endif
477	#endif
478	.ascii "\0"
479	.size cpu_arm926_name, . - cpu_arm926_name
480
481	.align
482
02b7dd12	483	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	484
	485	.type __arm926_proc_info,#object
	486	__arm926_proc_info:
	487	.long 0x41069260 @ ARM926EJ-S (v5TEJ)
	488	.long 0xff0ffff0
	489	.long PMD_TYPE_SECT \| \
	490	PMD_SECT_BUFFERABLE \| \
	491	PMD_SECT_CACHEABLE \| \
	492	PMD_BIT4 \| \
	493	PMD_SECT_AP_WRITE \| \
	494	PMD_SECT_AP_READ
	495	b __arm926_setup
	496	.long cpu_arch_name
	497	.long cpu_elf_name
	498	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_JAVA
	499	.long cpu_arm926_name
	500	.long arm926_processor_functions
	501	.long v4wbi_tlb_fns
	502	.long v4wb_user_fns
	503	.long arm926_cache_fns
	504	.size __arm926_proc_info, . - __arm926_proc_info