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1 | /* |
2 | * linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526 | |
3 | * | |
4 | * Written by : Luke Lee | |
5 | * Copyright (C) 2005 Faraday Corp. | |
6 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * | |
14 | * These are the low level assembler for performing cache and TLB | |
15 | * functions on the fa526. | |
16 | */ | |
17 | #include <linux/linkage.h> | |
18 | #include <linux/init.h> | |
19 | #include <asm/assembler.h> | |
20 | #include <asm/hwcap.h> | |
21 | #include <asm/pgtable-hwdef.h> | |
22 | #include <asm/pgtable.h> | |
23 | #include <asm/page.h> | |
24 | #include <asm/ptrace.h> | |
25 | #include <asm/system.h> | |
26 | ||
27 | #include "proc-macros.S" | |
28 | ||
29 | #define CACHE_DLINESIZE 16 | |
30 | ||
31 | .text | |
32 | /* | |
33 | * cpu_fa526_proc_init() | |
34 | */ | |
35 | ENTRY(cpu_fa526_proc_init) | |
36 | mov pc, lr | |
37 | ||
38 | /* | |
39 | * cpu_fa526_proc_fin() | |
40 | */ | |
41 | ENTRY(cpu_fa526_proc_fin) | |
28853ac8 PZ |
42 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
43 | bic r0, r0, #0x1000 @ ...i............ | |
44 | bic r0, r0, #0x000e @ ............wca. | |
45 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
46 | nop | |
47 | nop | |
9ca03a21 | 48 | mov pc, lr |
28853ac8 PZ |
49 | |
50 | /* | |
51 | * cpu_fa526_reset(loc) | |
52 | * | |
53 | * Perform a soft reset of the system. Put the CPU into the | |
54 | * same state as it would be if it had been reset, and branch | |
55 | * to what would be the reset vector. | |
56 | * | |
57 | * loc: location to jump to for soft reset | |
58 | */ | |
59 | .align 4 | |
60 | ENTRY(cpu_fa526_reset) | |
61 | /* TODO: Use CP8 if possible... */ | |
62 | mov ip, #0 | |
63 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
64 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
65 | #ifdef CONFIG_MMU | |
66 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | |
67 | #endif | |
68 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register | |
69 | bic ip, ip, #0x000f @ ............wcam | |
70 | bic ip, ip, #0x1100 @ ...i...s........ | |
71 | bic ip, ip, #0x0800 @ BTB off | |
72 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
73 | nop | |
74 | nop | |
75 | mov pc, r0 | |
76 | ||
77 | /* | |
78 | * cpu_fa526_do_idle() | |
79 | */ | |
80 | .align 4 | |
81 | ENTRY(cpu_fa526_do_idle) | |
82 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt | |
83 | mov pc, lr | |
84 | ||
85 | ||
86 | ENTRY(cpu_fa526_dcache_clean_area) | |
87 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
88 | add r0, r0, #CACHE_DLINESIZE | |
89 | subs r1, r1, #CACHE_DLINESIZE | |
90 | bhi 1b | |
91 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
92 | mov pc, lr | |
93 | ||
94 | /* =============================== PageTable ============================== */ | |
95 | ||
96 | /* | |
97 | * cpu_fa526_switch_mm(pgd) | |
98 | * | |
99 | * Set the translation base pointer to be as described by pgd. | |
100 | * | |
101 | * pgd: new page tables | |
102 | */ | |
103 | .align 4 | |
104 | ENTRY(cpu_fa526_switch_mm) | |
105 | #ifdef CONFIG_MMU | |
106 | mov ip, #0 | |
107 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
108 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
109 | #else | |
110 | mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache | |
111 | #endif | |
112 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
113 | mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed | |
114 | mcr p15, 0, ip, c7, c10, 4 @ data write barrier | |
115 | mcr p15, 0, ip, c7, c5, 4 @ prefetch flush | |
116 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | |
117 | mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB | |
118 | #endif | |
119 | mov pc, lr | |
120 | ||
121 | /* | |
122 | * cpu_fa526_set_pte_ext(ptep, pte, ext) | |
123 | * | |
124 | * Set a PTE and flush it out | |
125 | */ | |
126 | .align 4 | |
127 | ENTRY(cpu_fa526_set_pte_ext) | |
128 | #ifdef CONFIG_MMU | |
129 | armv3_set_pte_ext | |
130 | mov r0, r0 | |
131 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
132 | mov r0, #0 | |
133 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
134 | #endif | |
135 | mov pc, lr | |
136 | ||
5085f3ff | 137 | __CPUINIT |
28853ac8 PZ |
138 | |
139 | .type __fa526_setup, #function | |
140 | __fa526_setup: | |
141 | /* On return of this routine, r0 must carry correct flags for CFG register */ | |
142 | mov r0, #0 | |
143 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 | |
144 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 | |
145 | #ifdef CONFIG_MMU | |
146 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 | |
147 | #endif | |
148 | mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM | |
149 | ||
150 | mov r0, #1 | |
151 | mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR | |
152 | ||
153 | mov r0, #0 | |
154 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All | |
155 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | |
156 | mcr p15, 0, r0, c7, c5, 4 @ prefetch flush | |
157 | ||
158 | mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client | |
159 | mcr p15, 0, r0, c3, c0 @ load domain access register | |
160 | ||
161 | mrc p15, 0, r0, c1, c0 @ get control register v4 | |
162 | ldr r5, fa526_cr1_clear | |
163 | bic r0, r0, r5 | |
164 | ldr r5, fa526_cr1_set | |
165 | orr r0, r0, r5 | |
166 | mov pc, lr | |
167 | .size __fa526_setup, . - __fa526_setup | |
168 | ||
169 | /* | |
170 | * .RVI ZFRS BLDP WCAM | |
171 | * ..11 1001 .111 1101 | |
172 | * | |
173 | */ | |
174 | .type fa526_cr1_clear, #object | |
175 | .type fa526_cr1_set, #object | |
176 | fa526_cr1_clear: | |
177 | .word 0x3f3f | |
178 | fa526_cr1_set: | |
179 | .word 0x397D | |
180 | ||
181 | __INITDATA | |
182 | ||
183 | /* | |
184 | * Purpose : Function pointers used to access above functions - all calls | |
185 | * come through these | |
186 | */ | |
187 | .type fa526_processor_functions, #object | |
188 | fa526_processor_functions: | |
189 | .word v4_early_abort | |
4fb28474 | 190 | .word legacy_pabort |
28853ac8 PZ |
191 | .word cpu_fa526_proc_init |
192 | .word cpu_fa526_proc_fin | |
193 | .word cpu_fa526_reset | |
194 | .word cpu_fa526_do_idle | |
195 | .word cpu_fa526_dcache_clean_area | |
196 | .word cpu_fa526_switch_mm | |
197 | .word cpu_fa526_set_pte_ext | |
f6b0fa02 RK |
198 | .word 0 |
199 | .word 0 | |
200 | .word 0 | |
28853ac8 PZ |
201 | .size fa526_processor_functions, . - fa526_processor_functions |
202 | ||
203 | .section ".rodata" | |
204 | ||
205 | .type cpu_arch_name, #object | |
206 | cpu_arch_name: | |
207 | .asciz "armv4" | |
208 | .size cpu_arch_name, . - cpu_arch_name | |
209 | ||
210 | .type cpu_elf_name, #object | |
211 | cpu_elf_name: | |
212 | .asciz "v4" | |
213 | .size cpu_elf_name, . - cpu_elf_name | |
214 | ||
215 | .type cpu_fa526_name, #object | |
216 | cpu_fa526_name: | |
217 | .asciz "FA526" | |
218 | .size cpu_fa526_name, . - cpu_fa526_name | |
219 | ||
220 | .align | |
221 | ||
222 | .section ".proc.info.init", #alloc, #execinstr | |
223 | ||
224 | .type __fa526_proc_info,#object | |
225 | __fa526_proc_info: | |
226 | .long 0x66015261 | |
227 | .long 0xff01fff1 | |
228 | .long PMD_TYPE_SECT | \ | |
229 | PMD_SECT_BUFFERABLE | \ | |
230 | PMD_SECT_CACHEABLE | \ | |
231 | PMD_BIT4 | \ | |
232 | PMD_SECT_AP_WRITE | \ | |
233 | PMD_SECT_AP_READ | |
234 | .long PMD_TYPE_SECT | \ | |
235 | PMD_BIT4 | \ | |
236 | PMD_SECT_AP_WRITE | \ | |
237 | PMD_SECT_AP_READ | |
238 | b __fa526_setup | |
239 | .long cpu_arch_name | |
240 | .long cpu_elf_name | |
241 | .long HWCAP_SWP | HWCAP_HALF | |
242 | .long cpu_fa526_name | |
243 | .long fa526_processor_functions | |
244 | .long fa_tlb_fns | |
245 | .long fa_user_fns | |
246 | .long fa_cache_fns | |
247 | .size __fa526_proc_info, . - __fa526_proc_info |