[deliverable/linux.git] / arch / arm / mm / proc-sa110.S

/*
 *  linux/arch/arm/mm/proc-sa110.S
 *
 *  Copyright (C) 1997-2002 Russell King
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  MMU functions for SA110
 *
 *  These are the low level assembler for performing cache and TLB
 *  functions on the StrongARM-110.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <mach/hardware.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

/*
 * the cache line size of the I and D cache
 */
#define DCACHELINESIZE	32

	.text

/*
 * cpu_sa110_proc_init()
 */
ENTRY(cpu_sa110_proc_init)
	mov	r0, #0
	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
	mov	pc, lr

/*
 * cpu_sa110_proc_fin()
 */
ENTRY(cpu_sa110_proc_fin)
	mov	r0, #0
	mcr	p15, 0, r0, c15, c2, 2		@ Disable clock switching
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_sa110_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_sa110_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_sa110_do_idle(type)
 *
 * Cause the processor to idle
 *
 * type: call type:
 *   0 = slow idle
 *   1 = fast idle
 *   2 = switch to slow processor clock
 *   3 = switch to fast processor clock
 */
	.align	5

ENTRY(cpu_sa110_do_idle)
	mcr	p15, 0, ip, c15, c2, 2		@ disable clock switching
	ldr	r1, =UNCACHEABLE_ADDR		@ load from uncacheable loc
	ldr	r1, [r1, #0]			@ force switch to MCLK
	mov	r0, r0				@ safety
	mov	r0, r0				@ safety
	mov	r0, r0				@ safety
	mcr	p15, 0, r0, c15, c8, 2		@ Wait for interrupt, cache aligned
	mov	r0, r0				@ safety
	mov	r0, r0				@ safety
	mov	r0, r0				@ safety
	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
	mov	pc, lr

/* ================================= CACHE ================================ */

/*
 * cpu_sa110_dcache_clean_area(addr,sz)
 *
 * Clean the specified entry of any caches such that the MMU
 * translation fetches will obtain correct data.
 *
 * addr: cache-unaligned virtual address
 */
	.align	5
ENTRY(cpu_sa110_dcache_clean_area)
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #DCACHELINESIZE
	subs	r1, r1, #DCACHELINESIZE
	bhi	1b
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_sa110_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_sa110_switch_mm)
#ifdef CONFIG_MMU
	str	lr, [sp, #-4]!
	bl	v4wb_flush_kern_cache_all	@ clears IP
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
	ldr	pc, [sp], #4
#else
	mov	pc, lr
#endif

/*
 * cpu_sa110_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_sa110_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext wc_disable=0
	mov	r0, r0
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif
	mov	pc, lr

	__CPUINIT

	.type	__sa110_setup, #function
__sa110_setup:
	mov	r10, #0
	mcr	p15, 0, r10, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r10, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7		@ invalidate I,D TLBs on v4
#endif

	adr	r5, sa110_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
	mov	pc, lr
	.size	__sa110_setup, . - __sa110_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * ..01 0001 ..11 1101
	 * 
	 */
	.type	sa110_crval, #object
sa110_crval:
	crval	clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions sa110, dabort=v4_early_abort, pabort=legacy_pabort

	.section ".rodata"

	string	cpu_arch_name, "armv4"
	string	cpu_elf_name, "v4"
	string	cpu_sa110_name, "StrongARM-110"

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__sa110_proc_info,#object
__sa110_proc_info:
	.long	0x4401a100
	.long	0xfffffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__sa110_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
	.long	cpu_sa110_name
	.long	sa110_processor_functions
	.long	v4wb_tlb_fns
	.long	v4wb_user_fns
	.long	v4wb_cache_fns
	.size	__sa110_proc_info, . - __sa110_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-sa110.S
	3	*
	4	* Copyright (C) 1997-2002 Russell King
d090ddda	5	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* MMU functions for SA110
	12	*
	13	* These are the low level assembler for performing cache and TLB
	14	* functions on the StrongARM-110.
	15	*/
	16	#include <linux/linkage.h>
	17	#include <linux/init.h>
	18	#include <asm/assembler.h>
e6ae744d	19	#include <asm/asm-offsets.h>
5ec9407d	20	#include <asm/hwcap.h>
a09e64fb	21	#include <mach/hardware.h>
74945c86	22	#include <asm/pgtable-hwdef.h>
1da177e4 LT	23	#include <asm/pgtable.h>
	24	#include <asm/ptrace.h>
	25
bb8d5a55 TG	26	#include "proc-macros.S"
bb8d5a55 TG	27
1da177e4 LT	28	/*
	29	* the cache line size of the I and D cache
	30	*/
	31	#define DCACHELINESIZE 32
95f3df6b	32
1da177e4 LT	33	.text
	34
	35	/*
	36	* cpu_sa110_proc_init()
	37	*/
	38	ENTRY(cpu_sa110_proc_init)
	39	mov r0, #0
	40	mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
	41	mov pc, lr
	42
	43	/*
	44	* cpu_sa110_proc_fin()
	45	*/
	46	ENTRY(cpu_sa110_proc_fin)
9ca03a21	47	mov r0, #0
1da177e4 LT	48	mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
	49	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	50	bic r0, r0, #0x1000 @ ...i............
	51	bic r0, r0, #0x000e @ ............wca.
	52	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	53	mov pc, lr
1da177e4 LT	54
	55	/*
	56	* cpu_sa110_reset(loc)
	57	*
	58	* Perform a soft reset of the system. Put the CPU into the
	59	* same state as it would be if it had been reset, and branch
	60	* to what would be the reset vector.
	61	*
	62	* loc: location to jump to for soft reset
	63	*/
	64	.align 5
	65	ENTRY(cpu_sa110_reset)
	66	mov ip, #0
	67	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	68	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	69	#ifdef CONFIG_MMU
1da177e4	70	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	71	#endif
1da177e4 LT	72	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	73	bic ip, ip, #0x000f @ ............wcam
	74	bic ip, ip, #0x1100 @ ...i...s........
	75	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	76	mov pc, r0
	77
	78	/*
	79	* cpu_sa110_do_idle(type)
	80	*
	81	* Cause the processor to idle
	82	*
	83	* type: call type:
	84	* 0 = slow idle
	85	* 1 = fast idle
	86	* 2 = switch to slow processor clock
	87	* 3 = switch to fast processor clock
	88	*/
	89	.align 5
	90
	91	ENTRY(cpu_sa110_do_idle)
	92	mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
	93	ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc
	94	ldr r1, [r1, #0] @ force switch to MCLK
	95	mov r0, r0 @ safety
	96	mov r0, r0 @ safety
	97	mov r0, r0 @ safety
	98	mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
	99	mov r0, r0 @ safety
	100	mov r0, r0 @ safety
	101	mov r0, r0 @ safety
	102	mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
	103	mov pc, lr
	104
	105	/* ================================= CACHE ================================ */
	106
	107	/*
	108	* cpu_sa110_dcache_clean_area(addr,sz)
	109	*
	110	* Clean the specified entry of any caches such that the MMU
	111	* translation fetches will obtain correct data.
	112	*
	113	* addr: cache-unaligned virtual address
	114	*/
	115	.align 5
	116	ENTRY(cpu_sa110_dcache_clean_area)
	117	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	118	add r0, r0, #DCACHELINESIZE
	119	subs r1, r1, #DCACHELINESIZE
	120	bhi 1b
	121	mov pc, lr
	122
	123	/* =============================== PageTable ============================== */
	124
	125	/*
	126	* cpu_sa110_switch_mm(pgd)
	127	*
	128	* Set the translation base pointer to be as described by pgd.
	129	*
	130	* pgd: new page tables
	131	*/
	132	.align 5
	133	ENTRY(cpu_sa110_switch_mm)
d090ddda	134	#ifdef CONFIG_MMU
95f3df6b RK	135	str lr, [sp, #-4]!
95f3df6b RK	136	bl v4wb_flush_kern_cache_all @ clears IP
1da177e4	137	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
95f3df6b RK	138	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
95f3df6b RK	139	ldr pc, [sp], #4
d090ddda HC	140	#else
	141	mov pc, lr
	142	#endif
1da177e4 LT	143
1da177e4 LT	144	/*
ad1ae2fe	145	* cpu_sa110_set_pte_ext(ptep, pte, ext)
1da177e4 LT	146	*
	147	* Set a PTE and flush it out
	148	*/
	149	.align 5
ad1ae2fe	150	ENTRY(cpu_sa110_set_pte_ext)
d090ddda	151	#ifdef CONFIG_MMU
da091653	152	armv3_set_pte_ext wc_disable=0
1da177e4 LT	153	mov r0, r0
	154	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	155	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	156	#endif
1da177e4 LT	157	mov pc, lr
1da177e4 LT	158
5085f3ff	159	__CPUINIT
1da177e4 LT	160
	161	.type __sa110_setup, #function
	162	__sa110_setup:
	163	mov r10, #0
	164	mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
	165	mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
d090ddda	166	#ifdef CONFIG_MMU
1da177e4	167	mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	168	#endif
22b19086 RK	169
	170	adr r5, sa110_crval
	171	ldmia r5, {r5, r6}
1da177e4	172	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	173	bic r0, r0, r5
22b19086	174	orr r0, r0, r6
1da177e4 LT	175	mov pc, lr
	176	.size __sa110_setup, . - __sa110_setup
	177
	178	/*
	179	* R
	180	* .RVI ZFRS BLDP WCAM
	181	* ..01 0001 ..11 1101
	182	*
	183	*/
22b19086 RK	184	.type sa110_crval, #object
	185	sa110_crval:
	186	crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
1da177e4 LT	187
	188	__INITDATA
	189
5973ba58 DM	190	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
5973ba58 DM	191	define_processor_functions sa110, dabort=v4_early_abort, pabort=legacy_pabort
1da177e4 LT	192
	193	.section ".rodata"
	194
5973ba58 DM	195	string cpu_arch_name, "armv4"
	196	string cpu_elf_name, "v4"
	197	string cpu_sa110_name, "StrongARM-110"
1da177e4 LT	198
	199	.align
	200
02b7dd12	201	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	202
	203	.type __sa110_proc_info,#object
	204	__sa110_proc_info:
	205	.long 0x4401a100
	206	.long 0xfffffff0
	207	.long PMD_TYPE_SECT \| \
	208	PMD_SECT_BUFFERABLE \| \
	209	PMD_SECT_CACHEABLE \| \
	210	PMD_SECT_AP_WRITE \| \
	211	PMD_SECT_AP_READ
8799ee9f RK	212	.long PMD_TYPE_SECT \| \
	213	PMD_SECT_AP_WRITE \| \
	214	PMD_SECT_AP_READ
1da177e4 LT	215	b __sa110_setup
	216	.long cpu_arch_name
	217	.long cpu_elf_name
	218	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_26BIT \| HWCAP_FAST_MULT
	219	.long cpu_sa110_name
	220	.long sa110_processor_functions
	221	.long v4wb_tlb_fns
	222	.long v4wb_user_fns
	223	.long v4wb_cache_fns
	224	.size __sa110_proc_info, . - __sa110_proc_info