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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-sa110.S | |
3 | * | |
4 | * Copyright (C) 1997-2002 Russell King | |
d090ddda | 5 | * hacked for non-paged-MM by Hyok S. Choi, 2003. |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * MMU functions for SA110 | |
12 | * | |
13 | * These are the low level assembler for performing cache and TLB | |
14 | * functions on the StrongARM-110. | |
15 | */ | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/init.h> | |
18 | #include <asm/assembler.h> | |
e6ae744d | 19 | #include <asm/asm-offsets.h> |
5ec9407d | 20 | #include <asm/hwcap.h> |
a09e64fb | 21 | #include <mach/hardware.h> |
74945c86 | 22 | #include <asm/pgtable-hwdef.h> |
1da177e4 LT |
23 | #include <asm/pgtable.h> |
24 | #include <asm/ptrace.h> | |
25 | ||
bb8d5a55 TG |
26 | #include "proc-macros.S" |
27 | ||
1da177e4 LT |
28 | /* |
29 | * the cache line size of the I and D cache | |
30 | */ | |
31 | #define DCACHELINESIZE 32 | |
95f3df6b | 32 | |
1da177e4 LT |
33 | .text |
34 | ||
35 | /* | |
36 | * cpu_sa110_proc_init() | |
37 | */ | |
38 | ENTRY(cpu_sa110_proc_init) | |
39 | mov r0, #0 | |
40 | mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching | |
6ebbf2ce | 41 | ret lr |
1da177e4 LT |
42 | |
43 | /* | |
44 | * cpu_sa110_proc_fin() | |
45 | */ | |
46 | ENTRY(cpu_sa110_proc_fin) | |
9ca03a21 | 47 | mov r0, #0 |
1da177e4 LT |
48 | mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching |
49 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | |
50 | bic r0, r0, #0x1000 @ ...i............ | |
51 | bic r0, r0, #0x000e @ ............wca. | |
52 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
6ebbf2ce | 53 | ret lr |
1da177e4 LT |
54 | |
55 | /* | |
56 | * cpu_sa110_reset(loc) | |
57 | * | |
58 | * Perform a soft reset of the system. Put the CPU into the | |
59 | * same state as it would be if it had been reset, and branch | |
60 | * to what would be the reset vector. | |
61 | * | |
62 | * loc: location to jump to for soft reset | |
63 | */ | |
64 | .align 5 | |
1a4baafa | 65 | .pushsection .idmap.text, "ax" |
1da177e4 LT |
66 | ENTRY(cpu_sa110_reset) |
67 | mov ip, #0 | |
68 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
69 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
d090ddda | 70 | #ifdef CONFIG_MMU |
1da177e4 | 71 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
d090ddda | 72 | #endif |
1da177e4 LT |
73 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
74 | bic ip, ip, #0x000f @ ............wcam | |
75 | bic ip, ip, #0x1100 @ ...i...s........ | |
76 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
6ebbf2ce | 77 | ret r0 |
1a4baafa WD |
78 | ENDPROC(cpu_sa110_reset) |
79 | .popsection | |
1da177e4 LT |
80 | |
81 | /* | |
82 | * cpu_sa110_do_idle(type) | |
83 | * | |
84 | * Cause the processor to idle | |
85 | * | |
86 | * type: call type: | |
87 | * 0 = slow idle | |
88 | * 1 = fast idle | |
89 | * 2 = switch to slow processor clock | |
90 | * 3 = switch to fast processor clock | |
91 | */ | |
92 | .align 5 | |
93 | ||
94 | ENTRY(cpu_sa110_do_idle) | |
95 | mcr p15, 0, ip, c15, c2, 2 @ disable clock switching | |
96 | ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc | |
97 | ldr r1, [r1, #0] @ force switch to MCLK | |
98 | mov r0, r0 @ safety | |
99 | mov r0, r0 @ safety | |
100 | mov r0, r0 @ safety | |
101 | mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned | |
102 | mov r0, r0 @ safety | |
103 | mov r0, r0 @ safety | |
104 | mov r0, r0 @ safety | |
105 | mcr p15, 0, r0, c15, c1, 2 @ enable clock switching | |
6ebbf2ce | 106 | ret lr |
1da177e4 LT |
107 | |
108 | /* ================================= CACHE ================================ */ | |
109 | ||
110 | /* | |
111 | * cpu_sa110_dcache_clean_area(addr,sz) | |
112 | * | |
113 | * Clean the specified entry of any caches such that the MMU | |
114 | * translation fetches will obtain correct data. | |
115 | * | |
116 | * addr: cache-unaligned virtual address | |
117 | */ | |
118 | .align 5 | |
119 | ENTRY(cpu_sa110_dcache_clean_area) | |
120 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
121 | add r0, r0, #DCACHELINESIZE | |
122 | subs r1, r1, #DCACHELINESIZE | |
123 | bhi 1b | |
6ebbf2ce | 124 | ret lr |
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125 | |
126 | /* =============================== PageTable ============================== */ | |
127 | ||
128 | /* | |
129 | * cpu_sa110_switch_mm(pgd) | |
130 | * | |
131 | * Set the translation base pointer to be as described by pgd. | |
132 | * | |
133 | * pgd: new page tables | |
134 | */ | |
135 | .align 5 | |
136 | ENTRY(cpu_sa110_switch_mm) | |
d090ddda | 137 | #ifdef CONFIG_MMU |
95f3df6b RK |
138 | str lr, [sp, #-4]! |
139 | bl v4wb_flush_kern_cache_all @ clears IP | |
1da177e4 | 140 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
95f3df6b RK |
141 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
142 | ldr pc, [sp], #4 | |
d090ddda | 143 | #else |
6ebbf2ce | 144 | ret lr |
d090ddda | 145 | #endif |
1da177e4 LT |
146 | |
147 | /* | |
ad1ae2fe | 148 | * cpu_sa110_set_pte_ext(ptep, pte, ext) |
1da177e4 LT |
149 | * |
150 | * Set a PTE and flush it out | |
151 | */ | |
152 | .align 5 | |
ad1ae2fe | 153 | ENTRY(cpu_sa110_set_pte_ext) |
d090ddda | 154 | #ifdef CONFIG_MMU |
da091653 | 155 | armv3_set_pte_ext wc_disable=0 |
1da177e4 LT |
156 | mov r0, r0 |
157 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
158 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
d090ddda | 159 | #endif |
6ebbf2ce | 160 | ret lr |
1da177e4 | 161 | |
1da177e4 LT |
162 | .type __sa110_setup, #function |
163 | __sa110_setup: | |
164 | mov r10, #0 | |
165 | mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 | |
166 | mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4 | |
d090ddda | 167 | #ifdef CONFIG_MMU |
1da177e4 | 168 | mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 |
d090ddda | 169 | #endif |
22b19086 RK |
170 | |
171 | adr r5, sa110_crval | |
172 | ldmia r5, {r5, r6} | |
1da177e4 | 173 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
1da177e4 | 174 | bic r0, r0, r5 |
22b19086 | 175 | orr r0, r0, r6 |
6ebbf2ce | 176 | ret lr |
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177 | .size __sa110_setup, . - __sa110_setup |
178 | ||
179 | /* | |
180 | * R | |
181 | * .RVI ZFRS BLDP WCAM | |
182 | * ..01 0001 ..11 1101 | |
183 | * | |
184 | */ | |
22b19086 RK |
185 | .type sa110_crval, #object |
186 | sa110_crval: | |
187 | crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130 | |
1da177e4 LT |
188 | |
189 | __INITDATA | |
190 | ||
5973ba58 DM |
191 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
192 | define_processor_functions sa110, dabort=v4_early_abort, pabort=legacy_pabort | |
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193 | |
194 | .section ".rodata" | |
195 | ||
5973ba58 DM |
196 | string cpu_arch_name, "armv4" |
197 | string cpu_elf_name, "v4" | |
198 | string cpu_sa110_name, "StrongARM-110" | |
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199 | |
200 | .align | |
201 | ||
bf35706f | 202 | .section ".proc.info.init", #alloc |
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203 | |
204 | .type __sa110_proc_info,#object | |
205 | __sa110_proc_info: | |
206 | .long 0x4401a100 | |
207 | .long 0xfffffff0 | |
208 | .long PMD_TYPE_SECT | \ | |
209 | PMD_SECT_BUFFERABLE | \ | |
210 | PMD_SECT_CACHEABLE | \ | |
211 | PMD_SECT_AP_WRITE | \ | |
212 | PMD_SECT_AP_READ | |
8799ee9f RK |
213 | .long PMD_TYPE_SECT | \ |
214 | PMD_SECT_AP_WRITE | \ | |
215 | PMD_SECT_AP_READ | |
bf35706f | 216 | initfn __sa110_setup, __sa110_proc_info |
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217 | .long cpu_arch_name |
218 | .long cpu_elf_name | |
219 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT | |
220 | .long cpu_sa110_name | |
221 | .long sa110_processor_functions | |
222 | .long v4wb_tlb_fns | |
223 | .long v4wb_user_fns | |
224 | .long v4wb_cache_fns | |
225 | .size __sa110_proc_info, . - __sa110_proc_info |