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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-v6.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
d090ddda | 5 | * Modified by Catalin Marinas for noMMU support |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This is the "shell" of the ARMv6 processor support. | |
12 | */ | |
991da17e | 13 | #include <linux/init.h> |
1da177e4 LT |
14 | #include <linux/linkage.h> |
15 | #include <asm/assembler.h> | |
e6ae744d | 16 | #include <asm/asm-offsets.h> |
5ec9407d | 17 | #include <asm/hwcap.h> |
74945c86 | 18 | #include <asm/pgtable-hwdef.h> |
1da177e4 LT |
19 | #include <asm/pgtable.h> |
20 | ||
21 | #include "proc-macros.S" | |
22 | ||
23 | #define D_CACHE_LINE_SIZE 32 | |
24 | ||
3747b36e RK |
25 | #define TTB_C (1 << 0) |
26 | #define TTB_S (1 << 1) | |
27 | #define TTB_IMP (1 << 2) | |
28 | #define TTB_RGN_NC (0 << 3) | |
29 | #define TTB_RGN_WBWA (1 << 3) | |
30 | #define TTB_RGN_WT (2 << 3) | |
31 | #define TTB_RGN_WB (3 << 3) | |
32 | ||
f00ec48f RK |
33 | #define TTB_FLAGS_UP TTB_RGN_WBWA |
34 | #define PMD_FLAGS_UP PMD_SECT_WB | |
35 | #define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S | |
36 | #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S | |
f2131d34 | 37 | |
1da177e4 | 38 | ENTRY(cpu_v6_proc_init) |
6ebbf2ce | 39 | ret lr |
1da177e4 LT |
40 | |
41 | ENTRY(cpu_v6_proc_fin) | |
67c5587a TL |
42 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
43 | bic r0, r0, #0x1000 @ ...i............ | |
44 | bic r0, r0, #0x0006 @ .............ca. | |
45 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
6ebbf2ce | 46 | ret lr |
1da177e4 LT |
47 | |
48 | /* | |
49 | * cpu_v6_reset(loc) | |
50 | * | |
51 | * Perform a soft reset of the system. Put the CPU into the | |
52 | * same state as it would be if it had been reset, and branch | |
53 | * to what would be the reset vector. | |
54 | * | |
55 | * - loc - location to jump to for soft reset | |
1da177e4 LT |
56 | */ |
57 | .align 5 | |
1a4baafa | 58 | .pushsection .idmap.text, "ax" |
1da177e4 | 59 | ENTRY(cpu_v6_reset) |
f4daf06f WD |
60 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register |
61 | bic r1, r1, #0x1 @ ...............m | |
62 | mcr p15, 0, r1, c1, c0, 0 @ disable MMU | |
63 | mov r1, #0 | |
64 | mcr p15, 0, r1, c7, c5, 4 @ ISB | |
6ebbf2ce | 65 | ret r0 |
1a4baafa WD |
66 | ENDPROC(cpu_v6_reset) |
67 | .popsection | |
1da177e4 LT |
68 | |
69 | /* | |
70 | * cpu_v6_do_idle() | |
71 | * | |
72 | * Idle the processor (eg, wait for interrupt). | |
73 | * | |
74 | * IRQs are already disabled. | |
75 | */ | |
76 | ENTRY(cpu_v6_do_idle) | |
8553cb67 CM |
77 | mov r1, #0 |
78 | mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode | |
1da177e4 | 79 | mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt |
6ebbf2ce | 80 | ret lr |
1da177e4 LT |
81 | |
82 | ENTRY(cpu_v6_dcache_clean_area) | |
1da177e4 LT |
83 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
84 | add r0, r0, #D_CACHE_LINE_SIZE | |
85 | subs r1, r1, #D_CACHE_LINE_SIZE | |
86 | bhi 1b | |
6ebbf2ce | 87 | ret lr |
1da177e4 LT |
88 | |
89 | /* | |
2b6e204f | 90 | * cpu_v6_switch_mm(pgd_phys, tsk) |
1da177e4 LT |
91 | * |
92 | * Set the translation table base pointer to be pgd_phys | |
93 | * | |
94 | * - pgd_phys - physical address of new TTB | |
95 | * | |
96 | * It is assumed that: | |
97 | * - we are not using split page tables | |
98 | */ | |
99 | ENTRY(cpu_v6_switch_mm) | |
d090ddda | 100 | #ifdef CONFIG_MMU |
1da177e4 | 101 | mov r2, #0 |
251019fb | 102 | mmid r1, r1 @ get mm->context.id |
f00ec48f RK |
103 | ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) |
104 | ALT_UP(orr r0, r0, #TTB_FLAGS_UP) | |
d93742f5 | 105 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
1da177e4 LT |
106 | mcr p15, 0, r2, c7, c10, 4 @ drain write buffer |
107 | mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | |
575320d6 WD |
108 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
109 | mrc p15, 0, r2, c13, c0, 1 @ read current context ID | |
110 | bic r2, r2, #0xff @ extract the PID | |
111 | and r1, r1, #0xff | |
112 | orr r1, r1, r2 @ insert into new context ID | |
113 | #endif | |
1da177e4 | 114 | mcr p15, 0, r1, c13, c0, 1 @ set context ID |
d090ddda | 115 | #endif |
6ebbf2ce | 116 | ret lr |
1da177e4 | 117 | |
1da177e4 | 118 | /* |
ad1ae2fe | 119 | * cpu_v6_set_pte_ext(ptep, pte, ext) |
1da177e4 LT |
120 | * |
121 | * Set a level 2 translation table entry. | |
122 | * | |
123 | * - ptep - pointer to level 2 translation table entry | |
124 | * (hardware version is stored at -1024 bytes) | |
125 | * - pte - PTE value to store | |
ad1ae2fe | 126 | * - ext - value for extended PTE bits |
1da177e4 | 127 | */ |
639b0ae7 RK |
128 | armv6_mt_table cpu_v6 |
129 | ||
ad1ae2fe | 130 | ENTRY(cpu_v6_set_pte_ext) |
d090ddda | 131 | #ifdef CONFIG_MMU |
639b0ae7 | 132 | armv6_set_pte_ext cpu_v6 |
d090ddda | 133 | #endif |
6ebbf2ce | 134 | ret lr |
1da177e4 | 135 | |
f6b0fa02 RK |
136 | /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ |
137 | .globl cpu_v6_suspend_size | |
1aede681 | 138 | .equ cpu_v6_suspend_size, 4 * 6 |
b6c7aabd | 139 | #ifdef CONFIG_ARM_CPU_SUSPEND |
f6b0fa02 | 140 | ENTRY(cpu_v6_do_suspend) |
1aede681 | 141 | stmfd sp!, {r4 - r9, lr} |
f6b0fa02 | 142 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID |
aa1aadc3 | 143 | #ifdef CONFIG_MMU |
1aede681 RK |
144 | mrc p15, 0, r5, c3, c0, 0 @ Domain ID |
145 | mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1 | |
aa1aadc3 | 146 | #endif |
1aede681 RK |
147 | mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register |
148 | mrc p15, 0, r8, c1, c0, 2 @ co-processor access control | |
149 | mrc p15, 0, r9, c1, c0, 0 @ control register | |
150 | stmia r0, {r4 - r9} | |
151 | ldmfd sp!, {r4- r9, pc} | |
f6b0fa02 RK |
152 | ENDPROC(cpu_v6_do_suspend) |
153 | ||
154 | ENTRY(cpu_v6_do_resume) | |
155 | mov ip, #0 | |
156 | mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache | |
157 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
158 | mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache | |
159 | mcr p15, 0, ip, c7, c10, 4 @ drain write buffer | |
1aede681 RK |
160 | mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID |
161 | ldmia r0, {r4 - r9} | |
f6b0fa02 | 162 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID |
aa1aadc3 | 163 | #ifdef CONFIG_MMU |
1aede681 | 164 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID |
de8e71ca RK |
165 | ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) |
166 | ALT_UP(orr r1, r1, #TTB_FLAGS_UP) | |
167 | mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0 | |
1aede681 | 168 | mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1 |
aa1aadc3 WD |
169 | mcr p15, 0, ip, c2, c0, 2 @ TTB control register |
170 | #endif | |
1aede681 RK |
171 | mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register |
172 | mcr p15, 0, r8, c1, c0, 2 @ co-processor access control | |
f6b0fa02 | 173 | mcr p15, 0, ip, c7, c5, 4 @ ISB |
1aede681 | 174 | mov r0, r9 @ control register |
f6b0fa02 RK |
175 | b cpu_resume_mmu |
176 | ENDPROC(cpu_v6_do_resume) | |
f6b0fa02 | 177 | #endif |
1da177e4 | 178 | |
7b7dc6e8 | 179 | string cpu_v6_name, "ARMv6-compatible processor" |
edabd38e | 180 | |
1da177e4 LT |
181 | .align |
182 | ||
1da177e4 LT |
183 | /* |
184 | * __v6_setup | |
185 | * | |
186 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
187 | * on. Return in r0 the new CP15 C1 control register setting. | |
188 | * | |
189 | * We automatically detect if we have a Harvard cache, and use the | |
190 | * Harvard cache control instructions insead of the unified cache | |
191 | * control instructions. | |
192 | * | |
193 | * This should be able to cover all ARMv6 cores. | |
194 | * | |
195 | * It is assumed that: | |
196 | * - cache type register is implemented | |
197 | */ | |
198 | __v6_setup: | |
862184fe | 199 | #ifdef CONFIG_SMP |
f00ec48f RK |
200 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode |
201 | ALT_UP(nop) | |
862184fe | 202 | orr r0, r0, #0x20 |
f00ec48f RK |
203 | ALT_SMP(mcr p15, 0, r0, c1, c0, 1) |
204 | ALT_UP(nop) | |
862184fe RK |
205 | #endif |
206 | ||
1da177e4 LT |
207 | mov r0, #0 |
208 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache | |
209 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
210 | mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache | |
d090ddda | 211 | #ifdef CONFIG_MMU |
1da177e4 LT |
212 | mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs |
213 | mcr p15, 0, r0, c2, c0, 2 @ TTB control register | |
f00ec48f RK |
214 | ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) |
215 | ALT_UP(orr r4, r4, #TTB_FLAGS_UP) | |
d427958a CM |
216 | ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) |
217 | ALT_UP(orr r8, r8, #TTB_FLAGS_UP) | |
218 | mcr p15, 0, r8, c2, c0, 1 @ load TTB1 | |
d090ddda | 219 | #endif /* CONFIG_MMU */ |
bae0ca2b WD |
220 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and |
221 | @ complete invalidations | |
22b19086 RK |
222 | adr r5, v6_crval |
223 | ldmia r5, {r5, r6} | |
457c2403 | 224 | ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables |
1da177e4 | 225 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
1da177e4 | 226 | bic r0, r0, r5 @ clear bits them |
22b19086 | 227 | orr r0, r0, r6 @ set them |
145e10e1 CM |
228 | #ifdef CONFIG_ARM_ERRATA_364296 |
229 | /* | |
230 | * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data | |
231 | * corruption with hit-under-miss enabled). The conditional code below | |
232 | * (setting the undocumented bit 31 in the auxiliary control register | |
233 | * and the FI bit in the control register) disables hit-under-miss | |
234 | * without putting the processor into full low interrupt latency mode. | |
235 | */ | |
236 | ldr r6, =0x4107b362 @ id for ARM1136 r0p2 | |
237 | mrc p15, 0, r5, c0, c0, 0 @ get processor id | |
238 | teq r5, r6 @ check for the faulty core | |
239 | mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg | |
240 | orreq r5, r5, #(1 << 31) @ set the undocumented bit 31 | |
241 | mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg | |
242 | orreq r0, r0, #(1 << 21) @ low interrupt latency configuration | |
243 | #endif | |
6ebbf2ce | 244 | ret lr @ return to head.S:__ret |
1da177e4 LT |
245 | |
246 | /* | |
247 | * V X F I D LR | |
248 | * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM | |
249 | * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced | |
250 | * 0 110 0011 1.00 .111 1101 < we want | |
251 | */ | |
22b19086 RK |
252 | .type v6_crval, #object |
253 | v6_crval: | |
254 | crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c | |
1da177e4 | 255 | |
5085f3ff RK |
256 | __INITDATA |
257 | ||
7b7dc6e8 DM |
258 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
259 | define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1 | |
1da177e4 | 260 | |
5085f3ff RK |
261 | .section ".rodata" |
262 | ||
7b7dc6e8 DM |
263 | string cpu_arch_name, "armv6" |
264 | string cpu_elf_name, "v6" | |
1da177e4 LT |
265 | .align |
266 | ||
bf35706f | 267 | .section ".proc.info.init", #alloc |
1da177e4 LT |
268 | |
269 | /* | |
270 | * Match any ARMv6 processor core. | |
271 | */ | |
272 | .type __v6_proc_info, #object | |
273 | __v6_proc_info: | |
274 | .long 0x0007b000 | |
275 | .long 0x0007f000 | |
f00ec48f RK |
276 | ALT_SMP(.long \ |
277 | PMD_TYPE_SECT | \ | |
278 | PMD_SECT_AP_WRITE | \ | |
279 | PMD_SECT_AP_READ | \ | |
280 | PMD_FLAGS_SMP) | |
281 | ALT_UP(.long \ | |
282 | PMD_TYPE_SECT | \ | |
1da177e4 | 283 | PMD_SECT_AP_WRITE | \ |
4b46d641 | 284 | PMD_SECT_AP_READ | \ |
f00ec48f | 285 | PMD_FLAGS_UP) |
8799ee9f RK |
286 | .long PMD_TYPE_SECT | \ |
287 | PMD_SECT_XN | \ | |
288 | PMD_SECT_AP_WRITE | \ | |
289 | PMD_SECT_AP_READ | |
bf35706f | 290 | initfn __v6_setup, __v6_proc_info |
1da177e4 LT |
291 | .long cpu_arch_name |
292 | .long cpu_elf_name | |
f159f4ed TL |
293 | /* See also feat_v6_fixup() for HWCAP_TLS */ |
294 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS | |
1da177e4 LT |
295 | .long cpu_v6_name |
296 | .long v6_processor_functions | |
297 | .long v6wbi_tlb_fns | |
298 | .long v6_user_fns | |
299 | .long v6_cache_fns | |
300 | .size __v6_proc_info, . - __v6_proc_info |