[deliverable/linux.git] / arch / arm / mm / proc-v7-3level.S

/*
 * arch/arm/mm/proc-v7-3level.S
 *
 * Copyright (C) 2001 Deep Blue Solutions Ltd.
 * Copyright (C) 2011 ARM Ltd.
 * Author: Catalin Marinas <catalin.marinas@arm.com>
 *   based on arch/arm/mm/proc-v7-2level.S
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#define TTB_IRGN_NC	(0 << 8)
#define TTB_IRGN_WBWA	(1 << 8)
#define TTB_IRGN_WT	(2 << 8)
#define TTB_IRGN_WB	(3 << 8)
#define TTB_RGN_NC	(0 << 10)
#define TTB_RGN_OC_WBWA	(1 << 10)
#define TTB_RGN_OC_WT	(2 << 10)
#define TTB_RGN_OC_WB	(3 << 10)
#define TTB_S		(3 << 12)
#define TTB_EAE		(1 << 31)

/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
#define TTB_FLAGS_UP	(TTB_IRGN_WB|TTB_RGN_OC_WB)
#define PMD_FLAGS_UP	(PMD_SECT_WB)

/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
#define TTB_FLAGS_SMP	(TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
#define PMD_FLAGS_SMP	(PMD_SECT_WBWA|PMD_SECT_S)

#ifndef __ARMEB__
#  define rpgdl	r0
#  define rpgdh	r1
#else
#  define rpgdl	r1
#  define rpgdh	r0
#endif

/*
 * cpu_v7_switch_mm(pgd_phys, tsk)
 *
 * Set the translation table base pointer to be pgd_phys (physical address of
 * the new TTB).
 */
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
	mmid	r2, r2
	asid	r2, r2
	orr	rpgdh, rpgdh, r2, lsl #(48 - 32)	@ upper 32-bits of pgd
	mcrr	p15, 0, rpgdl, rpgdh, c2		@ set TTB 0
	isb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_switch_mm)

#ifdef __ARMEB__
#define rl r3
#define rh r2
#else
#define rl r2
#define rh r3
#endif

/*
 * cpu_v7_set_pte_ext(ptep, pte)
 *
 * Set a level 2 translation table entry.
 * - ptep - pointer to level 3 translation table entry
 * - pte - PTE value to store (64-bit in r2 and r3)
 */
ENTRY(cpu_v7_set_pte_ext)
#ifdef CONFIG_MMU
	tst	rl, #L_PTE_VALID
	beq	1f
	tst	rh, #1 << (57 - 32)		@ L_PTE_NONE
	bicne	rl, #L_PTE_VALID
	bne	1f
	tst	rh, #1 << (55 - 32)		@ L_PTE_DIRTY
	orreq	rl, #L_PTE_RDONLY
1:	strd	r2, r3, [r0]
	ALT_SMP(W(nop))
	ALT_UP (mcr	p15, 0, r0, c7, c10, 1)		@ flush_pte
#endif
	mov	pc, lr
ENDPROC(cpu_v7_set_pte_ext)

	/*
	 * Memory region attributes for LPAE (defined in pgtable-3level.h):
	 *
	 *   n = AttrIndx[2:0]
	 *
	 *			n	MAIR
	 *   UNCACHED		000	00000000
	 *   BUFFERABLE		001	01000100
	 *   DEV_WC		001	01000100
	 *   WRITETHROUGH	010	10101010
	 *   WRITEBACK		011	11101110
	 *   DEV_CACHED		011	11101110
	 *   DEV_SHARED		100	00000100
	 *   DEV_NONSHARED	100	00000100
	 *   unused		101
	 *   unused		110
	 *   WRITEALLOC		111	11111111
	 */
.equ	PRRR,	0xeeaa4400			@ MAIR0
.equ	NMRR,	0xff000004			@ MAIR1

	/*
	 * Macro for setting up the TTBRx and TTBCR registers.
	 * - \ttbr1 updated.
	 */
	.macro	v7_ttb_setup, zero, ttbr0, ttbr1, tmp
	ldr	\tmp, =swapper_pg_dir		@ swapper_pg_dir virtual address
	mov	\tmp, \tmp, lsr #ARCH_PGD_SHIFT
	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET?
	mrc	p15, 0, \tmp, c2, c0, 2		@ TTB control register
	orr	\tmp, \tmp, #TTB_EAE
	ALT_SMP(orr	\tmp, \tmp, #TTB_FLAGS_SMP)
	ALT_UP(orr	\tmp, \tmp, #TTB_FLAGS_UP)
	ALT_SMP(orr	\tmp, \tmp, #TTB_FLAGS_SMP << 16)
	ALT_UP(orr	\tmp, \tmp, #TTB_FLAGS_UP << 16)
	/*
	 * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
	 * otherwise booting secondary CPUs would end up using TTBR1 for the
	 * identity mapping set up in TTBR0.
	 */
	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ
	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR
	mov	\tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
	mov	\ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT		@ lower bits
	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
	mov	\tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
	mov	\ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT		@ lower bits
	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0
	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0
	.endm

	/*
	 *   AT
	 *  TFR   EV X F   IHD LR    S
	 * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
	 *   11    0 110    1  0011 1100 .111 1101 < we want
	 */
	.align	2
	.type	v7_crval, #object
v7_crval:
	crval	clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c
Commit	Line	Data
1b6ba46b CM	1	/*
	2	* arch/arm/mm/proc-v7-3level.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	* Copyright (C) 2011 ARM Ltd.
	6	* Author: Catalin Marinas <catalin.marinas@arm.com>
	7	* based on arch/arm/mm/proc-v7-2level.S
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22
	23	#define TTB_IRGN_NC (0 << 8)
	24	#define TTB_IRGN_WBWA (1 << 8)
	25	#define TTB_IRGN_WT (2 << 8)
	26	#define TTB_IRGN_WB (3 << 8)
	27	#define TTB_RGN_NC (0 << 10)
	28	#define TTB_RGN_OC_WBWA (1 << 10)
	29	#define TTB_RGN_OC_WT (2 << 10)
	30	#define TTB_RGN_OC_WB (3 << 10)
	31	#define TTB_S (3 << 12)
	32	#define TTB_EAE (1 << 31)
	33
	34	/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
	35	#define TTB_FLAGS_UP (TTB_IRGN_WB\|TTB_RGN_OC_WB)
	36	#define PMD_FLAGS_UP (PMD_SECT_WB)
	37
	38	/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
	39	#define TTB_FLAGS_SMP (TTB_IRGN_WBWA\|TTB_S\|TTB_RGN_OC_WBWA)
	40	#define PMD_FLAGS_SMP (PMD_SECT_WBWA\|PMD_SECT_S)
	41
13f659b0 CC	42	#ifndef __ARMEB__
	43	# define rpgdl r0
	44	# define rpgdh r1
	45	#else
	46	# define rpgdl r1
	47	# define rpgdh r0
	48	#endif
	49
1b6ba46b CM	50	/*
	51	* cpu_v7_switch_mm(pgd_phys, tsk)
	52	*
	53	* Set the translation table base pointer to be pgd_phys (physical address of
	54	* the new TTB).
	55	*/
	56	ENTRY(cpu_v7_switch_mm)
	57	#ifdef CONFIG_MMU
13f659b0 CC	58	mmid r2, r2
	59	asid r2, r2
	60	orr rpgdh, rpgdh, r2, lsl #(48 - 32) @ upper 32-bits of pgd
	61	mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0
1b6ba46b CM	62	isb
	63	#endif
	64	mov pc, lr
	65	ENDPROC(cpu_v7_switch_mm)
	66
86f40622 JW	67	#ifdef __ARMEB__
	68	#define rl r3
	69	#define rh r2
	70	#else
	71	#define rl r2
	72	#define rh r3
	73	#endif
	74
1b6ba46b CM	75	/*
	76	* cpu_v7_set_pte_ext(ptep, pte)
	77	*
	78	* Set a level 2 translation table entry.
	79	* - ptep - pointer to level 3 translation table entry
	80	* - pte - PTE value to store (64-bit in r2 and r3)
	81	*/
	82	ENTRY(cpu_v7_set_pte_ext)
	83	#ifdef CONFIG_MMU
86f40622	84	tst rl, #L_PTE_VALID
1b6ba46b	85	beq 1f
86f40622 JW	86	tst rh, #1 << (57 - 32) @ L_PTE_NONE
86f40622 JW	87	bicne rl, #L_PTE_VALID
26ffd0d4	88	bne 1f
86f40622 JW	89	tst rh, #1 << (55 - 32) @ L_PTE_DIRTY
86f40622 JW	90	orreq rl, #L_PTE_RDONLY
1b6ba46b	91	1: strd r2, r3, [r0]
bf3f0f33	92	ALT_SMP(W(nop))
ae8a8b95	93	ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
1b6ba46b CM	94	#endif
	95	mov pc, lr
	96	ENDPROC(cpu_v7_set_pte_ext)
	97
	98	/*
	99	* Memory region attributes for LPAE (defined in pgtable-3level.h):
	100	*
	101	* n = AttrIndx[2:0]
	102	*
	103	* n MAIR
	104	* UNCACHED 000 00000000
	105	* BUFFERABLE 001 01000100
	106	* DEV_WC 001 01000100
	107	* WRITETHROUGH 010 10101010
	108	* WRITEBACK 011 11101110
	109	* DEV_CACHED 011 11101110
	110	* DEV_SHARED 100 00000100
	111	* DEV_NONSHARED 100 00000100
	112	* unused 101
	113	* unused 110
	114	* WRITEALLOC 111 11111111
	115	*/
	116	.equ PRRR, 0xeeaa4400 @ MAIR0
	117	.equ NMRR, 0xff000004 @ MAIR1
	118
	119	/*
	120	* Macro for setting up the TTBRx and TTBCR registers.
	121	* - \ttbr1 updated.
	122	*/
	123	.macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp
	124	ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
4756dcbf	125	mov \tmp, \tmp, lsr #ARCH_PGD_SHIFT
a7fbc0d6	126	cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET?
1b6ba46b CM	127	mrc p15, 0, \tmp, c2, c0, 2 @ TTB control register
	128	orr \tmp, \tmp, #TTB_EAE
	129	ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
	130	ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
	131	ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
	132	ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16)
	133	/*
a7fbc0d6 CC	134	* Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
	135	* otherwise booting secondary CPUs would end up using TTBR1 for the
	136	* identity mapping set up in TTBR0.
1b6ba46b	137	*/
a7fbc0d6 CC	138	orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ
a7fbc0d6 CC	139	mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
4756dcbf CC	140	mov \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits
4756dcbf CC	141	mov \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT @ lower bits
a7fbc0d6 CC	142	addls \ttbr1, \ttbr1, #TTBR1_OFFSET
a7fbc0d6 CC	143	mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1
4756dcbf CC	144	mov \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits
	145	mov \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT @ lower bits
	146	mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0
	147	mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1
	148	mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0
1b6ba46b CM	149	.endm
1b6ba46b CM	150
1b6ba46b CM	151	/*
	152	* AT
	153	* TFR EV X F IHD LR S
	154	* .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
	155	* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
	156	* 11 0 110 1 0011 1100 .111 1101 < we want
	157	*/
	158	.align 2
	159	.type v7_crval, #object
	160	v7_crval:
	161	crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c