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bbe88886 CM |
1 | /* |
2 | * linux/arch/arm/mm/proc-v7.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This is the "shell" of the ARMv7 processor support. | |
11 | */ | |
12 | #include <linux/linkage.h> | |
13 | #include <asm/assembler.h> | |
14 | #include <asm/asm-offsets.h> | |
15 | #include <asm/elf.h> | |
16 | #include <asm/pgtable-hwdef.h> | |
17 | #include <asm/pgtable.h> | |
18 | ||
19 | #include "proc-macros.S" | |
20 | ||
21 | #define TTB_C (1 << 0) | |
22 | #define TTB_S (1 << 1) | |
23 | #define TTB_RGN_OC_WT (2 << 3) | |
24 | #define TTB_RGN_OC_WB (3 << 3) | |
25 | ||
26 | ENTRY(cpu_v7_proc_init) | |
27 | mov pc, lr | |
28 | ||
29 | ENTRY(cpu_v7_proc_fin) | |
30 | mov pc, lr | |
31 | ||
32 | /* | |
33 | * cpu_v7_reset(loc) | |
34 | * | |
35 | * Perform a soft reset of the system. Put the CPU into the | |
36 | * same state as it would be if it had been reset, and branch | |
37 | * to what would be the reset vector. | |
38 | * | |
39 | * - loc - location to jump to for soft reset | |
40 | * | |
41 | * It is assumed that: | |
42 | */ | |
43 | .align 5 | |
44 | ENTRY(cpu_v7_reset) | |
45 | mov pc, r0 | |
46 | ||
47 | /* | |
48 | * cpu_v7_do_idle() | |
49 | * | |
50 | * Idle the processor (eg, wait for interrupt). | |
51 | * | |
52 | * IRQs are already disabled. | |
53 | */ | |
54 | ENTRY(cpu_v7_do_idle) | |
55 | .long 0xe320f003 @ ARM V7 WFI instruction | |
56 | mov pc, lr | |
57 | ||
58 | ENTRY(cpu_v7_dcache_clean_area) | |
59 | #ifndef TLB_CAN_READ_FROM_L1_CACHE | |
60 | dcache_line_size r2, r3 | |
61 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
62 | add r0, r0, r2 | |
63 | subs r1, r1, r2 | |
64 | bhi 1b | |
65 | dsb | |
66 | #endif | |
67 | mov pc, lr | |
68 | ||
69 | /* | |
70 | * cpu_v7_switch_mm(pgd_phys, tsk) | |
71 | * | |
72 | * Set the translation table base pointer to be pgd_phys | |
73 | * | |
74 | * - pgd_phys - physical address of new TTB | |
75 | * | |
76 | * It is assumed that: | |
77 | * - we are not using split page tables | |
78 | */ | |
79 | ENTRY(cpu_v7_switch_mm) | |
2eb8c82b | 80 | #ifdef CONFIG_MMU |
bbe88886 CM |
81 | mov r2, #0 |
82 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | |
83 | orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB | |
84 | mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID | |
85 | isb | |
86 | 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | |
87 | isb | |
88 | mcr p15, 0, r1, c13, c0, 1 @ set context ID | |
89 | isb | |
2eb8c82b | 90 | #endif |
bbe88886 CM |
91 | mov pc, lr |
92 | ||
93 | /* | |
94 | * cpu_v7_set_pte_ext(ptep, pte) | |
95 | * | |
96 | * Set a level 2 translation table entry. | |
97 | * | |
98 | * - ptep - pointer to level 2 translation table entry | |
99 | * (hardware version is stored at -1024 bytes) | |
100 | * - pte - PTE value to store | |
101 | * - ext - value for extended PTE bits | |
bbe88886 CM |
102 | */ |
103 | ENTRY(cpu_v7_set_pte_ext) | |
2eb8c82b | 104 | #ifdef CONFIG_MMU |
da091653 | 105 | armv6_set_pte_ext |
2eb8c82b | 106 | #endif |
bbe88886 CM |
107 | mov pc, lr |
108 | ||
109 | cpu_v7_name: | |
110 | .ascii "ARMv7 Processor" | |
111 | .align | |
112 | ||
113 | .section ".text.init", #alloc, #execinstr | |
114 | ||
115 | /* | |
116 | * __v7_setup | |
117 | * | |
118 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
119 | * on. Return in r0 the new CP15 C1 control register setting. | |
120 | * | |
121 | * We automatically detect if we have a Harvard cache, and use the | |
122 | * Harvard cache control instructions insead of the unified cache | |
123 | * control instructions. | |
124 | * | |
125 | * This should be able to cover all ARMv7 cores. | |
126 | * | |
127 | * It is assumed that: | |
128 | * - cache type register is implemented | |
129 | */ | |
130 | __v7_setup: | |
131 | adr r12, __v7_setup_stack @ the local stack | |
132 | stmia r12, {r0-r5, r7, r9, r11, lr} | |
133 | bl v7_flush_dcache_all | |
134 | ldmia r12, {r0-r5, r7, r9, r11, lr} | |
135 | mov r10, #0 | |
136 | #ifdef HARVARD_CACHE | |
137 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate | |
138 | #endif | |
139 | dsb | |
2eb8c82b | 140 | #ifdef CONFIG_MMU |
bbe88886 CM |
141 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
142 | mcr p15, 0, r10, c2, c0, 2 @ TTB control register | |
143 | orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB | |
144 | mcr p15, 0, r4, c2, c0, 0 @ load TTB0 | |
145 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | |
146 | mov r10, #0x1f @ domains 0, 1 = manager | |
147 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register | |
2eb8c82b CM |
148 | #endif |
149 | adr r5, v7_crval | |
150 | ldmia r5, {r5, r6} | |
151 | mrc p15, 0, r0, c1, c0, 0 @ read control register | |
152 | bic r0, r0, r5 @ clear bits them | |
153 | orr r0, r0, r6 @ set them | |
bbe88886 CM |
154 | mov pc, lr @ return to head.S:__ret |
155 | ||
156 | /* | |
157 | * V X F I D LR | |
158 | * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM | |
159 | * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced | |
160 | * 0 110 0011 1.00 .111 1101 < we want | |
161 | */ | |
2eb8c82b CM |
162 | .type v7_crval, #object |
163 | v7_crval: | |
164 | crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c | |
bbe88886 CM |
165 | |
166 | __v7_setup_stack: | |
167 | .space 4 * 11 @ 11 registers | |
168 | ||
169 | .type v7_processor_functions, #object | |
170 | ENTRY(v7_processor_functions) | |
171 | .word v7_early_abort | |
4a1fd556 | 172 | .word pabort_ifar |
bbe88886 CM |
173 | .word cpu_v7_proc_init |
174 | .word cpu_v7_proc_fin | |
175 | .word cpu_v7_reset | |
176 | .word cpu_v7_do_idle | |
177 | .word cpu_v7_dcache_clean_area | |
178 | .word cpu_v7_switch_mm | |
179 | .word cpu_v7_set_pte_ext | |
180 | .size v7_processor_functions, . - v7_processor_functions | |
181 | ||
182 | .type cpu_arch_name, #object | |
183 | cpu_arch_name: | |
184 | .asciz "armv7" | |
185 | .size cpu_arch_name, . - cpu_arch_name | |
186 | ||
187 | .type cpu_elf_name, #object | |
188 | cpu_elf_name: | |
189 | .asciz "v7" | |
190 | .size cpu_elf_name, . - cpu_elf_name | |
191 | .align | |
192 | ||
193 | .section ".proc.info.init", #alloc, #execinstr | |
194 | ||
195 | /* | |
196 | * Match any ARMv7 processor core. | |
197 | */ | |
198 | .type __v7_proc_info, #object | |
199 | __v7_proc_info: | |
200 | .long 0x000f0000 @ Required ID value | |
201 | .long 0x000f0000 @ Mask for ID | |
202 | .long PMD_TYPE_SECT | \ | |
203 | PMD_SECT_BUFFERABLE | \ | |
204 | PMD_SECT_CACHEABLE | \ | |
205 | PMD_SECT_AP_WRITE | \ | |
206 | PMD_SECT_AP_READ | |
207 | .long PMD_TYPE_SECT | \ | |
208 | PMD_SECT_XN | \ | |
209 | PMD_SECT_AP_WRITE | \ | |
210 | PMD_SECT_AP_READ | |
211 | b __v7_setup | |
212 | .long cpu_arch_name | |
213 | .long cpu_elf_name | |
214 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP | |
215 | .long cpu_v7_name | |
216 | .long v7_processor_functions | |
2ccdd1e7 | 217 | .long v7wbi_tlb_fns |
bbe88886 CM |
218 | .long v6_user_fns |
219 | .long v7_cache_fns | |
220 | .size __v7_proc_info, . - __v7_proc_info |