[deliverable/linux.git] / arch / arm / mm / proc-v7.S

/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#ifdef CONFIG_ARM_LPAE
#include "proc-v7-3level.S"
#else
#include "proc-v7-2level.S"
#endif

ENTRY(cpu_v7_proc_init)
	mov	pc, lr
ENDPROC(cpu_v7_proc_init)

ENTRY(cpu_v7_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr
ENDPROC(cpu_v7_proc_fin)

/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 *
 *	This code must be executed using a flat identity mapping with
 *      caches disabled.
 */
	.align	5
	.pushsection	.idmap.text, "ax"
ENTRY(cpu_v7_reset)
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x1			@ ...............m
 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
	isb
	bx	r0
ENDPROC(cpu_v7_reset)
	.popsection

/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	mov	pc, lr
ENDPROC(cpu_v7_do_idle)

ENTRY(cpu_v7_dcache_clean_area)
	ALT_SMP(W(nop))			@ MP extensions imply L1 PTW
	ALT_UP_B(1f)
	mov	pc, lr
1:	dcache_line_size r2, r3
2:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	2b
	dsb	ishst
	mov	pc, lr
ENDPROC(cpu_v7_dcache_clean_area)

	string	cpu_v7_name, "ARMv7 Processor"
	.align

/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl	cpu_v7_suspend_size
.equ	cpu_v7_suspend_size, 4 * 9
#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v7_do_suspend)
	stmfd	sp!, {r4 - r10, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	stmia	r0!, {r4 - r5}
#ifdef CONFIG_MMU
	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
#ifdef CONFIG_ARM_LPAE
	mrrc	p15, 1, r5, r7, c2	@ TTB 1
#else
	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
#endif
	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
#endif
	mrc	p15, 0, r8, c1, c0, 0	@ Control register
	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
	stmia	r0, {r5 - r11}
	ldmfd	sp!, {r4 - r10, pc}
ENDPROC(cpu_v7_do_suspend)

ENTRY(cpu_v7_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
	ldmia	r0!, {r4 - r5}
	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	ldmia	r0, {r5 - r11}
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
#ifdef CONFIG_ARM_LPAE
	mcrr	p15, 0, r1, ip, c2	@ TTB 0
	mcrr	p15, 1, r5, r7, c2	@ TTB 1
#else
	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
#endif
	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
	ldr	r4, =PRRR		@ PRRR
	ldr	r5, =NMRR		@ NMRR
	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
#endif	/* CONFIG_MMU */
	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
	teq	r4, r9			@ Is it already set?
	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
	isb
	dsb
	mov	r0, r8			@ control register
	b	cpu_resume_mmu
ENDPROC(cpu_v7_do_resume)
#endif

#ifdef CONFIG_CPU_PJ4B
	globl_equ	cpu_pj4b_switch_mm,     cpu_v7_switch_mm
	globl_equ	cpu_pj4b_set_pte_ext,	cpu_v7_set_pte_ext
	globl_equ	cpu_pj4b_proc_init,	cpu_v7_proc_init
	globl_equ	cpu_pj4b_proc_fin, 	cpu_v7_proc_fin
	globl_equ	cpu_pj4b_reset,	   	cpu_v7_reset
#ifdef CONFIG_PJ4B_ERRATA_4742
ENTRY(cpu_pj4b_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	dsb					@barrier
	mov	pc, lr
ENDPROC(cpu_pj4b_do_idle)
#else
	globl_equ	cpu_pj4b_do_idle,  	cpu_v7_do_idle
#endif
	globl_equ	cpu_pj4b_dcache_clean_area,	cpu_v7_dcache_clean_area
	globl_equ	cpu_pj4b_do_suspend,	cpu_v7_do_suspend
	globl_equ	cpu_pj4b_do_resume,	cpu_v7_do_resume
	globl_equ	cpu_pj4b_suspend_size,	cpu_v7_suspend_size

#endif

/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v7_ca5mp_setup:
__v7_ca9mp_setup:
__v7_cr7mp_setup:
	mov	r10, #(1 << 0)			@ Cache/TLB ops broadcasting
	b	1f
__v7_ca7mp_setup:
__v7_ca15mp_setup:
	mov	r10, #0
1:
#ifdef CONFIG_SMP
	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
	mcreq	p15, 0, r0, c1, c0, 1
#endif
	b	__v7_setup

__v7_pj4b_setup:
#ifdef CONFIG_CPU_PJ4B

/* Auxiliary Debug Modes Control 1 Register */
#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */

/* Auxiliary Debug Modes Control 2 Register */
#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
			    PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)

/* Auxiliary Functional Modes Control Register 0 */
#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */

/* Auxiliary Debug Modes Control 0 Register */
#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */

	/* Auxiliary Debug Modes Control 1 Register */
	mrc	p15, 1,	r0, c15, c1, 1
	orr     r0, r0, #PJ4B_CLEAN_LINE
	orr     r0, r0, #PJ4B_BCK_OFF_STREX
	orr     r0, r0, #PJ4B_INTER_PARITY
	bic	r0, r0, #PJ4B_STATIC_BP
	mcr	p15, 1,	r0, c15, c1, 1

	/* Auxiliary Debug Modes Control 2 Register */
	mrc	p15, 1,	r0, c15, c1, 2
	bic	r0, r0, #PJ4B_FAST_LDR
	orr	r0, r0, #PJ4B_AUX_DBG_CTRL2
	mcr	p15, 1,	r0, c15, c1, 2

	/* Auxiliary Functional Modes Control Register 0 */
	mrc	p15, 1,	r0, c15, c2, 0
#ifdef CONFIG_SMP
	orr	r0, r0, #PJ4B_SMP_CFB
#endif
	orr	r0, r0, #PJ4B_L1_PAR_CHK
	orr	r0, r0, #PJ4B_BROADCAST_CACHE
	mcr	p15, 1,	r0, c15, c2, 0

	/* Auxiliary Debug Modes Control 0 Register */
	mrc	p15, 1,	r0, c15, c1, 0
	orr	r0, r0, #PJ4B_WFI_WFE
	mcr	p15, 1,	r0, c15, c1, 0

#endif /* CONFIG_CPU_PJ4B */

__v7_setup:
	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
	bl      v7_flush_dcache_louis
	ldmia	r12, {r0-r5, r7, r9, r11, lr}

	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
	and	r10, r0, #0xff000000		@ ARM?
	teq	r10, #0x41000000
	bne	3f
	and	r5, r0, #0x00f00000		@ variant
	and	r6, r0, #0x0000000f		@ revision
	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
	ubfx	r0, r0, #4, #12			@ primary part number

	/* Cortex-A8 Errata */
	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
	teq	r0, r10
	bne	2f
#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)

	teq	r5, #0x00100000			@ only present in r1p*
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_458693
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
	tsteq	r10, #1 << 22
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
#endif
	b	3f

	/* Cortex-A9 Errata */
2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
	teq	r0, r10
	bne	3f
#ifdef CONFIG_ARM_ERRATA_742230
	cmp	r6, #0x22			@ only present up to r2p2
	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrle	r10, r10, #1 << 4		@ set bit #4
	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_742231
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 12		@ set bit #12
	orreq	r10, r10, #1 << 22		@ set bit #22
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
	teq	r5, #0x00200000			@ only present in r2p*
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 6		@ set bit #6
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
	ALT_UP_B(1f)
	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrlt	r10, r10, #1 << 11		@ set bit #11
	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
1:
#endif

	/* Cortex-A15 Errata */
3:	ldr	r10, =0x00000c0f		@ Cortex-A15 primary part number
	teq	r0, r10
	bne	4f

#ifdef CONFIG_ARM_ERRATA_773022
	cmp	r6, #0x4			@ only present up to r0p4
	mrcle	p15, 0, r10, c1, c0, 1		@ read aux control register
	orrle	r10, r10, #1 << 1		@ disable loop buffer
	mcrle	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif

4:	mov	r10, #0
	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
	ldr	r5, =PRRR			@ PRRR
	ldr	r6, =NMRR			@ NMRR
	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
#endif
	dsb					@ Complete invalidations
#ifndef CONFIG_ARM_THUMBEE
	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field
	teq	r0, #(1 << 12)			@ check if ThumbEE is present
	bne	1f
	mov	r5, #0
	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
	orr	r0, r0, #1			@ set the 1st bit in order to
	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
1:
#endif
	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
 ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
#ifdef CONFIG_SWP_EMULATE
	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
#endif
   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
	mov	pc, lr				@ return to head.S:__ret
ENDPROC(__v7_setup)

	.align	2
__v7_setup_stack:
	.space	4 * 11				@ 11 registers

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
#ifdef CONFIG_CPU_PJ4B
	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
#endif

	.section ".rodata"

	string	cpu_arch_name, "armv7"
	string	cpu_elf_name, "v7"
	.align

	.section ".proc.info.init", #alloc, #execinstr

	/*
	 * Standard v7 proc info content
	 */
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
	W(b)	\initfunc
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
		HWCAP_EDSP | HWCAP_TLS | \hwcaps
	.long	cpu_v7_name
	.long	\proc_fns
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
.endm

#ifndef CONFIG_ARM_LPAE
	/*
	 * ARM Ltd. Cortex A5 processor.
	 */
	.type   __v7_ca5mp_proc_info, #object
__v7_ca5mp_proc_info:
	.long	0x410fc050
	.long	0xff0ffff0
	__v7_proc __v7_ca5mp_setup
	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info

	/*
	 * ARM Ltd. Cortex A9 processor.
	 */
	.type   __v7_ca9mp_proc_info, #object
__v7_ca9mp_proc_info:
	.long	0x410fc090
	.long	0xff0ffff0
	__v7_proc __v7_ca9mp_setup
	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info

#endif	/* CONFIG_ARM_LPAE */

	/*
	 * Marvell PJ4B processor.
	 */
#ifdef CONFIG_CPU_PJ4B
	.type   __v7_pj4b_proc_info, #object
__v7_pj4b_proc_info:
	.long	0x560f5800
	.long	0xff0fff00
	__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
#endif

	/*
	 * ARM Ltd. Cortex R7 processor.
	 */
	.type	__v7_cr7mp_proc_info, #object
__v7_cr7mp_proc_info:
	.long	0x410fc170
	.long	0xff0ffff0
	__v7_proc __v7_cr7mp_setup
	.size	__v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info

	/*
	 * ARM Ltd. Cortex A7 processor.
	 */
	.type	__v7_ca7mp_proc_info, #object
__v7_ca7mp_proc_info:
	.long	0x410fc070
	.long	0xff0ffff0
	__v7_proc __v7_ca7mp_setup
	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info

	/*
	 * ARM Ltd. Cortex A15 processor.
	 */
	.type	__v7_ca15mp_proc_info, #object
__v7_ca15mp_proc_info:
	.long	0x410fc0f0
	.long	0xff0ffff0
	__v7_proc __v7_ca15mp_setup
	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info

	/*
	 * Qualcomm Inc. Krait processors.
	 */
	.type	__krait_proc_info, #object
__krait_proc_info:
	.long	0x510f0400		@ Required ID value
	.long	0xff0ffc00		@ Mask for ID
	/*
	 * Some Krait processors don't indicate support for SDIV and UDIV
	 * instructions in the ARM instruction set, even though they actually
	 * do support them.
	 */
	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
	.size	__krait_proc_info, . - __krait_proc_info

	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	__v7_proc __v7_setup
	.size	__v7_proc_info, . - __v7_proc_info
Commit	Line	Data
bbe88886 CM	1	/*
	2	* linux/arch/arm/mm/proc-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This is the "shell" of the ARMv7 processor support.
	11	*/
991da17e	12	#include <linux/init.h>
bbe88886 CM	13	#include <linux/linkage.h>
	14	#include <asm/assembler.h>
	15	#include <asm/asm-offsets.h>
5ec9407d	16	#include <asm/hwcap.h>
bbe88886 CM	17	#include <asm/pgtable-hwdef.h>
	18	#include <asm/pgtable.h>
	19
	20	#include "proc-macros.S"
	21
1b6ba46b CM	22	#ifdef CONFIG_ARM_LPAE
	23	#include "proc-v7-3level.S"
	24	#else
8d2cd3a3	25	#include "proc-v7-2level.S"
1b6ba46b	26	#endif
73b63efa	27
bbe88886 CM	28	ENTRY(cpu_v7_proc_init)
bbe88886 CM	29	mov pc, lr
93ed3970	30	ENDPROC(cpu_v7_proc_init)
bbe88886 CM	31
bbe88886 CM	32	ENTRY(cpu_v7_proc_fin)
1f667c69 TL	33	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	34	bic r0, r0, #0x1000 @ ...i............
	35	bic r0, r0, #0x0006 @ .............ca.
	36	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	37	mov pc, lr
93ed3970	38	ENDPROC(cpu_v7_proc_fin)
bbe88886 CM	39
	40	/*
	41	* cpu_v7_reset(loc)
	42	*
	43	* Perform a soft reset of the system. Put the CPU into the
	44	* same state as it would be if it had been reset, and branch
	45	* to what would be the reset vector.
	46	*
	47	* - loc - location to jump to for soft reset
f4daf06f WD	48	*
	49	* This code must be executed using a flat identity mapping with
	50	* caches disabled.
bbe88886 CM	51	*/
bbe88886 CM	52	.align 5
1a4baafa	53	.pushsection .idmap.text, "ax"
bbe88886	54	ENTRY(cpu_v7_reset)
f4daf06f WD	55	mrc p15, 0, r1, c1, c0, 0 @ ctrl register
f4daf06f WD	56	bic r1, r1, #0x1 @ ...............m
0f81bb6b	57	THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
f4daf06f WD	58	mcr p15, 0, r1, c1, c0, 0 @ disable MMU
f4daf06f WD	59	isb
153cd8e8	60	bx r0
93ed3970	61	ENDPROC(cpu_v7_reset)
1a4baafa	62	.popsection
bbe88886 CM	63
	64	/*
	65	* cpu_v7_do_idle()
	66	*
	67	* Idle the processor (eg, wait for interrupt).
	68	*
	69	* IRQs are already disabled.
	70	*/
	71	ENTRY(cpu_v7_do_idle)
8553cb67	72	dsb @ WFI may enter a low-power mode
000b5025	73	wfi
bbe88886	74	mov pc, lr
93ed3970	75	ENDPROC(cpu_v7_do_idle)
bbe88886 CM	76
bbe88886 CM	77	ENTRY(cpu_v7_dcache_clean_area)
bf3f0f33 WD	78	ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
	79	ALT_UP_B(1f)
	80	mov pc, lr
	81	1: dcache_line_size r2, r3
	82	2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
bbe88886 CM	83	add r0, r0, r2
bbe88886 CM	84	subs r1, r1, r2
bf3f0f33	85	bhi 2b
6abdd491	86	dsb ishst
bbe88886	87	mov pc, lr
93ed3970	88	ENDPROC(cpu_v7_dcache_clean_area)
bbe88886	89
78a8f3c3	90	string cpu_v7_name, "ARMv7 Processor"
bbe88886 CM	91	.align
bbe88886 CM	92
f6b0fa02 RK	93	/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
f6b0fa02 RK	94	.globl cpu_v7_suspend_size
f3db3f43	95	.equ cpu_v7_suspend_size, 4 * 9
15e0d9e3	96	#ifdef CONFIG_ARM_CPU_SUSPEND
f6b0fa02	97	ENTRY(cpu_v7_do_suspend)
de8e71ca	98	stmfd sp!, {r4 - r10, lr}
f6b0fa02	99	mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
1aede681 RK	100	mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
1aede681 RK	101	stmia r0!, {r4 - r5}
aa1aadc3	102	#ifdef CONFIG_MMU
f6b0fa02	103	mrc p15, 0, r6, c3, c0, 0 @ Domain ID
f3db3f43 MS	104	#ifdef CONFIG_ARM_LPAE
	105	mrrc p15, 1, r5, r7, c2 @ TTB 1
	106	#else
de8e71ca	107	mrc p15, 0, r7, c2, c0, 1 @ TTB 1
f3db3f43	108	#endif
1b6ba46b	109	mrc p15, 0, r11, c2, c0, 2 @ TTB control register
aa1aadc3	110	#endif
de8e71ca RK	111	mrc p15, 0, r8, c1, c0, 0 @ Control register
	112	mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
	113	mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
f3db3f43	114	stmia r0, {r5 - r11}
de8e71ca	115	ldmfd sp!, {r4 - r10, pc}
f6b0fa02 RK	116	ENDPROC(cpu_v7_do_suspend)
	117
	118	ENTRY(cpu_v7_do_resume)
	119	mov ip, #0
f6b0fa02	120	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
1aede681 RK	121	mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
1aede681 RK	122	ldmia r0!, {r4 - r5}
f6b0fa02	123	mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
1aede681	124	mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
f3db3f43	125	ldmia r0, {r5 - r11}
aa1aadc3 WD	126	#ifdef CONFIG_MMU
aa1aadc3 WD	127	mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
f6b0fa02	128	mcr p15, 0, r6, c3, c0, 0 @ Domain ID
f3db3f43 MS	129	#ifdef CONFIG_ARM_LPAE
	130	mcrr p15, 0, r1, ip, c2 @ TTB 0
	131	mcrr p15, 1, r5, r7, c2 @ TTB 1
	132	#else
de8e71ca RK	133	ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
	134	ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
	135	mcr p15, 0, r1, c2, c0, 0 @ TTB 0
	136	mcr p15, 0, r7, c2, c0, 1 @ TTB 1
f3db3f43	137	#endif
1b6ba46b	138	mcr p15, 0, r11, c2, c0, 2 @ TTB control register
f6b0fa02 RK	139	ldr r4, =PRRR @ PRRR
	140	ldr r5, =NMRR @ NMRR
	141	mcr p15, 0, r4, c10, c2, 0 @ write PRRR
	142	mcr p15, 0, r5, c10, c2, 1 @ write NMRR
aa1aadc3 WD	143	#endif /* CONFIG_MMU */
	144	mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
	145	teq r4, r9 @ Is it already set?
	146	mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
	147	mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
f6b0fa02	148	isb
f35235a3	149	dsb
de8e71ca	150	mov r0, r8 @ control register
f6b0fa02 RK	151	b cpu_resume_mmu
f6b0fa02 RK	152	ENDPROC(cpu_v7_do_resume)
3e0a07f8 GC	153	#endif
	154
	155	#ifdef CONFIG_CPU_PJ4B
	156	globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
	157	globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
	158	globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
	159	globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
	160	globl_equ cpu_pj4b_reset, cpu_v7_reset
	161	#ifdef CONFIG_PJ4B_ERRATA_4742
	162	ENTRY(cpu_pj4b_do_idle)
	163	dsb @ WFI may enter a low-power mode
	164	wfi
	165	dsb @barrier
	166	mov pc, lr
	167	ENDPROC(cpu_pj4b_do_idle)
	168	#else
	169	globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
	170	#endif
	171	globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
	172	globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend
	173	globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume
	174	globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size
	175
f6b0fa02 RK	176	#endif
f6b0fa02 RK	177
bbe88886 CM	178	/*
	179	* __v7_setup
	180	*
	181	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	182	* on. Return in r0 the new CP15 C1 control register setting.
	183	*
bbe88886 CM	184	* This should be able to cover all ARMv7 cores.
	185	*
	186	* It is assumed that:
	187	* - cache type register is implemented
	188	*/
15eb169b	189	__v7_ca5mp_setup:
14eff181	190	__v7_ca9mp_setup:
c90ad5c9 JA	191	__v7_cr7mp_setup:
c90ad5c9 JA	192	mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
7665d9d2	193	b 1f
b4244738	194	__v7_ca7mp_setup:
7665d9d2 WD	195	__v7_ca15mp_setup:
	196	mov r10, #0
	197	1:
73b63efa	198	#ifdef CONFIG_SMP
f00ec48f RK	199	ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
f00ec48f RK	200	ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
1b3a02eb	201	tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
7665d9d2 WD	202	orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
	203	orreq r0, r0, r10 @ Enable CPU-specific SMP bits
	204	mcreq p15, 0, r0, c1, c0, 1
73b63efa	205	#endif
d106de38	206	b __v7_setup
de490193 GC	207
	208	__v7_pj4b_setup:
	209	#ifdef CONFIG_CPU_PJ4B
	210
	211	/* Auxiliary Debug Modes Control 1 Register */
	212	#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
	213	#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
	214	#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
	215	#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
	216
	217	/* Auxiliary Debug Modes Control 2 Register */
	218	#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
	219	#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
	220	#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
	221	#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
	222	#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
	223	#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA \| PJ4B_CWF \|\
	224	PJ4B_OUTSDNG_NC \| PJ4B_L1_REP_RR)
	225
	226	/* Auxiliary Functional Modes Control Register 0 */
	227	#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
	228	#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
	229	#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
	230
	231	/* Auxiliary Debug Modes Control 0 Register */
	232	#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
	233
	234	/* Auxiliary Debug Modes Control 1 Register */
	235	mrc p15, 1, r0, c15, c1, 1
	236	orr r0, r0, #PJ4B_CLEAN_LINE
	237	orr r0, r0, #PJ4B_BCK_OFF_STREX
	238	orr r0, r0, #PJ4B_INTER_PARITY
	239	bic r0, r0, #PJ4B_STATIC_BP
	240	mcr p15, 1, r0, c15, c1, 1
	241
	242	/* Auxiliary Debug Modes Control 2 Register */
	243	mrc p15, 1, r0, c15, c1, 2
	244	bic r0, r0, #PJ4B_FAST_LDR
	245	orr r0, r0, #PJ4B_AUX_DBG_CTRL2
	246	mcr p15, 1, r0, c15, c1, 2
	247
	248	/* Auxiliary Functional Modes Control Register 0 */
	249	mrc p15, 1, r0, c15, c2, 0
	250	#ifdef CONFIG_SMP
	251	orr r0, r0, #PJ4B_SMP_CFB
	252	#endif
	253	orr r0, r0, #PJ4B_L1_PAR_CHK
	254	orr r0, r0, #PJ4B_BROADCAST_CACHE
	255	mcr p15, 1, r0, c15, c2, 0
	256
	257	/* Auxiliary Debug Modes Control 0 Register */
	258	mrc p15, 1, r0, c15, c1, 0
	259	orr r0, r0, #PJ4B_WFI_WFE
	260	mcr p15, 1, r0, c15, c1, 0
	261
	262	#endif /* CONFIG_CPU_PJ4B */
	263
14eff181	264	__v7_setup:
bbe88886 CM	265	adr r12, __v7_setup_stack @ the local stack
bbe88886 CM	266	stmia r12, {r0-r5, r7, r9, r11, lr}
6323fa22	267	bl v7_flush_dcache_louis
bbe88886	268	ldmia r12, {r0-r5, r7, r9, r11, lr}
1946d6ef RK	269
	270	mrc p15, 0, r0, c0, c0, 0 @ read main ID register
	271	and r10, r0, #0xff000000 @ ARM?
	272	teq r10, #0x41000000
9f05027c	273	bne 3f
1946d6ef RK	274	and r5, r0, #0x00f00000 @ variant
1946d6ef RK	275	and r6, r0, #0x0000000f @ revision
6491848d WD	276	orr r6, r6, r5, lsr #20-4 @ combine variant and revision
6491848d WD	277	ubfx r0, r0, #4, #12 @ primary part number
1946d6ef	278
6491848d WD	279	/* Cortex-A8 Errata */
	280	ldr r10, =0x00000c08 @ Cortex-A8 primary part number
	281	teq r0, r10
	282	bne 2f
62e4d357 RH	283	#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
62e4d357 RH	284
1946d6ef RK	285	teq r5, #0x00100000 @ only present in r1p*
	286	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	287	orreq r10, r10, #(1 << 6) @ set IBE to 1
	288	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
855c551f CM	289	#endif
855c551f CM	290	#ifdef CONFIG_ARM_ERRATA_458693
6491848d	291	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	292	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	293	orreq r10, r10, #(1 << 5) @ set L1NEON to 1
	294	orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
	295	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
0516e464 CM	296	#endif
0516e464 CM	297	#ifdef CONFIG_ARM_ERRATA_460075
6491848d	298	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	299	mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
	300	tsteq r10, #1 << 22
	301	orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
	302	mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
7ce236fc	303	#endif
9f05027c WD	304	b 3f
	305
	306	/* Cortex-A9 Errata */
	307	2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
	308	teq r0, r10
	309	bne 3f
	310	#ifdef CONFIG_ARM_ERRATA_742230
	311	cmp r6, #0x22 @ only present up to r2p2
	312	mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
	313	orrle r10, r10, #1 << 4 @ set bit #4
	314	mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
	315	#endif
a672e99b WD	316	#ifdef CONFIG_ARM_ERRATA_742231
	317	teq r6, #0x20 @ present in r2p0
	318	teqne r6, #0x21 @ present in r2p1
	319	teqne r6, #0x22 @ present in r2p2
	320	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	321	orreq r10, r10, #1 << 12 @ set bit #12
	322	orreq r10, r10, #1 << 22 @ set bit #22
	323	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	324	#endif
475d92fc	325	#ifdef CONFIG_ARM_ERRATA_743622
efbc74ac	326	teq r5, #0x00200000 @ only present in r2p*
475d92fc WD	327	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	328	orreq r10, r10, #1 << 6 @ set bit #6
	329	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	330	#endif
ba90c516 DM	331	#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
	332	ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
	333	ALT_UP_B(1f)
9a27c27c WD	334	mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
	335	orrlt r10, r10, #1 << 11 @ set bit #11
	336	mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
ba90c516	337	1:
9a27c27c	338	#endif
1946d6ef	339
84b6504f WD	340	/* Cortex-A15 Errata */
	341	3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
	342	teq r0, r10
	343	bne 4f
	344
	345	#ifdef CONFIG_ARM_ERRATA_773022
	346	cmp r6, #0x4 @ only present up to r0p4
	347	mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
	348	orrle r10, r10, #1 << 1 @ disable loop buffer
	349	mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
	350	#endif
	351
	352	4: mov r10, #0
bbe88886	353	mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
2eb8c82b	354	#ifdef CONFIG_MMU
bbe88886	355	mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
8d2cd3a3	356	v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
f6b0fa02 RK	357	ldr r5, =PRRR @ PRRR
f6b0fa02 RK	358	ldr r6, =NMRR @ NMRR
3f69c0c1 RK	359	mcr p15, 0, r5, c10, c2, 0 @ write PRRR
3f69c0c1 RK	360	mcr p15, 0, r6, c10, c2, 1 @ write NMRR
078c0454	361	#endif
bae0ca2b	362	dsb @ Complete invalidations
078c0454 JA	363	#ifndef CONFIG_ARM_THUMBEE
	364	mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
	365	and r0, r0, #(0xf << 12) @ ThumbEE enabled field
	366	teq r0, #(1 << 12) @ check if ThumbEE is present
	367	bne 1f
	368	mov r5, #0
	369	mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
	370	mrc p14, 6, r0, c0, c0, 0 @ load TEECR
	371	orr r0, r0, #1 @ set the 1st bit in order to
	372	mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
	373	1:
bdaaaec3	374	#endif
2eb8c82b CM	375	adr r5, v7_crval
2eb8c82b CM	376	ldmia r5, {r5, r6}
457c2403	377	ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
64d2dc38 LL	378	#ifdef CONFIG_SWP_EMULATE
	379	orr r5, r5, #(1 << 10) @ set SW bit in "clear"
	380	bic r6, r6, #(1 << 10) @ clear it in "mmuset"
26584853	381	#endif
2eb8c82b CM	382	mrc p15, 0, r0, c1, c0, 0 @ read control register
	383	bic r0, r0, r5 @ clear bits them
	384	orr r0, r0, r6 @ set them
347c8b70	385	THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
bbe88886	386	mov pc, lr @ return to head.S:__ret
93ed3970	387	ENDPROC(__v7_setup)
bbe88886	388
8d2cd3a3	389	.align 2
bbe88886 CM	390	__v7_setup_stack:
	391	.space 4 * 11 @ 11 registers
	392
5085f3ff RK	393	__INITDATA
5085f3ff RK	394
78a8f3c3 DM	395	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
78a8f3c3 DM	396	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
3e0a07f8 GC	397	#ifdef CONFIG_CPU_PJ4B
	398	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
	399	#endif
bbe88886	400
5085f3ff RK	401	.section ".rodata"
5085f3ff RK	402
78a8f3c3 DM	403	string cpu_arch_name, "armv7"
78a8f3c3 DM	404	string cpu_elf_name, "v7"
bbe88886 CM	405	.align
	406
	407	.section ".proc.info.init", #alloc, #execinstr
	408
dc939cd8 PM	409	/*
	410	* Standard v7 proc info content
	411	*/
3e0a07f8	412	.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
dc939cd8	413	ALT_SMP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_AP_READ \| \
1b6ba46b	414	PMD_SECT_AF \| PMD_FLAGS_SMP \| \mm_mmuflags)
dc939cd8	415	ALT_UP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_AP_READ \| \
1b6ba46b CM	416	PMD_SECT_AF \| PMD_FLAGS_UP \| \mm_mmuflags)
	417	.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| \
	418	PMD_SECT_AP_READ \| PMD_SECT_AF \| \io_mmuflags
dc939cd8	419	W(b) \initfunc
14eff181 DW	420	.long cpu_arch_name
14eff181 DW	421	.long cpu_elf_name
dc939cd8 PM	422	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB \| HWCAP_FAST_MULT \| \
dc939cd8 PM	423	HWCAP_EDSP \| HWCAP_TLS \| \hwcaps
14eff181	424	.long cpu_v7_name
3e0a07f8	425	.long \proc_fns
14eff181 DW	426	.long v7wbi_tlb_fns
	427	.long v6_user_fns
	428	.long v7_cache_fns
dc939cd8 PM	429	.endm
dc939cd8 PM	430
1b6ba46b	431	#ifndef CONFIG_ARM_LPAE
15eb169b PM	432	/*
	433	* ARM Ltd. Cortex A5 processor.
	434	*/
	435	.type __v7_ca5mp_proc_info, #object
	436	__v7_ca5mp_proc_info:
	437	.long 0x410fc050
	438	.long 0xff0ffff0
	439	__v7_proc __v7_ca5mp_setup
	440	.size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
	441
dc939cd8 PM	442	/*
	443	* ARM Ltd. Cortex A9 processor.
	444	*/
	445	.type __v7_ca9mp_proc_info, #object
	446	__v7_ca9mp_proc_info:
	447	.long 0x410fc090
	448	.long 0xff0ffff0
	449	__v7_proc __v7_ca9mp_setup
14eff181	450	.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
de490193	451
b361d61d GC	452	#endif /* CONFIG_ARM_LPAE */
b361d61d GC	453
de490193 GC	454	/*
	455	* Marvell PJ4B processor.
	456	*/
3e0a07f8	457	#ifdef CONFIG_CPU_PJ4B
de490193 GC	458	.type __v7_pj4b_proc_info, #object
de490193 GC	459	__v7_pj4b_proc_info:
049be070 GC	460	.long 0x560f5800
049be070 GC	461	.long 0xff0fff00
3e0a07f8	462	__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
de490193	463	.size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
3e0a07f8	464	#endif
14eff181	465
c90ad5c9 JA	466	/*
	467	* ARM Ltd. Cortex R7 processor.
	468	*/
	469	.type __v7_cr7mp_proc_info, #object
	470	__v7_cr7mp_proc_info:
	471	.long 0x410fc170
	472	.long 0xff0ffff0
	473	__v7_proc __v7_cr7mp_setup
	474	.size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
	475
868dbf90 WD	476	/*
	477	* ARM Ltd. Cortex A7 processor.
	478	*/
	479	.type __v7_ca7mp_proc_info, #object
	480	__v7_ca7mp_proc_info:
	481	.long 0x410fc070
	482	.long 0xff0ffff0
8164f7af	483	__v7_proc __v7_ca7mp_setup
868dbf90 WD	484	.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
868dbf90 WD	485
7665d9d2 WD	486	/*
	487	* ARM Ltd. Cortex A15 processor.
	488	*/
	489	.type __v7_ca15mp_proc_info, #object
	490	__v7_ca15mp_proc_info:
	491	.long 0x410fc0f0
	492	.long 0xff0ffff0
8164f7af	493	__v7_proc __v7_ca15mp_setup
7665d9d2 WD	494	.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
7665d9d2 WD	495
120ecfaf SM	496	/*
	497	* Qualcomm Inc. Krait processors.
	498	*/
	499	.type __krait_proc_info, #object
	500	__krait_proc_info:
	501	.long 0x510f0400 @ Required ID value
	502	.long 0xff0ffc00 @ Mask for ID
	503	/*
	504	* Some Krait processors don't indicate support for SDIV and UDIV
	505	* instructions in the ARM instruction set, even though they actually
	506	* do support them.
	507	*/
	508	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
	509	.size __krait_proc_info, . - __krait_proc_info
	510
bbe88886 CM	511	/*
	512	* Match any ARMv7 processor core.
	513	*/
	514	.type __v7_proc_info, #object
	515	__v7_proc_info:
	516	.long 0x000f0000 @ Required ID value
	517	.long 0x000f0000 @ Mask for ID
dc939cd8	518	__v7_proc __v7_setup
bbe88886	519	.size __v7_proc_info, . - __v7_proc_info