[deliverable/linux.git] / arch / arm / mm / proc-xsc3.S

/*
 * linux/arch/arm/mm/proc-xsc3.S
 *
 * Original Author: Matthew Gilbert
 * Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
 *
 * Copyright 2004 (C) Intel Corp.
 * Copyright 2005 (C) MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * MMU functions for the Intel XScale3 Core (XSC3).  The XSC3 core is
 * an extension to Intel's original XScale core that adds the following
 * features:
 *
 * - ARMv6 Supersections
 * - Low Locality Reference pages (replaces mini-cache)
 * - 36-bit addressing
 * - L2 cache
 * - Cache coherency if chipset supports it
 *
 * Based on original XScale code by Nicolas Pitre.
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <mach/hardware.h>
#include <asm/pgtable.h>
#include <asm/pgtable-hwdef.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be flushed.  If the
 * area is larger than this, then we flush the whole cache.
 */
#define MAX_AREA_SIZE	32768

/*
 * The cache line size of the L1 I, L1 D and unified L2 cache.
 */
#define CACHELINESIZE	32

/*
 * The size of the L1 D cache.
 */
#define CACHESIZE	32768

/*
 * This macro is used to wait for a CP15 write and is needed when we
 * have to ensure that the last operation to the coprocessor was
 * completed before continuing with operation.
 */
	.macro	cpwait_ret, lr, rd
	mrc	p15, 0, \rd, c2, c0, 0		@ arbitrary read of cp15
	sub	pc, \lr, \rd, LSR #32		@ wait for completion and
						@ flush instruction pipeline
	.endm

/*
 * This macro cleans and invalidates the entire L1 D cache.
 */

 	.macro  clean_d_cache rd, rs
	mov	\rd, #0x1f00
	orr	\rd, \rd, #0x00e0
1:	mcr	p15, 0, \rd, c7, c14, 2		@ clean/invalidate L1 D line
	adds	\rd, \rd, #0x40000000
	bcc	1b
	subs	\rd, \rd, #0x20
	bpl	1b
	.endm

	.text

/*
 * cpu_xsc3_proc_init()
 *
 * Nothing too exciting at the moment
 */
ENTRY(cpu_xsc3_proc_init)
	mov	pc, lr

/*
 * cpu_xsc3_proc_fin()
 */
ENTRY(cpu_xsc3_proc_fin)
	str	lr, [sp, #-4]!
	mov	r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
	msr	cpsr_c, r0
	bl	xsc3_flush_kern_cache_all	@ clean caches
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1800			@ ...IZ...........
	bic	r0, r0, #0x0006			@ .............CA.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ldr	pc, [sp], #4

/*
 * cpu_xsc3_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_xsc3_reset)
	mov	r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
	msr	cpsr_c, r1			@ reset CPSR
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x3900			@ ..VIZ..S........
	bic	r1, r1, #0x0086			@ ........B....CA.
	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate L1 caches and BTB
	bic	r1, r1, #0x0001			@ ...............M
	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
	@ CAUTION: MMU turned off from this point.  We count on the pipeline
	@ already containing those two last instructions to survive.
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
	mov	pc, r0

/*
 * cpu_xsc3_do_idle()
 *
 * Cause the processor to idle
 *
 * For now we do nothing but go to idle mode for every case
 *
 * XScale supports clock switching, but using idle mode support
 * allows external hardware to react to system state changes.
 */
	.align	5

ENTRY(cpu_xsc3_do_idle)
	mov	r0, #1
	mcr	p14, 0, r0, c7, c0, 0		@ go to idle
	mov	pc, lr

/* ================================= CACHE ================================ */

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
ENTRY(xsc3_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(xsc3_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
	clean_d_cache r0, r1
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcrne	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcrne	p15, 0, ip, c7, c5, 4		@ prefetch flush
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, vm_flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start - start address (may not be aligned)
 *	- end	- end address (exclusive, may not be aligned)
 *	- vma	- vma_area_struct describing address space
 */
	.align	5
ENTRY(xsc3_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #MAX_AREA_SIZE
	bhs	__flush_whole_cache

1:	tst	r2, #VM_EXEC
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate L1 I line
	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 6		@ invalidate BTB
	mcrne	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcrne	p15, 0, ip, c7, c5, 4		@ prefetch flush
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the I cache and the D cache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 *
 *	Note: single I-cache line invalidation isn't used here since
 *	it also trashes the mini I-cache used by JTAG debuggers.
 */
ENTRY(xsc3_coherent_kern_range)
/* FALLTHROUGH */
ENTRY(xsc3_coherent_user_range)
	bic	r0, r0, #CACHELINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
	mov	pc, lr

/*
 *	flush_kern_dcache_page(void *page)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache.
 *
 *	- addr	- page aligned address
 */
ENTRY(xsc3_flush_kern_dcache_page)
	add	r1, r0, #PAGE_SZ
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(xsc3_dma_inv_range)
	tst	r0, #CACHELINESIZE - 1
	bic	r0, r0, #CACHELINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	tst	r1, #CACHELINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean L1 D line
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(xsc3_dma_clean_range)
	bic	r0, r0, #CACHELINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(xsc3_dma_flush_range)
	bic	r0, r0, #CACHELINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mov	pc, lr

ENTRY(xsc3_cache_fns)
	.long	xsc3_flush_kern_cache_all
	.long	xsc3_flush_user_cache_all
	.long	xsc3_flush_user_cache_range
	.long	xsc3_coherent_kern_range
	.long	xsc3_coherent_user_range
	.long	xsc3_flush_kern_dcache_page
	.long	xsc3_dma_inv_range
	.long	xsc3_dma_clean_range
	.long	xsc3_dma_flush_range

ENTRY(cpu_xsc3_dcache_clean_area)
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	add	r0, r0, #CACHELINESIZE
	subs	r1, r1, #CACHELINESIZE
	bhi	1b
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_xsc3_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_xsc3_switch_mm)
	clean_d_cache r1, r2
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
	orr	r0, r0, #0x18			@ cache the page table in L2
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
	cpwait_ret lr, ip

/*
 * cpu_xsc3_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
cpu_xsc3_mt_table:
	.long	0x00						@ L_PTE_MT_UNCACHED
	.long	PTE_EXT_TEX(1)					@ L_PTE_MT_BUFFERABLE
	.long	PTE_CACHEABLE					@ L_PTE_MT_WRITETHROUGH
	.long	PTE_CACHEABLE | PTE_BUFFERABLE			@ L_PTE_MT_WRITEBACK
	.long	PTE_EXT_TEX(1) | PTE_BUFFERABLE			@ L_PTE_MT_DEV_SHARED
	.long	0x00						@ unused
	.long	0x00						@ L_PTE_MT_MINICACHE (not present)
	.long	PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE	@ L_PTE_MT_WRITEALLOC (not present?)
	.long	0x00						@ unused
	.long	PTE_EXT_TEX(1)					@ L_PTE_MT_DEV_WC
	.long	0x00						@ unused
	.long	PTE_CACHEABLE | PTE_BUFFERABLE			@ L_PTE_MT_DEV_CACHED
	.long	PTE_EXT_TEX(2)					@ L_PTE_MT_DEV_NONSHARED
	.long	0x00						@ unused
	.long	0x00						@ unused
	.long	0x00						@ unused

	.align	5
ENTRY(cpu_xsc3_set_pte_ext)
	xscale_set_pte_ext_prologue

	tst	r1, #L_PTE_SHARED		@ shared?
	and	r1, r1, #L_PTE_MT_MASK
	adr	ip, cpu_xsc3_mt_table
	ldr	ip, [ip, r1]
	orrne	r2, r2, #PTE_EXT_COHERENT	@ interlock: mask in coherent bit
	bic	r2, r2, #0x0c			@ clear old C,B bits
	orr	r2, r2, ip

	xscale_set_pte_ext_epilogue
	mov	pc, lr

	.ltorg

	.align

	__INIT

	.type	__xsc3_setup, #function
__xsc3_setup:
	mov	r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
	msr	cpsr_c, r0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate L1 caches and BTB
	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
	orr	r4, r4, #0x18			@ cache the page table in L2
	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer

	mov	r0, #0				@ don't allow CP access
	mcr	p15, 0, r0, c15, c1, 0		@ write CP access register

	mrc	p15, 0, r0, c1, c0, 1		@ get auxiliary control reg
	and	r0, r0, #2			@ preserve bit P bit setting
	orr	r0, r0, #(1 << 10)		@ enable L2 for LLR cache
	mcr	p15, 0, r0, c1, c0, 1		@ set auxiliary control reg

	adr	r5, xsc3_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0, 0		@ get control register
	bic	r0, r0, r5			@ ..V. ..R. .... ..A.
	orr	r0, r0, r6			@ ..VI Z..S .... .C.M (mmu)
						@ ...I Z..S .... .... (uc)
	mov	pc, lr

	.size	__xsc3_setup, . - __xsc3_setup

	.type	xsc3_crval, #object
xsc3_crval:
	crval	clear=0x04002202, mmuset=0x00003905, ucset=0x00001900

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */

	.type	xsc3_processor_functions, #object
ENTRY(xsc3_processor_functions)
	.word	v5t_early_abort
	.word	pabort_noifar
	.word	cpu_xsc3_proc_init
	.word	cpu_xsc3_proc_fin
	.word	cpu_xsc3_reset
	.word	cpu_xsc3_do_idle
	.word	cpu_xsc3_dcache_clean_area
	.word	cpu_xsc3_switch_mm
	.word	cpu_xsc3_set_pte_ext
	.size	xsc3_processor_functions, . - xsc3_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv5te"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v5"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_xsc3_name, #object
cpu_xsc3_name:
	.asciz	"XScale-V3 based processor"
	.size	cpu_xsc3_name, . - cpu_xsc3_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__xsc3_proc_info,#object
__xsc3_proc_info:
	.long	0x69056000
	.long	0xffffe000
	.long	PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long	PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__xsc3_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
	.long	cpu_xsc3_name
	.long	xsc3_processor_functions
	.long	v4wbi_tlb_fns
	.long	xsc3_mc_user_fns
	.long	xsc3_cache_fns
	.size	__xsc3_proc_info, . - __xsc3_proc_info
Commit	Line	Data
23bdf86a LB	1	/*
	2	* linux/arch/arm/mm/proc-xsc3.S
	3	*
	4	* Original Author: Matthew Gilbert
57fee39f	5	* Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
23bdf86a LB	6	*
23bdf86a LB	7	* Copyright 2004 (C) Intel Corp.
850b4293	8	* Copyright 2005 (C) MontaVista Software, Inc.
23bdf86a LB	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
850b4293 LB	14	* MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is
850b4293 LB	15	* an extension to Intel's original XScale core that adds the following
23bdf86a LB	16	* features:
	17	*
	18	* - ARMv6 Supersections
	19	* - Low Locality Reference pages (replaces mini-cache)
	20	* - 36-bit addressing
	21	* - L2 cache
850b4293	22	* - Cache coherency if chipset supports it
23bdf86a	23	*
850b4293	24	* Based on original XScale code by Nicolas Pitre.
23bdf86a LB	25	*/
	26
	27	#include <linux/linkage.h>
	28	#include <linux/init.h>
	29	#include <asm/assembler.h>
5ec9407d	30	#include <asm/hwcap.h>
a09e64fb	31	#include <mach/hardware.h>
23bdf86a	32	#include <asm/pgtable.h>
b48340af	33	#include <asm/pgtable-hwdef.h>
23bdf86a LB	34	#include <asm/page.h>
	35	#include <asm/ptrace.h>
	36	#include "proc-macros.S"
	37
	38	/*
	39	* This is the maximum size of an area which will be flushed. If the
	40	* area is larger than this, then we flush the whole cache.
	41	*/
	42	#define MAX_AREA_SIZE 32768
	43
	44	/*
850b4293	45	* The cache line size of the L1 I, L1 D and unified L2 cache.
23bdf86a LB	46	*/
	47	#define CACHELINESIZE 32
	48
	49	/*
850b4293	50	* The size of the L1 D cache.
23bdf86a LB	51	*/
	52	#define CACHESIZE 32768
	53
23bdf86a	54	/*
850b4293 LB	55	* This macro is used to wait for a CP15 write and is needed when we
	56	* have to ensure that the last operation to the coprocessor was
	57	* completed before continuing with operation.
23bdf86a LB	58	*/
	59	.macro cpwait_ret, lr, rd
	60	mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
	61	sub pc, \lr, \rd, LSR #32 @ wait for completion and
	62	@ flush instruction pipeline
	63	.endm
	64
	65	/*
850b4293	66	* This macro cleans and invalidates the entire L1 D cache.
23bdf86a LB	67	*/
	68
	69	.macro clean_d_cache rd, rs
	70	mov \rd, #0x1f00
	71	orr \rd, \rd, #0x00e0
850b4293	72	1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
23bdf86a LB	73	adds \rd, \rd, #0x40000000
	74	bcc 1b
	75	subs \rd, \rd, #0x20
	76	bpl 1b
	77	.endm
	78
	79	.text
	80
	81	/*
	82	* cpu_xsc3_proc_init()
	83	*
	84	* Nothing too exciting at the moment
	85	*/
	86	ENTRY(cpu_xsc3_proc_init)
	87	mov pc, lr
	88
	89	/*
	90	* cpu_xsc3_proc_fin()
	91	*/
	92	ENTRY(cpu_xsc3_proc_fin)
	93	str lr, [sp, #-4]!
	94	mov r0, #PSR_F_BIT\|PSR_I_BIT\|SVC_MODE
	95	msr cpsr_c, r0
	96	bl xsc3_flush_kern_cache_all @ clean caches
	97	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	98	bic r0, r0, #0x1800 @ ...IZ...........
	99	bic r0, r0, #0x0006 @ .............CA.
	100	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	101	ldr pc, [sp], #4
	102
	103	/*
	104	* cpu_xsc3_reset(loc)
	105	*
	106	* Perform a soft reset of the system. Put the CPU into the
	107	* same state as it would be if it had been reset, and branch
	108	* to what would be the reset vector.
	109	*
	110	* loc: location to jump to for soft reset
	111	*/
	112	.align 5
	113	ENTRY(cpu_xsc3_reset)
	114	mov r1, #PSR_F_BIT\|PSR_I_BIT\|SVC_MODE
	115	msr cpsr_c, r1 @ reset CPSR
	116	mrc p15, 0, r1, c1, c0, 0 @ ctrl register
23bdf86a	117	bic r1, r1, #0x3900 @ ..VIZ..S........
850b4293	118	bic r1, r1, #0x0086 @ ........B....CA.
23bdf86a	119	mcr p15, 0, r1, c1, c0, 0 @ ctrl register
850b4293	120	mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
23bdf86a LB	121	bic r1, r1, #0x0001 @ ...............M
	122	mcr p15, 0, r1, c1, c0, 0 @ ctrl register
	123	@ CAUTION: MMU turned off from this point. We count on the pipeline
	124	@ already containing those two last instructions to survive.
850b4293	125	mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
23bdf86a LB	126	mov pc, r0
	127
	128	/*
	129	* cpu_xsc3_do_idle()
	130	*
	131	* Cause the processor to idle
	132	*
	133	* For now we do nothing but go to idle mode for every case
	134	*
	135	* XScale supports clock switching, but using idle mode support
	136	* allows external hardware to react to system state changes.
23bdf86a LB	137	*/
	138	.align 5
	139
	140	ENTRY(cpu_xsc3_do_idle)
	141	mov r0, #1
850b4293	142	mcr p14, 0, r0, c7, c0, 0 @ go to idle
23bdf86a LB	143	mov pc, lr
	144
	145	/* ================================= CACHE ================================ */
	146
	147	/*
	148	* flush_user_cache_all()
	149	*
	150	* Invalidate all cache entries in a particular address
	151	* space.
	152	*/
	153	ENTRY(xsc3_flush_user_cache_all)
	154	/* FALLTHROUGH */
	155
	156	/*
	157	* flush_kern_cache_all()
	158	*
	159	* Clean and invalidate the entire cache.
	160	*/
	161	ENTRY(xsc3_flush_kern_cache_all)
	162	mov r2, #VM_EXEC
	163	mov ip, #0
	164	__flush_whole_cache:
	165	clean_d_cache r0, r1
	166	tst r2, #VM_EXEC
850b4293 LB	167	mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
	168	mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
	169	mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
23bdf86a LB	170	mov pc, lr
	171
	172	/*
	173	* flush_user_cache_range(start, end, vm_flags)
	174	*
	175	* Invalidate a range of cache entries in the specified
	176	* address space.
	177	*
	178	* - start - start address (may not be aligned)
	179	* - end - end address (exclusive, may not be aligned)
	180	* - vma - vma_area_struct describing address space
	181	*/
	182	.align 5
	183	ENTRY(xsc3_flush_user_cache_range)
	184	mov ip, #0
	185	sub r3, r1, r0 @ calculate total size
	186	cmp r3, #MAX_AREA_SIZE
	187	bhs __flush_whole_cache
	188
	189	1: tst r2, #VM_EXEC
850b4293 LB	190	mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
850b4293 LB	191	mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
23bdf86a LB	192	add r0, r0, #CACHELINESIZE
	193	cmp r0, r1
	194	blo 1b
	195	tst r2, #VM_EXEC
850b4293 LB	196	mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
	197	mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
	198	mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
23bdf86a LB	199	mov pc, lr
	200
	201	/*
	202	* coherent_kern_range(start, end)
	203	*
850b4293	204	* Ensure coherency between the I cache and the D cache in the
23bdf86a LB	205	* region described by start. If you have non-snooping
	206	* Harvard caches, you need to implement this function.
	207	*
	208	* - start - virtual start address
	209	* - end - virtual end address
	210	*
	211	* Note: single I-cache line invalidation isn't used here since
	212	* it also trashes the mini I-cache used by JTAG debuggers.
	213	*/
	214	ENTRY(xsc3_coherent_kern_range)
	215	/* FALLTHROUGH */
	216	ENTRY(xsc3_coherent_user_range)
	217	bic r0, r0, #CACHELINESIZE - 1
850b4293	218	1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
23bdf86a LB	219	add r0, r0, #CACHELINESIZE
	220	cmp r0, r1
	221	blo 1b
	222	mov r0, #0
850b4293 LB	223	mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
	224	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
	225	mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
23bdf86a LB	226	mov pc, lr
	227
	228	/*
	229	* flush_kern_dcache_page(void *page)
	230	*
	231	* Ensure no D cache aliasing occurs, either with itself or
850b4293	232	* the I cache.
23bdf86a LB	233	*
	234	* - addr - page aligned address
	235	*/
	236	ENTRY(xsc3_flush_kern_dcache_page)
	237	add r1, r0, #PAGE_SZ
850b4293	238	1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
23bdf86a LB	239	add r0, r0, #CACHELINESIZE
	240	cmp r0, r1
	241	blo 1b
	242	mov r0, #0
850b4293 LB	243	mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
	244	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
	245	mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
23bdf86a LB	246	mov pc, lr
	247
	248	/*
	249	* dma_inv_range(start, end)
	250	*
	251	* Invalidate (discard) the specified virtual address range.
	252	* May not write back any entries. If 'start' or 'end'
	253	* are not cache line aligned, those lines must be written
	254	* back.
	255	*
	256	* - start - virtual start address
	257	* - end - virtual end address
	258	*/
	259	ENTRY(xsc3_dma_inv_range)
	260	tst r0, #CACHELINESIZE - 1
	261	bic r0, r0, #CACHELINESIZE - 1
850b4293	262	mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
23bdf86a	263	tst r1, #CACHELINESIZE - 1
850b4293	264	mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
850b4293	265	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
23bdf86a LB	266	add r0, r0, #CACHELINESIZE
	267	cmp r0, r1
	268	blo 1b
850b4293	269	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
23bdf86a LB	270	mov pc, lr
	271
	272	/*
	273	* dma_clean_range(start, end)
	274	*
	275	* Clean the specified virtual address range.
	276	*
	277	* - start - virtual start address
	278	* - end - virtual end address
	279	*/
	280	ENTRY(xsc3_dma_clean_range)
	281	bic r0, r0, #CACHELINESIZE - 1
850b4293	282	1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
23bdf86a LB	283	add r0, r0, #CACHELINESIZE
	284	cmp r0, r1
	285	blo 1b
850b4293	286	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
23bdf86a LB	287	mov pc, lr
	288
	289	/*
	290	* dma_flush_range(start, end)
	291	*
	292	* Clean and invalidate the specified virtual address range.
	293	*
	294	* - start - virtual start address
	295	* - end - virtual end address
	296	*/
	297	ENTRY(xsc3_dma_flush_range)
	298	bic r0, r0, #CACHELINESIZE - 1
850b4293	299	1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
23bdf86a LB	300	add r0, r0, #CACHELINESIZE
	301	cmp r0, r1
	302	blo 1b
850b4293	303	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
23bdf86a LB	304	mov pc, lr
	305
	306	ENTRY(xsc3_cache_fns)
	307	.long xsc3_flush_kern_cache_all
	308	.long xsc3_flush_user_cache_all
	309	.long xsc3_flush_user_cache_range
	310	.long xsc3_coherent_kern_range
	311	.long xsc3_coherent_user_range
	312	.long xsc3_flush_kern_dcache_page
	313	.long xsc3_dma_inv_range
	314	.long xsc3_dma_clean_range
	315	.long xsc3_dma_flush_range
	316
	317	ENTRY(cpu_xsc3_dcache_clean_area)
850b4293	318	1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
23bdf86a LB	319	add r0, r0, #CACHELINESIZE
	320	subs r1, r1, #CACHELINESIZE
	321	bhi 1b
	322	mov pc, lr
	323
	324	/* =============================== PageTable ============================== */
	325
	326	/*
	327	* cpu_xsc3_switch_mm(pgd)
	328	*
	329	* Set the translation base pointer to be as described by pgd.
	330	*
	331	* pgd: new page tables
	332	*/
	333	.align 5
	334	ENTRY(cpu_xsc3_switch_mm)
	335	clean_d_cache r1, r2
850b4293 LB	336	mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
	337	mcr p15, 0, ip, c7, c10, 4 @ data write barrier
	338	mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
23bdf86a	339	orr r0, r0, #0x18 @ cache the page table in L2
23bdf86a	340	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
850b4293	341	mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
23bdf86a LB	342	cpwait_ret lr, ip
	343
	344	/*
ad1ae2fe	345	* cpu_xsc3_set_pte_ext(ptep, pte, ext)
23bdf86a LB	346	*
23bdf86a LB	347	* Set a PTE and flush it out
23bdf86a	348	*/
9e8b5199 RK	349	cpu_xsc3_mt_table:
9e8b5199 RK	350	.long 0x00 @ L_PTE_MT_UNCACHED
40df2d1d RK	351	.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
	352	.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
	353	.long PTE_CACHEABLE \| PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
	354	.long PTE_EXT_TEX(1) \| PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
639b0ae7	355	.long 0x00 @ unused
9e8b5199 RK	356	.long 0x00 @ L_PTE_MT_MINICACHE (not present)
9e8b5199 RK	357	.long PTE_EXT_TEX(5) \| PTE_CACHEABLE \| PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
639b0ae7	358	.long 0x00 @ unused
9e8b5199 RK	359	.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
9e8b5199 RK	360	.long 0x00 @ unused
40df2d1d RK	361	.long PTE_CACHEABLE \| PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
40df2d1d RK	362	.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
db5b7169	363	.long 0x00 @ unused
9e8b5199 RK	364	.long 0x00 @ unused
	365	.long 0x00 @ unused
	366
23bdf86a	367	.align 5
ad1ae2fe	368	ENTRY(cpu_xsc3_set_pte_ext)
da091653	369	xscale_set_pte_ext_prologue
23bdf86a	370
da091653	371	tst r1, #L_PTE_SHARED @ shared?
9e8b5199 RK	372	and r1, r1, #L_PTE_MT_MASK
	373	adr ip, cpu_xsc3_mt_table
	374	ldr ip, [ip, r1]
	375	orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit
	376	bic r2, r2, #0x0c @ clear old C,B bits
	377	orr r2, r2, ip
23bdf86a	378
da091653	379	xscale_set_pte_ext_epilogue
23bdf86a LB	380	mov pc, lr
	381
	382	.ltorg
	383
	384	.align
	385
	386	__INIT
	387
	388	.type __xsc3_setup, #function
	389	__xsc3_setup:
	390	mov r0, #PSR_F_BIT\|PSR_I_BIT\|SVC_MODE
	391	msr cpsr_c, r0
850b4293 LB	392	mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
	393	mcr p15, 0, ip, c7, c10, 4 @ data write barrier
	394	mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
	395	mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
23bdf86a	396	orr r4, r4, #0x18 @ cache the page table in L2
23bdf86a	397	mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
850b4293 LB	398
	399	mov r0, #0 @ don't allow CP access
	400	mcr p15, 0, r0, c15, c1, 0 @ write CP access register
	401
23bdf86a LB	402	mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
23bdf86a LB	403	and r0, r0, #2 @ preserve bit P bit setting
23bdf86a	404	orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
23bdf86a	405	mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
22b19086 RK	406
	407	adr r5, xsc3_crval
	408	ldmia r5, {r5, r6}
23bdf86a	409	mrc p15, 0, r0, c1, c0, 0 @ get control register
850b4293 LB	410	bic r0, r0, r5 @ ..V. ..R. .... ..A.
	411	orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
	412	@ ...I Z..S .... .... (uc)
23bdf86a LB	413	mov pc, lr
	414
	415	.size __xsc3_setup, . - __xsc3_setup
	416
22b19086 RK	417	.type xsc3_crval, #object
22b19086 RK	418	xsc3_crval:
850b4293	419	crval clear=0x04002202, mmuset=0x00003905, ucset=0x00001900
22b19086	420
23bdf86a LB	421	__INITDATA
	422
	423	/*
	424	* Purpose : Function pointers used to access above functions - all calls
	425	* come through these
	426	*/
	427
	428	.type xsc3_processor_functions, #object
	429	ENTRY(xsc3_processor_functions)
	430	.word v5t_early_abort
4a1fd556	431	.word pabort_noifar
23bdf86a LB	432	.word cpu_xsc3_proc_init
	433	.word cpu_xsc3_proc_fin
	434	.word cpu_xsc3_reset
	435	.word cpu_xsc3_do_idle
	436	.word cpu_xsc3_dcache_clean_area
	437	.word cpu_xsc3_switch_mm
ad1ae2fe	438	.word cpu_xsc3_set_pte_ext
23bdf86a LB	439	.size xsc3_processor_functions, . - xsc3_processor_functions
	440
	441	.section ".rodata"
	442
	443	.type cpu_arch_name, #object
	444	cpu_arch_name:
	445	.asciz "armv5te"
	446	.size cpu_arch_name, . - cpu_arch_name
	447
	448	.type cpu_elf_name, #object
	449	cpu_elf_name:
	450	.asciz "v5"
	451	.size cpu_elf_name, . - cpu_elf_name
	452
	453	.type cpu_xsc3_name, #object
	454	cpu_xsc3_name:
850b4293	455	.asciz "XScale-V3 based processor"
23bdf86a LB	456	.size cpu_xsc3_name, . - cpu_xsc3_name
	457
	458	.align
	459
	460	.section ".proc.info.init", #alloc, #execinstr
	461
	462	.type __xsc3_proc_info,#object
	463	__xsc3_proc_info:
	464	.long 0x69056000
	465	.long 0xffffe000
8799ee9f RK	466	.long PMD_TYPE_SECT \| \
	467	PMD_SECT_BUFFERABLE \| \
	468	PMD_SECT_CACHEABLE \| \
	469	PMD_SECT_AP_WRITE \| \
	470	PMD_SECT_AP_READ
850b4293	471	.long PMD_TYPE_SECT \| \
8799ee9f RK	472	PMD_SECT_AP_WRITE \| \
8799ee9f RK	473	PMD_SECT_AP_READ
23bdf86a LB	474	b __xsc3_setup
	475	.long cpu_arch_name
	476	.long cpu_elf_name
	477	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP
	478	.long cpu_xsc3_name
	479	.long xsc3_processor_functions
	480	.long v4wbi_tlb_fns
	481	.long xsc3_mc_user_fns
	482	.long xsc3_cache_fns
	483	.size __xsc3_proc_info, . - __xsc3_proc_info