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[ARM] 3786/1: pnx4008: update defconfig
[deliverable/linux.git] / arch / arm / mm / proc-xscale.S
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/mm/proc-xscale.S
3 *
4 * Author: Nicolas Pitre
5 * Created: November 2000
6 * Copyright: (C) 2000, 2001 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * MMU functions for the Intel XScale CPUs
13 *
14 * 2001 Aug 21:
15 * some contributions by Brett Gaines <brett.w.gaines@intel.com>
16 * Copyright 2001 by Intel Corp.
17 *
18 * 2001 Sep 08:
19 * Completely revisited, many important fixes
20 * Nicolas Pitre <nico@cam.org>
21 */
22
23#include <linux/linkage.h>
24#include <linux/init.h>
25#include <asm/assembler.h>
26#include <asm/procinfo.h>
1da177e4 27#include <asm/pgtable.h>
0003cedf 28#include <asm/pgtable-hwdef.h>
1da177e4
LT		 29#include <asm/page.h>
30#include <asm/ptrace.h>
31#include "proc-macros.S"
32
33/*
34 * This is the maximum size of an area which will be flushed. If the area
35 * is larger than this, then we flush the whole cache
36 */
37#define MAX_AREA_SIZE 32768
38
39/*
40 * the cache line size of the I and D cache
41 */
42#define CACHELINESIZE 32
43
44/*
45 * the size of the data cache
46 */
47#define CACHESIZE 32768
48
49/*
50 * Virtual address used to allocate the cache when flushed
51 *
52 * This must be an address range which is _never_ used. It should
53 * apparently have a mapping in the corresponding page table for
54 * compatibility with future CPUs that _could_ require it. For instance we
55 * don't care.
56 *
57 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
58 * the 2 areas in alternance each time the clean_d_cache macro is used.
59 * Without this the XScale core exhibits cache eviction problems and no one
60 * knows why.
61 *
62 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
63 */
64#define CLEAN_ADDR 0xfffe0000
65
66/*
67 * This macro is used to wait for a CP15 write and is needed
68 * when we have to ensure that the last operation to the co-pro
69 * was completed before continuing with operation.
70 */
71 .macro cpwait, rd
72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
73 mov \rd, \rd @ wait for completion
74 sub pc, pc, #4 @ flush instruction pipeline
75 .endm
76
77 .macro cpwait_ret, lr, rd
78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
79 sub pc, \lr, \rd, LSR #32 @ wait for completion and
80 @ flush instruction pipeline
81 .endm
82
83/*
84 * This macro cleans the entire dcache using line allocate.
85 * The main loop has been unrolled to reduce loop overhead.
86 * rd and rs are two scratch registers.
87 */
88 .macro clean_d_cache, rd, rs
89 ldr \rs, =clean_addr
90 ldr \rd, [\rs]
91 eor \rd, \rd, #CACHESIZE
92 str \rd, [\rs]
93 add \rs, \rd, #CACHESIZE
941: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 add \rd, \rd, #CACHELINESIZE
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 add \rd, \rd, #CACHELINESIZE
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
99 add \rd, \rd, #CACHELINESIZE
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
101 add \rd, \rd, #CACHELINESIZE
102 teq \rd, \rs
103 bne 1b
104 .endm
105
106 .data
107clean_addr: .word CLEAN_ADDR
108
109 .text
110
111/*
112 * cpu_xscale_proc_init()
113 *
114 * Nothing too exciting at the moment
115 */
116ENTRY(cpu_xscale_proc_init)
117 mov pc, lr
118
119/*
120 * cpu_xscale_proc_fin()
121 */
122ENTRY(cpu_xscale_proc_fin)
123 str lr, [sp, #-4]!
124 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
125 msr cpsr_c, r0
126 bl xscale_flush_kern_cache_all @ clean caches
127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
128 bic r0, r0, #0x1800 @ ...IZ...........
129 bic r0, r0, #0x0006 @ .............CA.
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
131 ldr pc, [sp], #4
132
133/*
134 * cpu_xscale_reset(loc)
135 *
136 * Perform a soft reset of the system. Put the CPU into the
137 * same state as it would be if it had been reset, and branch
138 * to what would be the reset vector.
139 *
140 * loc: location to jump to for soft reset
2dc7667b
NP		 141 *
142 * Beware PXA270 erratum E7.
1da177e4
LT		 143 */
144 .align 5
145ENTRY(cpu_xscale_reset)
146 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
147 msr cpsr_c, r1 @ reset CPSR
2dc7667b
NP		 148 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
149 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
1da177e4
LT		 150 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
151 bic r1, r1, #0x0086 @ ........B....CA.
152 bic r1, r1, #0x3900 @ ..VIZ..S........
2dc7667b
NP		 153 sub pc, pc, #4 @ flush pipeline
154 @ *** cache line aligned ***
1da177e4 155 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
1da177e4 156 bic r1, r1, #0x0001 @ ...............M
2dc7667b 157 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
1da177e4
LT		 158 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
159 @ CAUTION: MMU turned off from this point. We count on the pipeline
160 @ already containing those two last instructions to survive.
161 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
162 mov pc, r0
163
164/*
165 * cpu_xscale_do_idle()
166 *
167 * Cause the processor to idle
168 *
169 * For now we do nothing but go to idle mode for every case
170 *
171 * XScale supports clock switching, but using idle mode support
172 * allows external hardware to react to system state changes.
173 */
174 .align 5
175
176ENTRY(cpu_xscale_do_idle)
177 mov r0, #1
178 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
179 mov pc, lr
180
181/* ================================= CACHE ================================ */
182
183/*
184 * flush_user_cache_all()
185 *
186 * Invalidate all cache entries in a particular address
187 * space.
188 */
189ENTRY(xscale_flush_user_cache_all)
190 /* FALLTHROUGH */
191
192/*
193 * flush_kern_cache_all()
194 *
195 * Clean and invalidate the entire cache.
196 */
197ENTRY(xscale_flush_kern_cache_all)
198 mov r2, #VM_EXEC
199 mov ip, #0
200__flush_whole_cache:
201 clean_d_cache r0, r1
202 tst r2, #VM_EXEC
203 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
204 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
205 mov pc, lr
206
207/*
208 * flush_user_cache_range(start, end, vm_flags)
209 *
210 * Invalidate a range of cache entries in the specified
211 * address space.
212 *
213 * - start - start address (may not be aligned)
214 * - end - end address (exclusive, may not be aligned)
215 * - vma - vma_area_struct describing address space
216 */
217 .align 5
218ENTRY(xscale_flush_user_cache_range)
219 mov ip, #0
220 sub r3, r1, r0 @ calculate total size
221 cmp r3, #MAX_AREA_SIZE
222 bhs __flush_whole_cache
223
2241: tst r2, #VM_EXEC
225 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
226 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
227 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
228 add r0, r0, #CACHELINESIZE
229 cmp r0, r1
230 blo 1b
231 tst r2, #VM_EXEC
232 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
233 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
234 mov pc, lr
235
236/*
237 * coherent_kern_range(start, end)
238 *
239 * Ensure coherency between the Icache and the Dcache in the
240 * region described by start. If you have non-snooping
241 * Harvard caches, you need to implement this function.
242 *
243 * - start - virtual start address
244 * - end - virtual end address
245 *
246 * Note: single I-cache line invalidation isn't used here since
247 * it also trashes the mini I-cache used by JTAG debuggers.
248 */
249ENTRY(xscale_coherent_kern_range)
8a052e0b
NP		 250 bic r0, r0, #CACHELINESIZE - 1
2511: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
252 add r0, r0, #CACHELINESIZE
253 cmp r0, r1
254 blo 1b
255 mov r0, #0
256 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
257 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
258 mov pc, lr
1da177e4
LT		 259
260/*
261 * coherent_user_range(start, end)
262 *
263 * Ensure coherency between the Icache and the Dcache in the
264 * region described by start. If you have non-snooping
265 * Harvard caches, you need to implement this function.
266 *
267 * - start - virtual start address
268 * - end - virtual end address
1da177e4
LT		 269 */
270ENTRY(xscale_coherent_user_range)
271 bic r0, r0, #CACHELINESIZE - 1
2721: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
8a052e0b 273 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
1da177e4
LT		 274 add r0, r0, #CACHELINESIZE
275 cmp r0, r1
276 blo 1b
277 mov r0, #0
8a052e0b 278 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
1da177e4
LT		 279 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
280 mov pc, lr
281
282/*
283 * flush_kern_dcache_page(void *page)
284 *
285 * Ensure no D cache aliasing occurs, either with itself or
286 * the I cache
287 *
288 * - addr - page aligned address
289 */
290ENTRY(xscale_flush_kern_dcache_page)
291 add r1, r0, #PAGE_SZ
2921: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
293 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
294 add r0, r0, #CACHELINESIZE
295 cmp r0, r1
296 blo 1b
297 mov r0, #0
298 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
299 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
300 mov pc, lr
301
302/*
303 * dma_inv_range(start, end)
304 *
305 * Invalidate (discard) the specified virtual address range.
306 * May not write back any entries. If 'start' or 'end'
307 * are not cache line aligned, those lines must be written
308 * back.
309 *
310 * - start - virtual start address
311 * - end - virtual end address
312 */
313ENTRY(xscale_dma_inv_range)
314 mrc p15, 0, r2, c0, c0, 0 @ read ID
315 eor r2, r2, #0x69000000
316 eor r2, r2, #0x00052000
317 bics r2, r2, #1
318 beq xscale_dma_flush_range
319
320 tst r0, #CACHELINESIZE - 1
321 bic r0, r0, #CACHELINESIZE - 1
322 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
323 tst r1, #CACHELINESIZE - 1
324 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
3251: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
326 add r0, r0, #CACHELINESIZE
327 cmp r0, r1
328 blo 1b
329 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
330 mov pc, lr
331
332/*
333 * dma_clean_range(start, end)
334 *
335 * Clean the specified virtual address range.
336 *
337 * - start - virtual start address
338 * - end - virtual end address
339 */
340ENTRY(xscale_dma_clean_range)
341 bic r0, r0, #CACHELINESIZE - 1
3421: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
343 add r0, r0, #CACHELINESIZE
344 cmp r0, r1
345 blo 1b
346 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
347 mov pc, lr
348
349/*
350 * dma_flush_range(start, end)
351 *
352 * Clean and invalidate the specified virtual address range.
353 *
354 * - start - virtual start address
355 * - end - virtual end address
356 */
357ENTRY(xscale_dma_flush_range)
358 bic r0, r0, #CACHELINESIZE - 1
3591: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
360 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
361 add r0, r0, #CACHELINESIZE
362 cmp r0, r1
363 blo 1b
364 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
365 mov pc, lr
366
367ENTRY(xscale_cache_fns)
368 .long xscale_flush_kern_cache_all
369 .long xscale_flush_user_cache_all
370 .long xscale_flush_user_cache_range
371 .long xscale_coherent_kern_range
372 .long xscale_coherent_user_range
373 .long xscale_flush_kern_dcache_page
374 .long xscale_dma_inv_range
375 .long xscale_dma_clean_range
376 .long xscale_dma_flush_range
377
378ENTRY(cpu_xscale_dcache_clean_area)
3791: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
380 add r0, r0, #CACHELINESIZE
381 subs r1, r1, #CACHELINESIZE
382 bhi 1b
383 mov pc, lr
384
1da177e4
LT		 385/* =============================== PageTable ============================== */
386
387#define PTE_CACHE_WRITE_ALLOCATE 0
388
389/*
390 * cpu_xscale_switch_mm(pgd)
391 *
392 * Set the translation base pointer to be as described by pgd.
393 *
394 * pgd: new page tables
395 */
396 .align 5
397ENTRY(cpu_xscale_switch_mm)
398 clean_d_cache r1, r2
399 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
400 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
401 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
402 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
403 cpwait_ret lr, ip
404
405/*
406 * cpu_xscale_set_pte(ptep, pte)
407 *
408 * Set a PTE and flush it out
409 *
410 * Errata 40: must set memory to write-through for user read-only pages.
411 */
412 .align 5
413ENTRY(cpu_xscale_set_pte)
414 str r1, [r0], #-2048 @ linux version
415
416 bic r2, r1, #0xff0
417 orr r2, r2, #PTE_TYPE_EXT @ extended page
418
419 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
420
421 tst r3, #L_PTE_USER @ User?
422 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
423
424 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
425 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
426 @ combined with user -> user r/w
427
428 @
429 @ Handle the X bit. We want to set this bit for the minicache
430 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
431 @ and we have a writeable, cacheable region. If we ignore the
432 @ U and E bits, we can allow user space to use the minicache as
433 @ well.
434 @
435 @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
436 @
437 eor ip, r1, #L_PTE_CACHEABLE
438 tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
439#if PTE_CACHE_WRITE_ALLOCATE
440 eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
441 tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
442#endif
443 orreq r2, r2, #PTE_EXT_TEX(1)
444
445 @
446 @ Erratum 40: The B bit must be cleared for a user read-only
447 @ cacheable page.
448 @
449 @ B = B & ~(U & C & ~W)
450 @
451 and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
452 teq ip, #L_PTE_USER | L_PTE_CACHEABLE
453 biceq r2, r2, #PTE_BUFFERABLE
454
455 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
456 movne r2, #0 @ no -> fault
457
458 str r2, [r0] @ hardware version
459 mov ip, #0
460 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
461 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
462 mov pc, lr
463
464
465 .ltorg
466
467 .align
468
469 __INIT
470
471 .type __xscale_setup, #function
472__xscale_setup:
473 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
474 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
475 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
476#ifdef CONFIG_IWMMXT
477 mov r0, #0 @ initially disallow access to CP0/CP1
478#else
479 mov r0, #1 @ Allow access to CP0
480#endif
481 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
482 orr r0, r0, #1 << 13 @ Its undefined whether this
483 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
22b19086
RK		 484
485 adr r5, xscale_crval
486 ldmia r5, {r5, r6}
1da177e4 487 mrc p15, 0, r0, c1, c0, 0 @ get control register
1da177e4 488 bic r0, r0, r5
22b19086 489 orr r0, r0, r6
1da177e4
LT		 490 mov pc, lr
491 .size __xscale_setup, . - __xscale_setup
492
493 /*
494 * R
495 * .RVI ZFRS BLDP WCAM
496 * ..11 1.01 .... .101
497 *
498 */
22b19086
RK		 499 .type xscale_crval, #object
500xscale_crval:
501 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
1da177e4
LT		 502
503 __INITDATA
504
505/*
506 * Purpose : Function pointers used to access above functions - all calls
507 * come through these
508 */
509
510 .type xscale_processor_functions, #object
511ENTRY(xscale_processor_functions)
512 .word v5t_early_abort
513 .word cpu_xscale_proc_init
514 .word cpu_xscale_proc_fin
515 .word cpu_xscale_reset
516 .word cpu_xscale_do_idle
517 .word cpu_xscale_dcache_clean_area
518 .word cpu_xscale_switch_mm
519 .word cpu_xscale_set_pte
520 .size xscale_processor_functions, . - xscale_processor_functions
521
522 .section ".rodata"
523
524 .type cpu_arch_name, #object
525cpu_arch_name:
526 .asciz "armv5te"
527 .size cpu_arch_name, . - cpu_arch_name
528
529 .type cpu_elf_name, #object
530cpu_elf_name:
531 .asciz "v5"
532 .size cpu_elf_name, . - cpu_elf_name
533
534 .type cpu_80200_name, #object
535cpu_80200_name:
536 .asciz "XScale-80200"
537 .size cpu_80200_name, . - cpu_80200_name
538
a6a38a66
LB		 539 .type cpu_80219_name, #object
540cpu_80219_name:
541 .asciz "XScale-80219"
542 .size cpu_80219_name, . - cpu_80219_name
543
1da177e4
LT		 544 .type cpu_8032x_name, #object
545cpu_8032x_name:
546 .asciz "XScale-IOP8032x Family"
547 .size cpu_8032x_name, . - cpu_8032x_name
548
549 .type cpu_8033x_name, #object
550cpu_8033x_name:
551 .asciz "XScale-IOP8033x Family"
552 .size cpu_8033x_name, . - cpu_8033x_name
553
554 .type cpu_pxa250_name, #object
555cpu_pxa250_name:
556 .asciz "XScale-PXA250"
557 .size cpu_pxa250_name, . - cpu_pxa250_name
558
559 .type cpu_pxa210_name, #object
560cpu_pxa210_name:
561 .asciz "XScale-PXA210"
562 .size cpu_pxa210_name, . - cpu_pxa210_name
563
564 .type cpu_ixp42x_name, #object
565cpu_ixp42x_name:
566 .asciz "XScale-IXP42x Family"
567 .size cpu_ixp42x_name, . - cpu_ixp42x_name
568
569 .type cpu_ixp46x_name, #object
570cpu_ixp46x_name:
571 .asciz "XScale-IXP46x Family"
572 .size cpu_ixp46x_name, . - cpu_ixp46x_name
573
574 .type cpu_ixp2400_name, #object
575cpu_ixp2400_name:
576 .asciz "XScale-IXP2400"
577 .size cpu_ixp2400_name, . - cpu_ixp2400_name
578
579 .type cpu_ixp2800_name, #object
580cpu_ixp2800_name:
581 .asciz "XScale-IXP2800"
582 .size cpu_ixp2800_name, . - cpu_ixp2800_name
583
584 .type cpu_pxa255_name, #object
585cpu_pxa255_name:
586 .asciz "XScale-PXA255"
587 .size cpu_pxa255_name, . - cpu_pxa255_name
588
589 .type cpu_pxa270_name, #object
590cpu_pxa270_name:
591 .asciz "XScale-PXA270"
592 .size cpu_pxa270_name, . - cpu_pxa270_name
593
594 .align
595
02b7dd12 596 .section ".proc.info.init", #alloc, #execinstr
1da177e4
LT		 597
598 .type __80200_proc_info,#object
599__80200_proc_info:
600 .long 0x69052000
601 .long 0xfffffff0
602 .long PMD_TYPE_SECT | \
603 PMD_SECT_BUFFERABLE | \
604 PMD_SECT_CACHEABLE | \
605 PMD_SECT_AP_WRITE | \
606 PMD_SECT_AP_READ
8799ee9f
RK		 607 .long PMD_TYPE_SECT | \
608 PMD_SECT_AP_WRITE | \
609 PMD_SECT_AP_READ
1da177e4
LT		 610 b __xscale_setup
611 .long cpu_arch_name
612 .long cpu_elf_name
613 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
614 .long cpu_80200_name
615 .long xscale_processor_functions
616 .long v4wbi_tlb_fns
617 .long xscale_mc_user_fns
618 .long xscale_cache_fns
619 .size __80200_proc_info, . - __80200_proc_info
620
a6a38a66
LB		 621 .type __80219_proc_info,#object
622__80219_proc_info:
623 .long 0x69052e20
624 .long 0xffffffe0
625 .long PMD_TYPE_SECT | \
626 PMD_SECT_BUFFERABLE | \
627 PMD_SECT_CACHEABLE | \
628 PMD_SECT_AP_WRITE | \
629 PMD_SECT_AP_READ
630 .long PMD_TYPE_SECT | \
631 PMD_SECT_AP_WRITE | \
632 PMD_SECT_AP_READ
633 b __xscale_setup
634 .long cpu_arch_name
635 .long cpu_elf_name
636 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
637 .long cpu_80219_name
638 .long xscale_processor_functions
639 .long v4wbi_tlb_fns
640 .long xscale_mc_user_fns
641 .long xscale_cache_fns
642 .size __80219_proc_info, . - __80219_proc_info
643
1da177e4
LT		 644 .type __8032x_proc_info,#object
645__8032x_proc_info:
646 .long 0x69052420
a6a38a66 647 .long 0xffffffe0
1da177e4
LT		 648 .long PMD_TYPE_SECT | \
649 PMD_SECT_BUFFERABLE | \
650 PMD_SECT_CACHEABLE | \
651 PMD_SECT_AP_WRITE | \
652 PMD_SECT_AP_READ
8799ee9f
RK		 653 .long PMD_TYPE_SECT | \
654 PMD_SECT_AP_WRITE | \
655 PMD_SECT_AP_READ
1da177e4
LT		 656 b __xscale_setup
657 .long cpu_arch_name
658 .long cpu_elf_name
659 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
660 .long cpu_8032x_name
661 .long xscale_processor_functions
662 .long v4wbi_tlb_fns
663 .long xscale_mc_user_fns
664 .long xscale_cache_fns
665 .size __8032x_proc_info, . - __8032x_proc_info
666
667 .type __8033x_proc_info,#object
668__8033x_proc_info:
669 .long 0x69054010
670 .long 0xffffff30
671 .long PMD_TYPE_SECT | \
672 PMD_SECT_BUFFERABLE | \
673 PMD_SECT_CACHEABLE | \
674 PMD_SECT_AP_WRITE | \
675 PMD_SECT_AP_READ
8799ee9f
RK		 676 .long PMD_TYPE_SECT | \
677 PMD_SECT_AP_WRITE | \
678 PMD_SECT_AP_READ
1da177e4
LT		 679 b __xscale_setup
680 .long cpu_arch_name
681 .long cpu_elf_name
682 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
683 .long cpu_8033x_name
684 .long xscale_processor_functions
685 .long v4wbi_tlb_fns
686 .long xscale_mc_user_fns
687 .long xscale_cache_fns
688 .size __8033x_proc_info, . - __8033x_proc_info
689
690 .type __pxa250_proc_info,#object
691__pxa250_proc_info:
692 .long 0x69052100
693 .long 0xfffff7f0
694 .long PMD_TYPE_SECT | \
695 PMD_SECT_BUFFERABLE | \
696 PMD_SECT_CACHEABLE | \
697 PMD_SECT_AP_WRITE | \
698 PMD_SECT_AP_READ
8799ee9f
RK		 699 .long PMD_TYPE_SECT | \
700 PMD_SECT_AP_WRITE | \
701 PMD_SECT_AP_READ
1da177e4
LT		 702 b __xscale_setup
703 .long cpu_arch_name
704 .long cpu_elf_name
705 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
706 .long cpu_pxa250_name
707 .long xscale_processor_functions
708 .long v4wbi_tlb_fns
709 .long xscale_mc_user_fns
710 .long xscale_cache_fns
711 .size __pxa250_proc_info, . - __pxa250_proc_info
712
713 .type __pxa210_proc_info,#object
714__pxa210_proc_info:
715 .long 0x69052120
716 .long 0xfffff3f0
717 .long PMD_TYPE_SECT | \
718 PMD_SECT_BUFFERABLE | \
719 PMD_SECT_CACHEABLE | \
720 PMD_SECT_AP_WRITE | \
721 PMD_SECT_AP_READ
8799ee9f
RK		 722 .long PMD_TYPE_SECT | \
723 PMD_SECT_AP_WRITE | \
724 PMD_SECT_AP_READ
1da177e4
LT		 725 b __xscale_setup
726 .long cpu_arch_name
727 .long cpu_elf_name
728 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
729 .long cpu_pxa210_name
730 .long xscale_processor_functions
731 .long v4wbi_tlb_fns
732 .long xscale_mc_user_fns
733 .long xscale_cache_fns
734 .size __pxa210_proc_info, . - __pxa210_proc_info
735
736 .type __ixp2400_proc_info, #object
737__ixp2400_proc_info:
738 .long 0x69054190
739 .long 0xfffffff0
740 .long PMD_TYPE_SECT | \
741 PMD_SECT_BUFFERABLE | \
742 PMD_SECT_CACHEABLE | \
743 PMD_SECT_AP_WRITE | \
744 PMD_SECT_AP_READ
8799ee9f
RK		 745 .long PMD_TYPE_SECT | \
746 PMD_SECT_AP_WRITE | \
747 PMD_SECT_AP_READ
1da177e4
LT		 748 b __xscale_setup
749 .long cpu_arch_name
750 .long cpu_elf_name
751 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
752 .long cpu_ixp2400_name
753 .long xscale_processor_functions
754 .long v4wbi_tlb_fns
755 .long xscale_mc_user_fns
756 .long xscale_cache_fns
757 .size __ixp2400_proc_info, . - __ixp2400_proc_info
758
759 .type __ixp2800_proc_info, #object
760__ixp2800_proc_info:
761 .long 0x690541a0
762 .long 0xfffffff0
763 .long PMD_TYPE_SECT | \
764 PMD_SECT_BUFFERABLE | \
765 PMD_SECT_CACHEABLE | \
766 PMD_SECT_AP_WRITE | \
767 PMD_SECT_AP_READ
8799ee9f
RK		 768 .long PMD_TYPE_SECT | \
769 PMD_SECT_AP_WRITE | \
770 PMD_SECT_AP_READ
1da177e4
LT		 771 b __xscale_setup
772 .long cpu_arch_name
773 .long cpu_elf_name
774 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
775 .long cpu_ixp2800_name
776 .long xscale_processor_functions
777 .long v4wbi_tlb_fns
778 .long xscale_mc_user_fns
779 .long xscale_cache_fns
780 .size __ixp2800_proc_info, . - __ixp2800_proc_info
781
782 .type __ixp42x_proc_info, #object
783__ixp42x_proc_info:
784 .long 0x690541c0
785 .long 0xffffffc0
786 .long PMD_TYPE_SECT | \
787 PMD_SECT_BUFFERABLE | \
788 PMD_SECT_CACHEABLE | \
789 PMD_SECT_AP_WRITE | \
790 PMD_SECT_AP_READ
8799ee9f
RK		 791 .long PMD_TYPE_SECT | \
792 PMD_SECT_AP_WRITE | \
793 PMD_SECT_AP_READ
1da177e4
LT		 794 b __xscale_setup
795 .long cpu_arch_name
796 .long cpu_elf_name
797 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
798 .long cpu_ixp42x_name
799 .long xscale_processor_functions
800 .long v4wbi_tlb_fns
801 .long xscale_mc_user_fns
802 .long xscale_cache_fns
803 .size __ixp42x_proc_info, . - __ixp42x_proc_info
804
805 .type __ixp46x_proc_info, #object
806__ixp46x_proc_info:
807 .long 0x69054200
808 .long 0xffffff00
8799ee9f
RK		 809 .long PMD_TYPE_SECT | \
810 PMD_SECT_BUFFERABLE | \
811 PMD_SECT_CACHEABLE | \
812 PMD_SECT_AP_WRITE | \
813 PMD_SECT_AP_READ
814 .long PMD_TYPE_SECT | \
815 PMD_SECT_AP_WRITE | \
816 PMD_SECT_AP_READ
1da177e4
LT		 817 b __xscale_setup
818 .long cpu_arch_name
819 .long cpu_elf_name
820 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
821 .long cpu_ixp46x_name
822 .long xscale_processor_functions
823 .long v4wbi_tlb_fns
824 .long xscale_mc_user_fns
825 .long xscale_cache_fns
826 .size __ixp46x_proc_info, . - __ixp46x_proc_info
827
828 .type __pxa255_proc_info,#object
829__pxa255_proc_info:
830 .long 0x69052d00
831 .long 0xfffffff0
832 .long PMD_TYPE_SECT | \
833 PMD_SECT_BUFFERABLE | \
834 PMD_SECT_CACHEABLE | \
835 PMD_SECT_AP_WRITE | \
836 PMD_SECT_AP_READ
8799ee9f
RK		 837 .long PMD_TYPE_SECT | \
838 PMD_SECT_AP_WRITE | \
839 PMD_SECT_AP_READ
1da177e4
LT		 840 b __xscale_setup
841 .long cpu_arch_name
842 .long cpu_elf_name
843 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
844 .long cpu_pxa255_name
845 .long xscale_processor_functions
846 .long v4wbi_tlb_fns
847 .long xscale_mc_user_fns
848 .long xscale_cache_fns
849 .size __pxa255_proc_info, . - __pxa255_proc_info
850
851 .type __pxa270_proc_info,#object
852__pxa270_proc_info:
853 .long 0x69054110
854 .long 0xfffffff0
855 .long PMD_TYPE_SECT | \
856 PMD_SECT_BUFFERABLE | \
857 PMD_SECT_CACHEABLE | \
858 PMD_SECT_AP_WRITE | \
859 PMD_SECT_AP_READ
8799ee9f
RK		 860 .long PMD_TYPE_SECT | \
861 PMD_SECT_AP_WRITE | \
862 PMD_SECT_AP_READ
1da177e4
LT		 863 b __xscale_setup
864 .long cpu_arch_name
865 .long cpu_elf_name
866 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
867 .long cpu_pxa270_name
868 .long xscale_processor_functions
869 .long v4wbi_tlb_fns
870 .long xscale_mc_user_fns
871 .long xscale_cache_fns
872 .size __pxa270_proc_info, . - __pxa270_proc_info
873
Linux kernel - Deliverables
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