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[ARM] Convert set_pte_ext implementions to macros
[deliverable/linux.git] / arch / arm / mm / proc-xscale.S
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/mm/proc-xscale.S
3 *
4 * Author: Nicolas Pitre
5 * Created: November 2000
6 * Copyright: (C) 2000, 2001 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * MMU functions for the Intel XScale CPUs
13 *
14 * 2001 Aug 21:
15 * some contributions by Brett Gaines <brett.w.gaines@intel.com>
16 * Copyright 2001 by Intel Corp.
17 *
18 * 2001 Sep 08:
19 * Completely revisited, many important fixes
20 * Nicolas Pitre <nico@cam.org>
21 */
22
23#include <linux/linkage.h>
24#include <linux/init.h>
25#include <asm/assembler.h>
ee90dabc 26#include <asm/elf.h>
1da177e4 27#include <asm/pgtable.h>
0003cedf 28#include <asm/pgtable-hwdef.h>
1da177e4
LT		 29#include <asm/page.h>
30#include <asm/ptrace.h>
31#include "proc-macros.S"
32
33/*
34 * This is the maximum size of an area which will be flushed. If the area
35 * is larger than this, then we flush the whole cache
36 */
37#define MAX_AREA_SIZE 32768
38
39/*
40 * the cache line size of the I and D cache
41 */
42#define CACHELINESIZE 32
43
44/*
45 * the size of the data cache
46 */
47#define CACHESIZE 32768
48
49/*
50 * Virtual address used to allocate the cache when flushed
51 *
52 * This must be an address range which is _never_ used. It should
53 * apparently have a mapping in the corresponding page table for
54 * compatibility with future CPUs that _could_ require it. For instance we
55 * don't care.
56 *
57 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
58 * the 2 areas in alternance each time the clean_d_cache macro is used.
59 * Without this the XScale core exhibits cache eviction problems and no one
60 * knows why.
61 *
62 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
63 */
64#define CLEAN_ADDR 0xfffe0000
65
66/*
67 * This macro is used to wait for a CP15 write and is needed
68 * when we have to ensure that the last operation to the co-pro
69 * was completed before continuing with operation.
70 */
71 .macro cpwait, rd
72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
73 mov \rd, \rd @ wait for completion
74 sub pc, pc, #4 @ flush instruction pipeline
75 .endm
76
77 .macro cpwait_ret, lr, rd
78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
79 sub pc, \lr, \rd, LSR #32 @ wait for completion and
80 @ flush instruction pipeline
81 .endm
82
83/*
84 * This macro cleans the entire dcache using line allocate.
85 * The main loop has been unrolled to reduce loop overhead.
86 * rd and rs are two scratch registers.
87 */
88 .macro clean_d_cache, rd, rs
89 ldr \rs, =clean_addr
90 ldr \rd, [\rs]
91 eor \rd, \rd, #CACHESIZE
92 str \rd, [\rs]
93 add \rs, \rd, #CACHESIZE
941: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 add \rd, \rd, #CACHELINESIZE
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 add \rd, \rd, #CACHELINESIZE
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
99 add \rd, \rd, #CACHELINESIZE
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
101 add \rd, \rd, #CACHELINESIZE
102 teq \rd, \rs
103 bne 1b
104 .endm
105
106 .data
107clean_addr: .word CLEAN_ADDR
108
109 .text
110
111/*
112 * cpu_xscale_proc_init()
113 *
114 * Nothing too exciting at the moment
115 */
116ENTRY(cpu_xscale_proc_init)
391c569d
AP		 117 @ enable write buffer coalescing. Some bootloader disable it
118 mrc p15, 0, r1, c1, c0, 1
119 bic r1, r1, #1
120 mcr p15, 0, r1, c1, c0, 1
1da177e4
LT		 121 mov pc, lr
122
123/*
124 * cpu_xscale_proc_fin()
125 */
126ENTRY(cpu_xscale_proc_fin)
127 str lr, [sp, #-4]!
128 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
129 msr cpsr_c, r0
130 bl xscale_flush_kern_cache_all @ clean caches
131 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
132 bic r0, r0, #0x1800 @ ...IZ...........
133 bic r0, r0, #0x0006 @ .............CA.
134 mcr p15, 0, r0, c1, c0, 0 @ disable caches
135 ldr pc, [sp], #4
136
137/*
138 * cpu_xscale_reset(loc)
139 *
140 * Perform a soft reset of the system. Put the CPU into the
141 * same state as it would be if it had been reset, and branch
142 * to what would be the reset vector.
143 *
144 * loc: location to jump to for soft reset
2dc7667b
NP		 145 *
146 * Beware PXA270 erratum E7.
1da177e4
LT		 147 */
148 .align 5
149ENTRY(cpu_xscale_reset)
150 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
151 msr cpsr_c, r1 @ reset CPSR
2dc7667b
NP		 152 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
153 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
1da177e4
LT		 154 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
155 bic r1, r1, #0x0086 @ ........B....CA.
156 bic r1, r1, #0x3900 @ ..VIZ..S........
2dc7667b
NP		 157 sub pc, pc, #4 @ flush pipeline
158 @ *** cache line aligned ***
1da177e4 159 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
1da177e4 160 bic r1, r1, #0x0001 @ ...............M
2dc7667b 161 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
1da177e4
LT		 162 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
163 @ CAUTION: MMU turned off from this point. We count on the pipeline
164 @ already containing those two last instructions to survive.
165 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
166 mov pc, r0
167
168/*
169 * cpu_xscale_do_idle()
170 *
171 * Cause the processor to idle
172 *
173 * For now we do nothing but go to idle mode for every case
174 *
175 * XScale supports clock switching, but using idle mode support
176 * allows external hardware to react to system state changes.
177 */
178 .align 5
179
180ENTRY(cpu_xscale_do_idle)
181 mov r0, #1
182 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
183 mov pc, lr
184
185/* ================================= CACHE ================================ */
186
187/*
188 * flush_user_cache_all()
189 *
190 * Invalidate all cache entries in a particular address
191 * space.
192 */
193ENTRY(xscale_flush_user_cache_all)
194 /* FALLTHROUGH */
195
196/*
197 * flush_kern_cache_all()
198 *
199 * Clean and invalidate the entire cache.
200 */
201ENTRY(xscale_flush_kern_cache_all)
202 mov r2, #VM_EXEC
203 mov ip, #0
204__flush_whole_cache:
205 clean_d_cache r0, r1
206 tst r2, #VM_EXEC
207 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
208 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
209 mov pc, lr
210
211/*
212 * flush_user_cache_range(start, end, vm_flags)
213 *
214 * Invalidate a range of cache entries in the specified
215 * address space.
216 *
217 * - start - start address (may not be aligned)
218 * - end - end address (exclusive, may not be aligned)
219 * - vma - vma_area_struct describing address space
220 */
221 .align 5
222ENTRY(xscale_flush_user_cache_range)
223 mov ip, #0
224 sub r3, r1, r0 @ calculate total size
225 cmp r3, #MAX_AREA_SIZE
226 bhs __flush_whole_cache
227
2281: tst r2, #VM_EXEC
229 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
230 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
231 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
232 add r0, r0, #CACHELINESIZE
233 cmp r0, r1
234 blo 1b
235 tst r2, #VM_EXEC
236 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
237 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
238 mov pc, lr
239
240/*
241 * coherent_kern_range(start, end)
242 *
243 * Ensure coherency between the Icache and the Dcache in the
244 * region described by start. If you have non-snooping
245 * Harvard caches, you need to implement this function.
246 *
247 * - start - virtual start address
248 * - end - virtual end address
249 *
250 * Note: single I-cache line invalidation isn't used here since
251 * it also trashes the mini I-cache used by JTAG debuggers.
252 */
253ENTRY(xscale_coherent_kern_range)
8a052e0b
NP		 254 bic r0, r0, #CACHELINESIZE - 1
2551: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
256 add r0, r0, #CACHELINESIZE
257 cmp r0, r1
258 blo 1b
259 mov r0, #0
260 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
261 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
262 mov pc, lr
1da177e4
LT		 263
264/*
265 * coherent_user_range(start, end)
266 *
267 * Ensure coherency between the Icache and the Dcache in the
268 * region described by start. If you have non-snooping
269 * Harvard caches, you need to implement this function.
270 *
271 * - start - virtual start address
272 * - end - virtual end address
1da177e4
LT		 273 */
274ENTRY(xscale_coherent_user_range)
275 bic r0, r0, #CACHELINESIZE - 1
2761: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
8a052e0b 277 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
1da177e4
LT		 278 add r0, r0, #CACHELINESIZE
279 cmp r0, r1
280 blo 1b
281 mov r0, #0
8a052e0b 282 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
1da177e4
LT		 283 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
284 mov pc, lr
285
286/*
287 * flush_kern_dcache_page(void *page)
288 *
289 * Ensure no D cache aliasing occurs, either with itself or
290 * the I cache
291 *
292 * - addr - page aligned address
293 */
294ENTRY(xscale_flush_kern_dcache_page)
295 add r1, r0, #PAGE_SZ
2961: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
297 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
298 add r0, r0, #CACHELINESIZE
299 cmp r0, r1
300 blo 1b
301 mov r0, #0
302 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
303 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
304 mov pc, lr
305
306/*
307 * dma_inv_range(start, end)
308 *
309 * Invalidate (discard) the specified virtual address range.
310 * May not write back any entries. If 'start' or 'end'
311 * are not cache line aligned, those lines must be written
312 * back.
313 *
314 * - start - virtual start address
315 * - end - virtual end address
316 */
317ENTRY(xscale_dma_inv_range)
1da177e4
LT		 318 tst r0, #CACHELINESIZE - 1
319 bic r0, r0, #CACHELINESIZE - 1
320 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
321 tst r1, #CACHELINESIZE - 1
322 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
3231: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
324 add r0, r0, #CACHELINESIZE
325 cmp r0, r1
326 blo 1b
327 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
328 mov pc, lr
329
330/*
331 * dma_clean_range(start, end)
332 *
333 * Clean the specified virtual address range.
334 *
335 * - start - virtual start address
336 * - end - virtual end address
337 */
338ENTRY(xscale_dma_clean_range)
339 bic r0, r0, #CACHELINESIZE - 1
3401: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
341 add r0, r0, #CACHELINESIZE
342 cmp r0, r1
343 blo 1b
344 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
345 mov pc, lr
346
347/*
348 * dma_flush_range(start, end)
349 *
350 * Clean and invalidate the specified virtual address range.
351 *
352 * - start - virtual start address
353 * - end - virtual end address
354 */
355ENTRY(xscale_dma_flush_range)
356 bic r0, r0, #CACHELINESIZE - 1
3571: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
358 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
359 add r0, r0, #CACHELINESIZE
360 cmp r0, r1
361 blo 1b
362 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
363 mov pc, lr
364
365ENTRY(xscale_cache_fns)
366 .long xscale_flush_kern_cache_all
367 .long xscale_flush_user_cache_all
368 .long xscale_flush_user_cache_range
369 .long xscale_coherent_kern_range
370 .long xscale_coherent_user_range
371 .long xscale_flush_kern_dcache_page
372 .long xscale_dma_inv_range
373 .long xscale_dma_clean_range
374 .long xscale_dma_flush_range
375
197c9444
LB		 376/*
377 * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
378 * clear the dirty bits, which means that if we invalidate a dirty line,
379 * the dirty data can still be written back to external memory later on.
380 *
381 * The recommended workaround is to always do a clean D-cache line before
382 * doing an invalidate D-cache line, so on the affected processors,
383 * dma_inv_range() is implemented as dma_flush_range().
384 *
385 * See erratum #25 of "Intel 80200 Processor Specification Update",
386 * revision January 22, 2003, available at:
387 * http://www.intel.com/design/iio/specupdt/273415.htm
388 */
389ENTRY(xscale_80200_A0_A1_cache_fns)
390 .long xscale_flush_kern_cache_all
391 .long xscale_flush_user_cache_all
392 .long xscale_flush_user_cache_range
393 .long xscale_coherent_kern_range
394 .long xscale_coherent_user_range
395 .long xscale_flush_kern_dcache_page
396 .long xscale_dma_flush_range
397 .long xscale_dma_clean_range
398 .long xscale_dma_flush_range
399
1da177e4
LT		 400ENTRY(cpu_xscale_dcache_clean_area)
4011: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
402 add r0, r0, #CACHELINESIZE
403 subs r1, r1, #CACHELINESIZE
404 bhi 1b
405 mov pc, lr
406
1da177e4
LT		 407/* =============================== PageTable ============================== */
408
409#define PTE_CACHE_WRITE_ALLOCATE 0
410
411/*
412 * cpu_xscale_switch_mm(pgd)
413 *
414 * Set the translation base pointer to be as described by pgd.
415 *
416 * pgd: new page tables
417 */
418 .align 5
419ENTRY(cpu_xscale_switch_mm)
420 clean_d_cache r1, r2
421 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
422 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
423 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
424 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
425 cpwait_ret lr, ip
426
427/*
ad1ae2fe 428 * cpu_xscale_set_pte_ext(ptep, pte, ext)
1da177e4
LT		 429 *
430 * Set a PTE and flush it out
431 *
432 * Errata 40: must set memory to write-through for user read-only pages.
433 */
434 .align 5
ad1ae2fe 435ENTRY(cpu_xscale_set_pte_ext)
da091653 436 xscale_set_pte_ext_prologue
1da177e4
LT		 437 @
438 @ Handle the X bit. We want to set this bit for the minicache
439 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
440 @ and we have a writeable, cacheable region. If we ignore the
441 @ U and E bits, we can allow user space to use the minicache as
442 @ well.
443 @
444 @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
445 @
da091653
RK		 446 and ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
447 teq ip, #L_PTE_CACHEABLE
1da177e4 448#if PTE_CACHE_WRITE_ALLOCATE
da091653 449 teqne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
1da177e4
LT		 450#endif
451 orreq r2, r2, #PTE_EXT_TEX(1)
452
453 @
454 @ Erratum 40: The B bit must be cleared for a user read-only
455 @ cacheable page.
456 @
457 @ B = B & ~(U & C & ~W)
458 @
459 and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
460 teq ip, #L_PTE_USER | L_PTE_CACHEABLE
461 biceq r2, r2, #PTE_BUFFERABLE
462
da091653 463 xscale_set_pte_ext_epilogue
1da177e4
LT		 464 mov pc, lr
465
466
467 .ltorg
468
469 .align
470
471 __INIT
472
473 .type __xscale_setup, #function
474__xscale_setup:
475 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
476 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
477 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
afe4b25e 478 mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
1da177e4
LT		 479 orr r0, r0, #1 << 13 @ Its undefined whether this
480 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
22b19086
RK		 481
482 adr r5, xscale_crval
483 ldmia r5, {r5, r6}
1da177e4 484 mrc p15, 0, r0, c1, c0, 0 @ get control register
1da177e4 485 bic r0, r0, r5
22b19086 486 orr r0, r0, r6
1da177e4
LT		 487 mov pc, lr
488 .size __xscale_setup, . - __xscale_setup
489
490 /*
491 * R
492 * .RVI ZFRS BLDP WCAM
493 * ..11 1.01 .... .101
494 *
495 */
22b19086
RK		 496 .type xscale_crval, #object
497xscale_crval:
498 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
1da177e4
LT		 499
500 __INITDATA
501
502/*
503 * Purpose : Function pointers used to access above functions - all calls
504 * come through these
505 */
506
507 .type xscale_processor_functions, #object
508ENTRY(xscale_processor_functions)
509 .word v5t_early_abort
4a1fd556 510 .word pabort_noifar
1da177e4
LT		 511 .word cpu_xscale_proc_init
512 .word cpu_xscale_proc_fin
513 .word cpu_xscale_reset
514 .word cpu_xscale_do_idle
515 .word cpu_xscale_dcache_clean_area
516 .word cpu_xscale_switch_mm
ad1ae2fe 517 .word cpu_xscale_set_pte_ext
1da177e4
LT		 518 .size xscale_processor_functions, . - xscale_processor_functions
519
520 .section ".rodata"
521
522 .type cpu_arch_name, #object
523cpu_arch_name:
524 .asciz "armv5te"
525 .size cpu_arch_name, . - cpu_arch_name
526
527 .type cpu_elf_name, #object
528cpu_elf_name:
529 .asciz "v5"
530 .size cpu_elf_name, . - cpu_elf_name
531
197c9444
LB		 532 .type cpu_80200_A0_A1_name, #object
533cpu_80200_A0_A1_name:
534 .asciz "XScale-80200 A0/A1"
535 .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
536
1da177e4
LT		 537 .type cpu_80200_name, #object
538cpu_80200_name:
539 .asciz "XScale-80200"
540 .size cpu_80200_name, . - cpu_80200_name
541
a6a38a66
LB		 542 .type cpu_80219_name, #object
543cpu_80219_name:
544 .asciz "XScale-80219"
545 .size cpu_80219_name, . - cpu_80219_name
546
1da177e4
LT		 547 .type cpu_8032x_name, #object
548cpu_8032x_name:
549 .asciz "XScale-IOP8032x Family"
550 .size cpu_8032x_name, . - cpu_8032x_name
551
552 .type cpu_8033x_name, #object
553cpu_8033x_name:
554 .asciz "XScale-IOP8033x Family"
555 .size cpu_8033x_name, . - cpu_8033x_name
556
557 .type cpu_pxa250_name, #object
558cpu_pxa250_name:
559 .asciz "XScale-PXA250"
560 .size cpu_pxa250_name, . - cpu_pxa250_name
561
562 .type cpu_pxa210_name, #object
563cpu_pxa210_name:
564 .asciz "XScale-PXA210"
565 .size cpu_pxa210_name, . - cpu_pxa210_name
566
567 .type cpu_ixp42x_name, #object
568cpu_ixp42x_name:
569 .asciz "XScale-IXP42x Family"
570 .size cpu_ixp42x_name, . - cpu_ixp42x_name
571
45fba084
RS		 572 .type cpu_ixp43x_name, #object
573cpu_ixp43x_name:
574 .asciz "XScale-IXP43x Family"
575 .size cpu_ixp43x_name, . - cpu_ixp43x_name
576
1da177e4
LT		 577 .type cpu_ixp46x_name, #object
578cpu_ixp46x_name:
579 .asciz "XScale-IXP46x Family"
580 .size cpu_ixp46x_name, . - cpu_ixp46x_name
581
582 .type cpu_ixp2400_name, #object
583cpu_ixp2400_name:
584 .asciz "XScale-IXP2400"
585 .size cpu_ixp2400_name, . - cpu_ixp2400_name
586
587 .type cpu_ixp2800_name, #object
588cpu_ixp2800_name:
589 .asciz "XScale-IXP2800"
590 .size cpu_ixp2800_name, . - cpu_ixp2800_name
591
592 .type cpu_pxa255_name, #object
593cpu_pxa255_name:
594 .asciz "XScale-PXA255"
595 .size cpu_pxa255_name, . - cpu_pxa255_name
596
597 .type cpu_pxa270_name, #object
598cpu_pxa270_name:
599 .asciz "XScale-PXA270"
600 .size cpu_pxa270_name, . - cpu_pxa270_name
601
602 .align
603
02b7dd12 604 .section ".proc.info.init", #alloc, #execinstr
1da177e4 605
197c9444
LB		 606 .type __80200_A0_A1_proc_info,#object
607__80200_A0_A1_proc_info:
608 .long 0x69052000
609 .long 0xfffffffe
610 .long PMD_TYPE_SECT | \
611 PMD_SECT_BUFFERABLE | \
612 PMD_SECT_CACHEABLE | \
613 PMD_SECT_AP_WRITE | \
614 PMD_SECT_AP_READ
615 .long PMD_TYPE_SECT | \
616 PMD_SECT_AP_WRITE | \
617 PMD_SECT_AP_READ
618 b __xscale_setup
619 .long cpu_arch_name
620 .long cpu_elf_name
621 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
622 .long cpu_80200_name
623 .long xscale_processor_functions
624 .long v4wbi_tlb_fns
625 .long xscale_mc_user_fns
626 .long xscale_80200_A0_A1_cache_fns
627 .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
628
1da177e4
LT		 629 .type __80200_proc_info,#object
630__80200_proc_info:
631 .long 0x69052000
632 .long 0xfffffff0
633 .long PMD_TYPE_SECT | \
634 PMD_SECT_BUFFERABLE | \
635 PMD_SECT_CACHEABLE | \
636 PMD_SECT_AP_WRITE | \
637 PMD_SECT_AP_READ
8799ee9f
RK		 638 .long PMD_TYPE_SECT | \
639 PMD_SECT_AP_WRITE | \
640 PMD_SECT_AP_READ
1da177e4
LT		 641 b __xscale_setup
642 .long cpu_arch_name
643 .long cpu_elf_name
644 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
645 .long cpu_80200_name
646 .long xscale_processor_functions
647 .long v4wbi_tlb_fns
648 .long xscale_mc_user_fns
649 .long xscale_cache_fns
650 .size __80200_proc_info, . - __80200_proc_info
651
a6a38a66
LB		 652 .type __80219_proc_info,#object
653__80219_proc_info:
654 .long 0x69052e20
655 .long 0xffffffe0
656 .long PMD_TYPE_SECT | \
657 PMD_SECT_BUFFERABLE | \
658 PMD_SECT_CACHEABLE | \
659 PMD_SECT_AP_WRITE | \
660 PMD_SECT_AP_READ
661 .long PMD_TYPE_SECT | \
662 PMD_SECT_AP_WRITE | \
663 PMD_SECT_AP_READ
664 b __xscale_setup
665 .long cpu_arch_name
666 .long cpu_elf_name
667 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
668 .long cpu_80219_name
669 .long xscale_processor_functions
670 .long v4wbi_tlb_fns
671 .long xscale_mc_user_fns
672 .long xscale_cache_fns
673 .size __80219_proc_info, . - __80219_proc_info
674
1da177e4
LT		 675 .type __8032x_proc_info,#object
676__8032x_proc_info:
677 .long 0x69052420
36694a4c 678 .long 0xfffff7e0
1da177e4
LT		 679 .long PMD_TYPE_SECT | \
680 PMD_SECT_BUFFERABLE | \
681 PMD_SECT_CACHEABLE | \
682 PMD_SECT_AP_WRITE | \
683 PMD_SECT_AP_READ
8799ee9f
RK		 684 .long PMD_TYPE_SECT | \
685 PMD_SECT_AP_WRITE | \
686 PMD_SECT_AP_READ
1da177e4
LT		 687 b __xscale_setup
688 .long cpu_arch_name
689 .long cpu_elf_name
690 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
691 .long cpu_8032x_name
692 .long xscale_processor_functions
693 .long v4wbi_tlb_fns
694 .long xscale_mc_user_fns
695 .long xscale_cache_fns
696 .size __8032x_proc_info, . - __8032x_proc_info
697
698 .type __8033x_proc_info,#object
699__8033x_proc_info:
700 .long 0x69054010
7f215abc 701 .long 0xfffffd30
1da177e4
LT		 702 .long PMD_TYPE_SECT | \
703 PMD_SECT_BUFFERABLE | \
704 PMD_SECT_CACHEABLE | \
705 PMD_SECT_AP_WRITE | \
706 PMD_SECT_AP_READ
8799ee9f
RK		 707 .long PMD_TYPE_SECT | \
708 PMD_SECT_AP_WRITE | \
709 PMD_SECT_AP_READ
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LT		 710 b __xscale_setup
711 .long cpu_arch_name
712 .long cpu_elf_name
713 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
714 .long cpu_8033x_name
715 .long xscale_processor_functions
716 .long v4wbi_tlb_fns
717 .long xscale_mc_user_fns
718 .long xscale_cache_fns
719 .size __8033x_proc_info, . - __8033x_proc_info
720
721 .type __pxa250_proc_info,#object
722__pxa250_proc_info:
723 .long 0x69052100
724 .long 0xfffff7f0
725 .long PMD_TYPE_SECT | \
726 PMD_SECT_BUFFERABLE | \
727 PMD_SECT_CACHEABLE | \
728 PMD_SECT_AP_WRITE | \
729 PMD_SECT_AP_READ
8799ee9f
RK		 730 .long PMD_TYPE_SECT | \
731 PMD_SECT_AP_WRITE | \
732 PMD_SECT_AP_READ
1da177e4
LT		 733 b __xscale_setup
734 .long cpu_arch_name
735 .long cpu_elf_name
736 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
737 .long cpu_pxa250_name
738 .long xscale_processor_functions
739 .long v4wbi_tlb_fns
740 .long xscale_mc_user_fns
741 .long xscale_cache_fns
742 .size __pxa250_proc_info, . - __pxa250_proc_info
743
744 .type __pxa210_proc_info,#object
745__pxa210_proc_info:
746 .long 0x69052120
747 .long 0xfffff3f0
748 .long PMD_TYPE_SECT | \
749 PMD_SECT_BUFFERABLE | \
750 PMD_SECT_CACHEABLE | \
751 PMD_SECT_AP_WRITE | \
752 PMD_SECT_AP_READ
8799ee9f
RK		 753 .long PMD_TYPE_SECT | \
754 PMD_SECT_AP_WRITE | \
755 PMD_SECT_AP_READ
1da177e4
LT		 756 b __xscale_setup
757 .long cpu_arch_name
758 .long cpu_elf_name
759 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
760 .long cpu_pxa210_name
761 .long xscale_processor_functions
762 .long v4wbi_tlb_fns
763 .long xscale_mc_user_fns
764 .long xscale_cache_fns
765 .size __pxa210_proc_info, . - __pxa210_proc_info
766
767 .type __ixp2400_proc_info, #object
768__ixp2400_proc_info:
769 .long 0x69054190
770 .long 0xfffffff0
771 .long PMD_TYPE_SECT | \
772 PMD_SECT_BUFFERABLE | \
773 PMD_SECT_CACHEABLE | \
774 PMD_SECT_AP_WRITE | \
775 PMD_SECT_AP_READ
8799ee9f
RK		 776 .long PMD_TYPE_SECT | \
777 PMD_SECT_AP_WRITE | \
778 PMD_SECT_AP_READ
1da177e4
LT		 779 b __xscale_setup
780 .long cpu_arch_name
781 .long cpu_elf_name
782 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
783 .long cpu_ixp2400_name
784 .long xscale_processor_functions
785 .long v4wbi_tlb_fns
786 .long xscale_mc_user_fns
787 .long xscale_cache_fns
788 .size __ixp2400_proc_info, . - __ixp2400_proc_info
789
790 .type __ixp2800_proc_info, #object
791__ixp2800_proc_info:
792 .long 0x690541a0
793 .long 0xfffffff0
794 .long PMD_TYPE_SECT | \
795 PMD_SECT_BUFFERABLE | \
796 PMD_SECT_CACHEABLE | \
797 PMD_SECT_AP_WRITE | \
798 PMD_SECT_AP_READ
8799ee9f
RK		 799 .long PMD_TYPE_SECT | \
800 PMD_SECT_AP_WRITE | \
801 PMD_SECT_AP_READ
1da177e4
LT		 802 b __xscale_setup
803 .long cpu_arch_name
804 .long cpu_elf_name
805 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
806 .long cpu_ixp2800_name
807 .long xscale_processor_functions
808 .long v4wbi_tlb_fns
809 .long xscale_mc_user_fns
810 .long xscale_cache_fns
811 .size __ixp2800_proc_info, . - __ixp2800_proc_info
812
813 .type __ixp42x_proc_info, #object
814__ixp42x_proc_info:
815 .long 0x690541c0
816 .long 0xffffffc0
817 .long PMD_TYPE_SECT | \
818 PMD_SECT_BUFFERABLE | \
819 PMD_SECT_CACHEABLE | \
820 PMD_SECT_AP_WRITE | \
821 PMD_SECT_AP_READ
8799ee9f
RK		 822 .long PMD_TYPE_SECT | \
823 PMD_SECT_AP_WRITE | \
824 PMD_SECT_AP_READ
1da177e4
LT		 825 b __xscale_setup
826 .long cpu_arch_name
827 .long cpu_elf_name
828 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
829 .long cpu_ixp42x_name
830 .long xscale_processor_functions
831 .long v4wbi_tlb_fns
832 .long xscale_mc_user_fns
833 .long xscale_cache_fns
834 .size __ixp42x_proc_info, . - __ixp42x_proc_info
835
45fba084
RS		 836 .type __ixp43x_proc_info, #object
837__ixp43x_proc_info:
838 .long 0x69054040
839 .long 0xfffffff0
840 .long PMD_TYPE_SECT | \
841 PMD_SECT_BUFFERABLE | \
842 PMD_SECT_CACHEABLE | \
843 PMD_SECT_AP_WRITE | \
844 PMD_SECT_AP_READ
845 .long PMD_TYPE_SECT | \
846 PMD_SECT_AP_WRITE | \
847 PMD_SECT_AP_READ
848 b __xscale_setup
849 .long cpu_arch_name
850 .long cpu_elf_name
851 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
852 .long cpu_ixp43x_name
853 .long xscale_processor_functions
854 .long v4wbi_tlb_fns
855 .long xscale_mc_user_fns
856 .long xscale_cache_fns
857 .size __ixp43x_proc_info, . - __ixp43x_proc_info
858
1da177e4
LT		 859 .type __ixp46x_proc_info, #object
860__ixp46x_proc_info:
861 .long 0x69054200
862 .long 0xffffff00
8799ee9f
RK		 863 .long PMD_TYPE_SECT | \
864 PMD_SECT_BUFFERABLE | \
865 PMD_SECT_CACHEABLE | \
866 PMD_SECT_AP_WRITE | \
867 PMD_SECT_AP_READ
868 .long PMD_TYPE_SECT | \
869 PMD_SECT_AP_WRITE | \
870 PMD_SECT_AP_READ
1da177e4
LT		 871 b __xscale_setup
872 .long cpu_arch_name
873 .long cpu_elf_name
874 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
875 .long cpu_ixp46x_name
876 .long xscale_processor_functions
877 .long v4wbi_tlb_fns
878 .long xscale_mc_user_fns
879 .long xscale_cache_fns
880 .size __ixp46x_proc_info, . - __ixp46x_proc_info
881
882 .type __pxa255_proc_info,#object
883__pxa255_proc_info:
884 .long 0x69052d00
885 .long 0xfffffff0
886 .long PMD_TYPE_SECT | \
887 PMD_SECT_BUFFERABLE | \
888 PMD_SECT_CACHEABLE | \
889 PMD_SECT_AP_WRITE | \
890 PMD_SECT_AP_READ
8799ee9f
RK		 891 .long PMD_TYPE_SECT | \
892 PMD_SECT_AP_WRITE | \
893 PMD_SECT_AP_READ
1da177e4
LT		 894 b __xscale_setup
895 .long cpu_arch_name
896 .long cpu_elf_name
897 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
898 .long cpu_pxa255_name
899 .long xscale_processor_functions
900 .long v4wbi_tlb_fns
901 .long xscale_mc_user_fns
902 .long xscale_cache_fns
903 .size __pxa255_proc_info, . - __pxa255_proc_info
904
905 .type __pxa270_proc_info,#object
906__pxa270_proc_info:
907 .long 0x69054110
908 .long 0xfffffff0
909 .long PMD_TYPE_SECT | \
910 PMD_SECT_BUFFERABLE | \
911 PMD_SECT_CACHEABLE | \
912 PMD_SECT_AP_WRITE | \
913 PMD_SECT_AP_READ
8799ee9f
RK		 914 .long PMD_TYPE_SECT | \
915 PMD_SECT_AP_WRITE | \
916 PMD_SECT_AP_READ
1da177e4
LT		 917 b __xscale_setup
918 .long cpu_arch_name
919 .long cpu_elf_name
afe4b25e 920 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
1da177e4
LT		 921 .long cpu_pxa270_name
922 .long xscale_processor_functions
923 .long v4wbi_tlb_fns
924 .long xscale_mc_user_fns
925 .long xscale_cache_fns
926 .size __pxa270_proc_info, . - __pxa270_proc_info
927
Linux kernel - Deliverables
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