[deliverable/linux.git] / arch / arm / mm / tlb-v4wbi.S

/*
 *  linux/arch/arm/mm/tlbv4wbi.S
 *
 *  Copyright (C) 1997-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  ARM architecture version 4 and version 5 TLB handling functions.
 *  These assume a split I/D TLBs, with a write buffer.
 *
 *  Processors: ARM920 ARM922 ARM925 ARM926 XScale
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/tlbflush.h>
#include "proc-macros.S"

/*
 *	v4wb_flush_user_tlb_range(start, end, mm)
 *
 *	Invalidate a range of TLB entries in the specified address space.
 *
 *	- start - range start address
 *	- end   - range end address
 *	- mm    - mm_struct describing address space
 */
	.align	5
ENTRY(v4wbi_flush_user_tlb_range)
	vma_vm_mm ip, r2
	act_mm	r3				@ get current->active_mm
	eors	r3, ip, r3			@ == mm ?
	retne	lr				@ no, we dont do anything
	mov	r3, #0
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
	vma_vm_flags r2, r2
	bic	r0, r0, #0x0ff
	bic	r0, r0, #0xf00
1:	tst	r2, #VM_EXEC
	mcrne	p15, 0, r0, c8, c5, 1		@ invalidate I TLB entry
	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
	add	r0, r0, #PAGE_SZ
	cmp	r0, r1
	blo	1b
	ret	lr

ENTRY(v4wbi_flush_kern_tlb_range)
	mov	r3, #0
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
	bic	r0, r0, #0x0ff
	bic	r0, r0, #0xf00
1:	mcr	p15, 0, r0, c8, c5, 1		@ invalidate I TLB entry
	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
	add	r0, r0, #PAGE_SZ
	cmp	r0, r1
	blo	1b
	ret	lr

	__INITDATA

	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
	define_tlb_functions v4wbi, v4wbi_tlb_flags
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/tlbv4wbi.S
	3	*
	4	* Copyright (C) 1997-2002 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* ARM architecture version 4 and version 5 TLB handling functions.
	11	* These assume a split I/D TLBs, with a write buffer.
	12	*
	13	* Processors: ARM920 ARM922 ARM925 ARM926 XScale
	14	*/
	15	#include <linux/linkage.h>
	16	#include <linux/init.h>
6ebbf2ce	17	#include <asm/assembler.h>
e6ae744d	18	#include <asm/asm-offsets.h>
1da177e4 LT	19	#include <asm/tlbflush.h>
	20	#include "proc-macros.S"
	21
	22	/*
	23	* v4wb_flush_user_tlb_range(start, end, mm)
	24	*
	25	* Invalidate a range of TLB entries in the specified address space.
	26	*
	27	* - start - range start address
	28	* - end - range end address
	29	* - mm - mm_struct describing address space
	30	*/
	31	.align 5
	32	ENTRY(v4wbi_flush_user_tlb_range)
	33	vma_vm_mm ip, r2
	34	act_mm r3 @ get current->active_mm
	35	eors r3, ip, r3 @ == mm ?
6ebbf2ce	36	retne lr @ no, we dont do anything
1da177e4 LT	37	mov r3, #0
	38	mcr p15, 0, r3, c7, c10, 4 @ drain WB
	39	vma_vm_flags r2, r2
	40	bic r0, r0, #0x0ff
	41	bic r0, r0, #0xf00
	42	1: tst r2, #VM_EXEC
	43	mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
	44	mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
	45	add r0, r0, #PAGE_SZ
	46	cmp r0, r1
	47	blo 1b
6ebbf2ce	48	ret lr
1da177e4 LT	49
	50	ENTRY(v4wbi_flush_kern_tlb_range)
	51	mov r3, #0
	52	mcr p15, 0, r3, c7, c10, 4 @ drain WB
	53	bic r0, r0, #0x0ff
	54	bic r0, r0, #0xf00
	55	1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
	56	mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
	57	add r0, r0, #PAGE_SZ
	58	cmp r0, r1
	59	blo 1b
6ebbf2ce	60	ret lr
1da177e4 LT	61
	62	__INITDATA
	63
ca560963 DM	64	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
ca560963 DM	65	define_tlb_functions v4wbi, v4wbi_tlb_flags