[deliverable/linux.git] / arch / arm / plat-mxc / ehci.c

/*
 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 */

#include <linux/platform_device.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/mxc_ehci.h>

#define USBCTRL_OTGBASE_OFFSET	0x600

#define MX31_OTG_SIC_SHIFT	29
#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
#define MX31_OTG_PM_BIT		(1 << 24)

#define MX31_H2_SIC_SHIFT	21
#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
#define MX31_H2_PM_BIT		(1 << 16)
#define MX31_H2_DT_BIT		(1 << 5)

#define MX31_H1_SIC_SHIFT	13
#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
#define MX31_H1_PM_BIT		(1 << 8)
#define MX31_H1_DT_BIT		(1 << 4)

#define MX35_OTG_SIC_SHIFT	29
#define MX35_OTG_SIC_MASK	(0x3 << MX35_OTG_SIC_SHIFT)
#define MX35_OTG_PM_BIT		(1 << 24)

#define MX35_H1_SIC_SHIFT	21
#define MX35_H1_SIC_MASK	(0x3 << MX35_H1_SIC_SHIFT)
#define MX35_H1_PM_BIT		(1 << 8)
#define MX35_H1_IPPUE_UP_BIT	(1 << 7)
#define MX35_H1_IPPUE_DOWN_BIT	(1 << 6)
#define MX35_H1_TLL_BIT		(1 << 5)
#define MX35_H1_USBTE_BIT	(1 << 4)

#define MXC_OTG_OFFSET		0
#define MXC_H1_OFFSET		0x200

/* USB_CTRL */
#define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)	/* OTG wakeup intr enable */
#define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)	/* OTG power mask */
#define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)	/* Host1 ULPI interrupt enable */
#define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)	/* HOST1 wakeup intr enable */
#define MXC_H1_UCTRL_H1PM_BIT		(1 <<  8)		/* HOST1 power mask */

/* USB_PHY_CTRL_FUNC */
#define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)	/* OTG Disable Overcurrent Event */
#define MXC_H1_OC_DIS_BIT			(1 << 5)	/* UH1 Disable Overcurrent Event */

#define MXC_USBCMD_OFFSET			0x140

/* USBCMD */
#define MXC_UCMD_ITC_NO_THRESHOLD_MASK	(~(0xff << 16))	/* Interrupt Threshold Control */

int mxc_initialize_usb_hw(int port, unsigned int flags)
{
	unsigned int v;
#if defined(CONFIG_SOC_IMX25)
	if (cpu_is_mx25()) {
		v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
				     USBCTRL_OTGBASE_OFFSET));

		switch (port) {
		case 0:	/* OTG port */
			v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
			v |= (flags & MXC_EHCI_INTERFACE_MASK)
					<< MX35_OTG_SIC_SHIFT;
			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
				v |= MX35_OTG_PM_BIT;

			break;
		case 1: /* H1 port */
			v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
				MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
			v |= (flags & MXC_EHCI_INTERFACE_MASK)
						<< MX35_H1_SIC_SHIFT;
			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
				v |= MX35_H1_PM_BIT;

			if (!(flags & MXC_EHCI_TTL_ENABLED))
				v |= MX35_H1_TLL_BIT;

			if (flags & MXC_EHCI_INTERNAL_PHY)
				v |= MX35_H1_USBTE_BIT;

			if (flags & MXC_EHCI_IPPUE_DOWN)
				v |= MX35_H1_IPPUE_DOWN_BIT;

			if (flags & MXC_EHCI_IPPUE_UP)
				v |= MX35_H1_IPPUE_UP_BIT;

			break;
		default:
			return -EINVAL;
		}

		writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
				     USBCTRL_OTGBASE_OFFSET));
		return 0;
	}
#endif /* if defined(CONFIG_SOC_IMX25) */
#if defined(CONFIG_ARCH_MX3)
	if (cpu_is_mx31()) {
		v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
				     USBCTRL_OTGBASE_OFFSET));

		switch (port) {
		case 0:	/* OTG port */
			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
			v |= (flags & MXC_EHCI_INTERFACE_MASK)
					<< MX31_OTG_SIC_SHIFT;
			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
				v |= MX31_OTG_PM_BIT;

			break;
		case 1: /* H1 port */
			v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
			v |= (flags & MXC_EHCI_INTERFACE_MASK)
						<< MX31_H1_SIC_SHIFT;
			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
				v |= MX31_H1_PM_BIT;

			if (!(flags & MXC_EHCI_TTL_ENABLED))
				v |= MX31_H1_DT_BIT;

			break;
		case 2:	/* H2 port */
			v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
			v |= (flags & MXC_EHCI_INTERFACE_MASK)
						<< MX31_H2_SIC_SHIFT;
			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
				v |= MX31_H2_PM_BIT;

			if (!(flags & MXC_EHCI_TTL_ENABLED))
				v |= MX31_H2_DT_BIT;

			break;
		default:
			return -EINVAL;
		}

		writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
				     USBCTRL_OTGBASE_OFFSET));
		return 0;
	}

	if (cpu_is_mx35()) {
		v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
				     USBCTRL_OTGBASE_OFFSET));

		switch (port) {
		case 0:	/* OTG port */
			v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
			v |= (flags & MXC_EHCI_INTERFACE_MASK)
					<< MX35_OTG_SIC_SHIFT;
			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
				v |= MX35_OTG_PM_BIT;

			break;
		case 1: /* H1 port */
			v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
				MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
			v |= (flags & MXC_EHCI_INTERFACE_MASK)
						<< MX35_H1_SIC_SHIFT;
			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
				v |= MX35_H1_PM_BIT;

			if (!(flags & MXC_EHCI_TTL_ENABLED))
				v |= MX35_H1_TLL_BIT;

			if (flags & MXC_EHCI_INTERNAL_PHY)
				v |= MX35_H1_USBTE_BIT;

			if (flags & MXC_EHCI_IPPUE_DOWN)
				v |= MX35_H1_IPPUE_DOWN_BIT;

			if (flags & MXC_EHCI_IPPUE_UP)
				v |= MX35_H1_IPPUE_UP_BIT;

			break;
		default:
			return -EINVAL;
		}

		writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
				     USBCTRL_OTGBASE_OFFSET));
		return 0;
	}
#endif /* CONFIG_ARCH_MX3 */
#ifdef CONFIG_MACH_MX27
	if (cpu_is_mx27()) {
		/* On i.MX27 we can use the i.MX31 USBCTRL bits, they
		 * are identical
		 */
		v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
				     USBCTRL_OTGBASE_OFFSET));
		switch (port) {
		case 0:	/* OTG port */
			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
			v |= (flags & MXC_EHCI_INTERFACE_MASK)
					<< MX31_OTG_SIC_SHIFT;
			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
				v |= MX31_OTG_PM_BIT;
			break;
		case 1: /* H1 port */
			v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
			v |= (flags & MXC_EHCI_INTERFACE_MASK)
						<< MX31_H1_SIC_SHIFT;
			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
				v |= MX31_H1_PM_BIT;

			if (!(flags & MXC_EHCI_TTL_ENABLED))
				v |= MX31_H1_DT_BIT;

			break;
		case 2:	/* H2 port */
			v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
			v |= (flags & MXC_EHCI_INTERFACE_MASK)
						<< MX31_H2_SIC_SHIFT;
			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
				v |= MX31_H2_PM_BIT;

			if (!(flags & MXC_EHCI_TTL_ENABLED))
				v |= MX31_H2_DT_BIT;

			break;
		default:
			return -EINVAL;
		}
		writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
				     USBCTRL_OTGBASE_OFFSET));
		return 0;
	}
#endif /* CONFIG_MACH_MX27 */
#ifdef CONFIG_SOC_IMX51
	if (cpu_is_mx51()) {
		void __iomem *usb_base;
		void __iomem *usbotg_base;
		void __iomem *usbother_base;
		int ret = 0;

		usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
		if (!usb_base) {
			printk(KERN_ERR "%s(): ioremap failed\n", __func__);
			return -ENOMEM;
		}

		switch (port) {
		case 0:	/* OTG port */
			usbotg_base = usb_base + MXC_OTG_OFFSET;
			break;
		case 1:	/* Host 1 port */
			usbotg_base = usb_base + MXC_H1_OFFSET;
			break;
		default:
			printk(KERN_ERR"%s no such port %d\n", __func__, port);
			ret = -ENOENT;
			goto error;
		}
		usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

		switch (port) {
		case 0:	/*OTG port */
			if (flags & MXC_EHCI_INTERNAL_PHY) {
				v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

				if (flags & MXC_EHCI_POWER_PINS_ENABLED)
					v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */
				else
					v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */
				__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

				v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
				if (flags & MXC_EHCI_WAKEUP_ENABLED)
					v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
				else
					v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
				__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
			}
			break;
		case 1:	/* Host 1 */
			/*Host ULPI */
			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
			if (flags & MXC_EHCI_WAKEUP_ENABLED)
				v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
			else
				v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */

			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
				v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
			else
				v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);

			v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
				v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
			else
				v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
			__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

			v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
			if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
				/* Interrupt Threshold Control:Immediate (no threshold) */
				v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
			__raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
			break;
		}

error:
		iounmap(usb_base);
		return ret;
	}
#endif
	printk(KERN_WARNING
		"%s() unable to setup USBCONTROL for this CPU\n", __func__);
	return -EINVAL;
}
EXPORT_SYMBOL(mxc_initialize_usb_hw);
Commit	Line	Data
7e8d5cd9 DM	1	/*
7e8d5cd9 DM	2	* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
5a25ad84	3	* Copyright (C) 2010 Freescale Semiconductor, Inc.
7e8d5cd9 DM	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	12	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
7e8d5cd9 DM	14	*/
	15
	16	#include <linux/platform_device.h>
	17	#include <linux/io.h>
	18
	19	#include <mach/hardware.h>
	20	#include <mach/mxc_ehci.h>
	21
	22	#define USBCTRL_OTGBASE_OFFSET 0x600
	23
	24	#define MX31_OTG_SIC_SHIFT 29
84ab8061	25	#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
7e8d5cd9 DM	26	#define MX31_OTG_PM_BIT (1 << 24)
	27
	28	#define MX31_H2_SIC_SHIFT 21
84ab8061	29	#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
7e8d5cd9 DM	30	#define MX31_H2_PM_BIT (1 << 16)
	31	#define MX31_H2_DT_BIT (1 << 5)
	32
	33	#define MX31_H1_SIC_SHIFT 13
84ab8061	34	#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
7e8d5cd9 DM	35	#define MX31_H1_PM_BIT (1 << 8)
	36	#define MX31_H1_DT_BIT (1 << 4)
	37
d186f04c SH	38	#define MX35_OTG_SIC_SHIFT 29
	39	#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
	40	#define MX35_OTG_PM_BIT (1 << 24)
	41
	42	#define MX35_H1_SIC_SHIFT 21
	43	#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
	44	#define MX35_H1_PM_BIT (1 << 8)
	45	#define MX35_H1_IPPUE_UP_BIT (1 << 7)
	46	#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
	47	#define MX35_H1_TLL_BIT (1 << 5)
	48	#define MX35_H1_USBTE_BIT (1 << 4)
	49
5a25ad84 DN	50	#define MXC_OTG_OFFSET 0
	51	#define MXC_H1_OFFSET 0x200
	52
	53	/* USB_CTRL */
	54	#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
	55	#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
	56	#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
	57	#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
	58	#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
	59
	60	/* USB_PHY_CTRL_FUNC */
	61	#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
	62	#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
	63
	64	#define MXC_USBCMD_OFFSET 0x140
	65
	66	/* USBCMD */
	67	#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
	68
	69	int mxc_initialize_usb_hw(int port, unsigned int flags)
7e8d5cd9 DM	70	{
7e8d5cd9 DM	71	unsigned int v;
972cc482	72	#if defined(CONFIG_SOC_IMX25)
648beaf5	73	if (cpu_is_mx25()) {
2c20b9f1	74	v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
648beaf5 EB	75	USBCTRL_OTGBASE_OFFSET));
	76
	77	switch (port) {
	78	case 0: /* OTG port */
	79	v &= ~(MX35_OTG_SIC_MASK \| MX35_OTG_PM_BIT);
	80	v \|= (flags & MXC_EHCI_INTERFACE_MASK)
	81	<< MX35_OTG_SIC_SHIFT;
	82	if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
	83	v \|= MX35_OTG_PM_BIT;
	84
	85	break;
	86	case 1: /* H1 port */
	87	v &= ~(MX35_H1_SIC_MASK \| MX35_H1_PM_BIT \| MX35_H1_TLL_BIT \|
	88	MX35_H1_USBTE_BIT \| MX35_H1_IPPUE_DOWN_BIT \| MX35_H1_IPPUE_UP_BIT);
	89	v \|= (flags & MXC_EHCI_INTERFACE_MASK)
	90	<< MX35_H1_SIC_SHIFT;
	91	if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
	92	v \|= MX35_H1_PM_BIT;
	93
	94	if (!(flags & MXC_EHCI_TTL_ENABLED))
	95	v \|= MX35_H1_TLL_BIT;
	96
	97	if (flags & MXC_EHCI_INTERNAL_PHY)
	98	v \|= MX35_H1_USBTE_BIT;
	99
	100	if (flags & MXC_EHCI_IPPUE_DOWN)
	101	v \|= MX35_H1_IPPUE_DOWN_BIT;
	102
	103	if (flags & MXC_EHCI_IPPUE_UP)
	104	v \|= MX35_H1_IPPUE_UP_BIT;
	105
	106	break;
	107	default:
	108	return -EINVAL;
	109	}
	110
2c20b9f1	111	writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
648beaf5 EB	112	USBCTRL_OTGBASE_OFFSET));
	113	return 0;
	114	}
972cc482	115	#endif /* if defined(CONFIG_SOC_IMX25) */
648beaf5	116	#if defined(CONFIG_ARCH_MX3)
7e8d5cd9	117	if (cpu_is_mx31()) {
29bb6afc	118	v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
7e8d5cd9 DM	119	USBCTRL_OTGBASE_OFFSET));
	120
	121	switch (port) {
	122	case 0: /* OTG port */
	123	v &= ~(MX31_OTG_SIC_MASK \| MX31_OTG_PM_BIT);
	124	v \|= (flags & MXC_EHCI_INTERFACE_MASK)
	125	<< MX31_OTG_SIC_SHIFT;
84ab8061	126	if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
7e8d5cd9 DM	127	v \|= MX31_OTG_PM_BIT;
	128
	129	break;
	130	case 1: /* H1 port */
84ab8061	131	v &= ~(MX31_H1_SIC_MASK \| MX31_H1_PM_BIT \| MX31_H1_DT_BIT);
7e8d5cd9 DM	132	v \|= (flags & MXC_EHCI_INTERFACE_MASK)
7e8d5cd9 DM	133	<< MX31_H1_SIC_SHIFT;
84ab8061	134	if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
7e8d5cd9 DM	135	v \|= MX31_H1_PM_BIT;
	136
	137	if (!(flags & MXC_EHCI_TTL_ENABLED))
	138	v \|= MX31_H1_DT_BIT;
	139
	140	break;
	141	case 2: /* H2 port */
84ab8061	142	v &= ~(MX31_H2_SIC_MASK \| MX31_H2_PM_BIT \| MX31_H2_DT_BIT);
7e8d5cd9 DM	143	v \|= (flags & MXC_EHCI_INTERFACE_MASK)
	144	<< MX31_H2_SIC_SHIFT;
	145	if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
	146	v \|= MX31_H2_PM_BIT;
	147
	148	if (!(flags & MXC_EHCI_TTL_ENABLED))
	149	v \|= MX31_H2_DT_BIT;
	150
	151	break;
84ab8061 SH	152	default:
84ab8061 SH	153	return -EINVAL;
7e8d5cd9 DM	154	}
7e8d5cd9 DM	155
29bb6afc	156	writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
7e8d5cd9 DM	157	USBCTRL_OTGBASE_OFFSET));
	158	return 0;
	159	}
d186f04c SH	160
d186f04c SH	161	if (cpu_is_mx35()) {
29bb6afc	162	v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
d186f04c SH	163	USBCTRL_OTGBASE_OFFSET));
	164
	165	switch (port) {
	166	case 0: /* OTG port */
	167	v &= ~(MX35_OTG_SIC_MASK \| MX35_OTG_PM_BIT);
	168	v \|= (flags & MXC_EHCI_INTERFACE_MASK)
	169	<< MX35_OTG_SIC_SHIFT;
	170	if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
	171	v \|= MX35_OTG_PM_BIT;
	172
	173	break;
	174	case 1: /* H1 port */
	175	v &= ~(MX35_H1_SIC_MASK \| MX35_H1_PM_BIT \| MX35_H1_TLL_BIT \|
	176	MX35_H1_USBTE_BIT \| MX35_H1_IPPUE_DOWN_BIT \| MX35_H1_IPPUE_UP_BIT);
	177	v \|= (flags & MXC_EHCI_INTERFACE_MASK)
	178	<< MX35_H1_SIC_SHIFT;
	179	if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
	180	v \|= MX35_H1_PM_BIT;
	181
	182	if (!(flags & MXC_EHCI_TTL_ENABLED))
	183	v \|= MX35_H1_TLL_BIT;
	184
	185	if (flags & MXC_EHCI_INTERNAL_PHY)
	186	v \|= MX35_H1_USBTE_BIT;
	187
	188	if (flags & MXC_EHCI_IPPUE_DOWN)
	189	v \|= MX35_H1_IPPUE_DOWN_BIT;
	190
	191	if (flags & MXC_EHCI_IPPUE_UP)
	192	v \|= MX35_H1_IPPUE_UP_BIT;
	193
	194	break;
	195	default:
	196	return -EINVAL;
	197	}
	198
29bb6afc	199	writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
d186f04c SH	200	USBCTRL_OTGBASE_OFFSET));
	201	return 0;
	202	}
9cf945cb SH	203	#endif /* CONFIG_ARCH_MX3 */
	204	#ifdef CONFIG_MACH_MX27
	205	if (cpu_is_mx27()) {
	206	/* On i.MX27 we can use the i.MX31 USBCTRL bits, they
	207	* are identical
	208	*/
29bb6afc	209	v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
9cf945cb SH	210	USBCTRL_OTGBASE_OFFSET));
	211	switch (port) {
	212	case 0: /* OTG port */
	213	v &= ~(MX31_OTG_SIC_MASK \| MX31_OTG_PM_BIT);
	214	v \|= (flags & MXC_EHCI_INTERFACE_MASK)
	215	<< MX31_OTG_SIC_SHIFT;
	216	if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
	217	v \|= MX31_OTG_PM_BIT;
	218	break;
	219	case 1: /* H1 port */
	220	v &= ~(MX31_H1_SIC_MASK \| MX31_H1_PM_BIT \| MX31_H1_DT_BIT);
	221	v \|= (flags & MXC_EHCI_INTERFACE_MASK)
	222	<< MX31_H1_SIC_SHIFT;
	223	if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
	224	v \|= MX31_H1_PM_BIT;
	225
	226	if (!(flags & MXC_EHCI_TTL_ENABLED))
	227	v \|= MX31_H1_DT_BIT;
7e8d5cd9	228
9cf945cb SH	229	break;
	230	case 2: /* H2 port */
	231	v &= ~(MX31_H2_SIC_MASK \| MX31_H2_PM_BIT \| MX31_H2_DT_BIT);
	232	v \|= (flags & MXC_EHCI_INTERFACE_MASK)
	233	<< MX31_H2_SIC_SHIFT;
	234	if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
	235	v \|= MX31_H2_PM_BIT;
	236
	237	if (!(flags & MXC_EHCI_TTL_ENABLED))
	238	v \|= MX31_H2_DT_BIT;
	239
	240	break;
	241	default:
	242	return -EINVAL;
	243	}
29bb6afc	244	writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
9cf945cb SH	245	USBCTRL_OTGBASE_OFFSET));
	246	return 0;
	247	}
	248	#endif /* CONFIG_MACH_MX27 */
d94ed128	249	#ifdef CONFIG_SOC_IMX51
5a25ad84 DN	250	if (cpu_is_mx51()) {
5a25ad84 DN	251	void __iomem *usb_base;
a0606562 UKK	252	void __iomem *usbotg_base;
a0606562 UKK	253	void __iomem *usbother_base;
5a25ad84 DN	254	int ret = 0;
	255
	256	usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
28a4f908 FE	257	if (!usb_base) {
	258	printk(KERN_ERR "%s(): ioremap failed\n", __func__);
	259	return -ENOMEM;
	260	}
5a25ad84 DN	261
	262	switch (port) {
	263	case 0: /* OTG port */
	264	usbotg_base = usb_base + MXC_OTG_OFFSET;
	265	break;
	266	case 1: /* Host 1 port */
	267	usbotg_base = usb_base + MXC_H1_OFFSET;
	268	break;
	269	default:
	270	printk(KERN_ERR"%s no such port %d\n", __func__, port);
	271	ret = -ENOENT;
	272	goto error;
	273	}
	274	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	275
	276	switch (port) {
	277	case 0: /OTG port /
	278	if (flags & MXC_EHCI_INTERNAL_PHY) {
	279	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
	280
	281	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	282	v \|= (MXC_OTG_PHYCTRL_OC_DIS_BIT \| MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */
	283	else
	284	v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT \| MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */
	285	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
	286
	287	v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
	288	if (flags & MXC_EHCI_WAKEUP_ENABLED)
	289	v \|= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
	290	else
	291	v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
	292	__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
	293	}
	294	break;
	295	case 1: /* Host 1 */
	296	/Host ULPI /
	297	v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
	298	if (flags & MXC_EHCI_WAKEUP_ENABLED)
	299	v &= ~(MXC_H1_UCTRL_H1WIE_BIT \| MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
	300	else
	301	v &= ~(MXC_H1_UCTRL_H1WIE_BIT \| MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
	302
	303	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	304	v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
	305	else
	306	v \|= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
	307	__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
	308
	309	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
	310	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	311	v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
	312	else
	313	v \|= MXC_H1_OC_DIS_BIT; /* OC is not used */
	314	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
	315
	316	v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
	317	if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
	318	/* Interrupt Threshold Control:Immediate (no threshold) */
	319	v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
	320	__raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
	321	break;
	322	}
	323
	324	error:
325	iounmap(usb_base);
326	return ret;
327	}
328	#endif
7e8d5cd9 DM	329	printk(KERN_WARNING
	330	"%s() unable to setup USBCONTROL for this CPU\n", __func__);
	331	return -EINVAL;
	332	}
5a25ad84	333	EXPORT_SYMBOL(mxc_initialize_usb_hw);
7e8d5cd9	334