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07bd1a6c JB |
1 | /* |
2 | * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> | |
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
4 | * | |
5 | * Based on code from Freescale, | |
6 | * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version 2 | |
11 | * of the License, or (at your option) any later version. | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
20 | */ | |
21 | ||
22 | #include <linux/init.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/gpio.h> | |
a09e64fb | 26 | #include <mach/hardware.h> |
07bd1a6c JB |
27 | #include <asm-generic/bug.h> |
28 | ||
29 | static struct mxc_gpio_port *mxc_gpio_ports; | |
30 | static int gpio_table_size; | |
31 | ||
494f22dd SH |
32 | #define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2()) |
33 | ||
34 | #define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00) | |
35 | #define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04) | |
36 | #define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08) | |
37 | #define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C) | |
38 | #define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10) | |
39 | #define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14) | |
40 | #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) | |
41 | #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) | |
42 | ||
43 | #define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0) | |
44 | #define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1) | |
45 | #define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2) | |
46 | #define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3) | |
47 | #define GPIO_INT_NONE 0x4 | |
48 | ||
07bd1a6c JB |
49 | /* Note: This driver assumes 32 GPIOs are handled in one register */ |
50 | ||
51 | static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index) | |
52 | { | |
53 | __raw_writel(1 << index, port->base + GPIO_ISR); | |
54 | } | |
55 | ||
56 | static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index, | |
57 | int enable) | |
58 | { | |
59 | u32 l; | |
60 | ||
61 | l = __raw_readl(port->base + GPIO_IMR); | |
62 | l = (l & (~(1 << index))) | (!!enable << index); | |
63 | __raw_writel(l, port->base + GPIO_IMR); | |
64 | } | |
65 | ||
66 | static void gpio_ack_irq(u32 irq) | |
67 | { | |
68 | u32 gpio = irq_to_gpio(irq); | |
69 | _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f); | |
70 | } | |
71 | ||
72 | static void gpio_mask_irq(u32 irq) | |
73 | { | |
74 | u32 gpio = irq_to_gpio(irq); | |
75 | _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0); | |
76 | } | |
77 | ||
78 | static void gpio_unmask_irq(u32 irq) | |
79 | { | |
80 | u32 gpio = irq_to_gpio(irq); | |
81 | _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1); | |
82 | } | |
83 | ||
910862ec GL |
84 | static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset); |
85 | ||
07bd1a6c JB |
86 | static int gpio_set_irq_type(u32 irq, u32 type) |
87 | { | |
88 | u32 gpio = irq_to_gpio(irq); | |
89 | struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32]; | |
90 | u32 bit, val; | |
91 | int edge; | |
92 | void __iomem *reg = port->base; | |
93 | ||
910862ec | 94 | port->both_edges &= ~(1 << (gpio & 31)); |
07bd1a6c | 95 | switch (type) { |
6cab4860 | 96 | case IRQ_TYPE_EDGE_RISING: |
07bd1a6c JB |
97 | edge = GPIO_INT_RISE_EDGE; |
98 | break; | |
6cab4860 | 99 | case IRQ_TYPE_EDGE_FALLING: |
07bd1a6c JB |
100 | edge = GPIO_INT_FALL_EDGE; |
101 | break; | |
910862ec GL |
102 | case IRQ_TYPE_EDGE_BOTH: |
103 | val = mxc_gpio_get(&port->chip, gpio & 31); | |
104 | if (val) { | |
105 | edge = GPIO_INT_LOW_LEV; | |
106 | pr_debug("mxc: set GPIO %d to low trigger\n", gpio); | |
107 | } else { | |
108 | edge = GPIO_INT_HIGH_LEV; | |
109 | pr_debug("mxc: set GPIO %d to high trigger\n", gpio); | |
110 | } | |
111 | port->both_edges |= 1 << (gpio & 31); | |
112 | break; | |
6cab4860 | 113 | case IRQ_TYPE_LEVEL_LOW: |
07bd1a6c JB |
114 | edge = GPIO_INT_LOW_LEV; |
115 | break; | |
6cab4860 | 116 | case IRQ_TYPE_LEVEL_HIGH: |
07bd1a6c JB |
117 | edge = GPIO_INT_HIGH_LEV; |
118 | break; | |
910862ec | 119 | default: |
07bd1a6c JB |
120 | return -EINVAL; |
121 | } | |
122 | ||
123 | reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ | |
124 | bit = gpio & 0xf; | |
125 | val = __raw_readl(reg) & ~(0x3 << (bit << 1)); | |
126 | __raw_writel(val | (edge << (bit << 1)), reg); | |
127 | _clear_gpio_irqstatus(port, gpio & 0x1f); | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
910862ec GL |
132 | static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) |
133 | { | |
134 | void __iomem *reg = port->base; | |
135 | u32 bit, val; | |
136 | int edge; | |
137 | ||
138 | reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ | |
139 | bit = gpio & 0xf; | |
140 | val = __raw_readl(reg); | |
141 | edge = (val >> (bit << 1)) & 3; | |
142 | val &= ~(0x3 << (bit << 1)); | |
3d40f7fe | 143 | if (edge == GPIO_INT_HIGH_LEV) { |
910862ec GL |
144 | edge = GPIO_INT_LOW_LEV; |
145 | pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); | |
3d40f7fe | 146 | } else if (edge == GPIO_INT_LOW_LEV) { |
910862ec GL |
147 | edge = GPIO_INT_HIGH_LEV; |
148 | pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); | |
3d40f7fe | 149 | } else { |
910862ec GL |
150 | pr_err("mxc: invalid configuration for GPIO %d: %x\n", |
151 | gpio, edge); | |
152 | return; | |
153 | } | |
154 | __raw_writel(val | (edge << (bit << 1)), reg); | |
155 | } | |
156 | ||
3621f188 | 157 | /* handle 32 interrupts in one status register */ |
07bd1a6c JB |
158 | static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) |
159 | { | |
3621f188 | 160 | u32 gpio_irq_no_base = port->virtual_irq_start; |
07bd1a6c | 161 | |
3621f188 UKK |
162 | while (irq_stat != 0) { |
163 | int irqoffset = fls(irq_stat) - 1; | |
07bd1a6c | 164 | |
3621f188 UKK |
165 | if (port->both_edges & (1 << irqoffset)) |
166 | mxc_flip_edge(port, irqoffset); | |
910862ec | 167 | |
3621f188 | 168 | generic_handle_irq(gpio_irq_no_base + irqoffset); |
910862ec | 169 | |
3621f188 | 170 | irq_stat &= ~(1 << irqoffset); |
07bd1a6c JB |
171 | } |
172 | } | |
173 | ||
cfca8b53 | 174 | /* MX1 and MX3 has one interrupt *per* gpio port */ |
07bd1a6c JB |
175 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) |
176 | { | |
177 | u32 irq_stat; | |
178 | struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); | |
179 | ||
180 | irq_stat = __raw_readl(port->base + GPIO_ISR) & | |
181 | __raw_readl(port->base + GPIO_IMR); | |
e2c97e7f | 182 | |
07bd1a6c JB |
183 | mxc_gpio_irq_handler(port, irq_stat); |
184 | } | |
07bd1a6c | 185 | |
07bd1a6c JB |
186 | /* MX2 has one interrupt *for all* gpio ports */ |
187 | static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) | |
188 | { | |
189 | int i; | |
190 | u32 irq_msk, irq_stat; | |
191 | struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); | |
192 | ||
193 | /* walk through all interrupt status registers */ | |
194 | for (i = 0; i < gpio_table_size; i++) { | |
195 | irq_msk = __raw_readl(port[i].base + GPIO_IMR); | |
196 | if (!irq_msk) | |
197 | continue; | |
198 | ||
199 | irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk; | |
200 | if (irq_stat) | |
201 | mxc_gpio_irq_handler(&port[i], irq_stat); | |
202 | } | |
203 | } | |
07bd1a6c JB |
204 | |
205 | static struct irq_chip gpio_irq_chip = { | |
206 | .ack = gpio_ack_irq, | |
207 | .mask = gpio_mask_irq, | |
208 | .unmask = gpio_unmask_irq, | |
209 | .set_type = gpio_set_irq_type, | |
210 | }; | |
211 | ||
212 | static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, | |
213 | int dir) | |
214 | { | |
215 | struct mxc_gpio_port *port = | |
216 | container_of(chip, struct mxc_gpio_port, chip); | |
217 | u32 l; | |
218 | ||
219 | l = __raw_readl(port->base + GPIO_GDIR); | |
220 | if (dir) | |
221 | l |= 1 << offset; | |
222 | else | |
223 | l &= ~(1 << offset); | |
224 | __raw_writel(l, port->base + GPIO_GDIR); | |
225 | } | |
226 | ||
227 | static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
228 | { | |
229 | struct mxc_gpio_port *port = | |
230 | container_of(chip, struct mxc_gpio_port, chip); | |
231 | void __iomem *reg = port->base + GPIO_DR; | |
232 | u32 l; | |
233 | ||
234 | l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset); | |
235 | __raw_writel(l, reg); | |
236 | } | |
237 | ||
238 | static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset) | |
239 | { | |
240 | struct mxc_gpio_port *port = | |
241 | container_of(chip, struct mxc_gpio_port, chip); | |
242 | ||
5cac9d65 | 243 | return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1; |
07bd1a6c JB |
244 | } |
245 | ||
246 | static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
247 | { | |
248 | _set_gpio_direction(chip, offset, 0); | |
249 | return 0; | |
250 | } | |
251 | ||
252 | static int mxc_gpio_direction_output(struct gpio_chip *chip, | |
253 | unsigned offset, int value) | |
254 | { | |
07bd1a6c | 255 | mxc_gpio_set(chip, offset, value); |
999981d9 | 256 | _set_gpio_direction(chip, offset, 1); |
07bd1a6c JB |
257 | return 0; |
258 | } | |
259 | ||
260 | int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) | |
261 | { | |
262 | int i, j; | |
263 | ||
264 | /* save for local usage */ | |
265 | mxc_gpio_ports = port; | |
266 | gpio_table_size = cnt; | |
267 | ||
268 | printk(KERN_INFO "MXC GPIO hardware\n"); | |
269 | ||
270 | for (i = 0; i < cnt; i++) { | |
271 | /* disable the interrupt and clear the status */ | |
272 | __raw_writel(0, port[i].base + GPIO_IMR); | |
273 | __raw_writel(~0, port[i].base + GPIO_ISR); | |
274 | for (j = port[i].virtual_irq_start; | |
275 | j < port[i].virtual_irq_start + 32; j++) { | |
276 | set_irq_chip(j, &gpio_irq_chip); | |
060d20d3 | 277 | set_irq_handler(j, handle_level_irq); |
07bd1a6c JB |
278 | set_irq_flags(j, IRQF_VALID); |
279 | } | |
280 | ||
281 | /* register gpio chip */ | |
282 | port[i].chip.direction_input = mxc_gpio_direction_input; | |
283 | port[i].chip.direction_output = mxc_gpio_direction_output; | |
284 | port[i].chip.get = mxc_gpio_get; | |
285 | port[i].chip.set = mxc_gpio_set; | |
286 | port[i].chip.base = i * 32; | |
287 | port[i].chip.ngpio = 32; | |
288 | ||
289 | /* its a serious configuration bug when it fails */ | |
290 | BUG_ON( gpiochip_add(&port[i].chip) < 0 ); | |
291 | ||
8c25c36f | 292 | if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) { |
8afaada2 SH |
293 | /* setup one handler for each entry */ |
294 | set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); | |
295 | set_irq_data(port[i].irq, &port[i]); | |
296 | } | |
297 | } | |
298 | ||
299 | if (cpu_is_mx2()) { | |
300 | /* setup one handler for all GPIO interrupts */ | |
301 | set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler); | |
302 | set_irq_data(port[0].irq, port); | |
07bd1a6c JB |
303 | } |
304 | ||
07bd1a6c JB |
305 | return 0; |
306 | } |