projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 58a85f46 SH |
1 | /* |
| 2 | * linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h | |
| 3 | * | |
| 4 | * i.MX DMA registration and IRQ dispatching | |
| 5 | * | |
| 6 | * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz> | |
| 7 | * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de> | |
| 8 | * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de> | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License | |
| 12 | * as published by the Free Software Foundation; either version 2 | |
| 13 | * of the License, or (at your option) any later version. | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
| 22 | * MA 02110-1301, USA. | |
| 23 | */ | |
| 24 | ||
| 58a85f46 SH |
25 | #ifndef __ASM_ARCH_MXC_DMA_H |
| 26 | #define __ASM_ARCH_MXC_DMA_H | |
| 27 | ||
| 28 | #define IMX_DMA_CHANNELS 16 | |
| 29 | ||
| 33ebc19d SH |
30 | #define DMA_MODE_READ 0 |
| 31 | #define DMA_MODE_WRITE 1 | |
| 32 | #define DMA_MODE_MASK 1 | |
| 33 | ||
| 58a85f46 SH |
34 | #define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR) |
| 35 | ||
| 36 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
| 37 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
| 38 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
| 39 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
| 40 | #define IMX_DMA_TYPE_2D (1 << 10) | |
| 41 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
| 42 | ||
| 43 | #define IMX_DMA_ERR_BURST (1 << 0) | |
| 44 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
| 45 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
| 46 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
| 47 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
| 48 | ||
| 49 | int | |
| 50 | imx_dma_config_channel(int channel, unsigned int config_port, | |
| 51 | unsigned int config_mem, unsigned int dmareq, int hw_chaining); | |
| 52 | ||
| 53 | void | |
| 54 | imx_dma_config_burstlen(int channel, unsigned int burstlen); | |
| 55 | ||
| 56 | int | |
| 57 | imx_dma_setup_single(int channel, dma_addr_t dma_address, | |
| 58 | unsigned int dma_length, unsigned int dev_addr, | |
| 33ebc19d | 59 | unsigned int dmamode); |
| 58a85f46 | 60 | |
| 4998f1a3 SH |
61 | |
| 62 | /* | |
| 63 | * Use this flag as the dma_length argument to imx_dma_setup_sg() | |
| 64 | * to create an endless running dma loop. The end of the scatterlist | |
| 65 | * must be linked to the beginning for this to work. | |
| 66 | */ | |
| 67 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) | |
| 68 | ||
| 58a85f46 SH |
69 | int |
| 70 | imx_dma_setup_sg(int channel, struct scatterlist *sg, | |
| 71 | unsigned int sgcount, unsigned int dma_length, | |
| 33ebc19d | 72 | unsigned int dev_addr, unsigned int dmamode); |
| 58a85f46 SH |
73 | |
| 74 | int | |
| 75 | imx_dma_setup_handlers(int channel, | |
| 76 | void (*irq_handler) (int, void *), | |
| 77 | void (*err_handler) (int, void *, int), void *data); | |
| 78 | ||
| 79 | int | |
| 80 | imx_dma_setup_progression_handler(int channel, | |
| 81 | void (*prog_handler) (int, void*, struct scatterlist*)); | |
| 82 | ||
| 83 | void imx_dma_enable(int channel); | |
| 84 | ||
| 85 | void imx_dma_disable(int channel); | |
| 86 | ||
| 87 | int imx_dma_request(int channel, const char *name); | |
| 88 | ||
| 89 | void imx_dma_free(int channel); | |
| 90 | ||
| 91 | enum imx_dma_prio { | |
| 92 | DMA_PRIO_HIGH = 0, | |
| 93 | DMA_PRIO_MEDIUM = 1, | |
| 94 | DMA_PRIO_LOW = 2 | |
| 95 | }; | |
| 96 | ||
| 97 | int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio); | |
| 98 | ||
| 99 | #endif /* _ASM_ARCH_MXC_DMA_H */ |