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cfca8b53 PZ |
1 | /* |
2 | * Copyright (C) 1997,1998 Russell King | |
3 | * Copyright (C) 1999 ARM Limited | |
4 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef __ASM_ARCH_MXC_MX1_H__ | |
13 | #define __ASM_ARCH_MXC_MX1_H__ | |
14 | ||
cfca8b53 PZ |
15 | #include <mach/vmalloc.h> |
16 | ||
cfca8b53 PZ |
17 | /* |
18 | * Memory map | |
19 | */ | |
20 | #define IMX_IO_PHYS 0x00200000 | |
21 | #define IMX_IO_SIZE 0x00100000 | |
22 | #define IMX_IO_BASE VMALLOC_END | |
23 | ||
24 | #define IMX_CS0_PHYS 0x10000000 | |
25 | #define IMX_CS0_SIZE 0x02000000 | |
26 | ||
27 | #define IMX_CS1_PHYS 0x12000000 | |
28 | #define IMX_CS1_SIZE 0x01000000 | |
29 | ||
30 | #define IMX_CS2_PHYS 0x13000000 | |
31 | #define IMX_CS2_SIZE 0x01000000 | |
32 | ||
33 | #define IMX_CS3_PHYS 0x14000000 | |
34 | #define IMX_CS3_SIZE 0x01000000 | |
35 | ||
36 | #define IMX_CS4_PHYS 0x15000000 | |
37 | #define IMX_CS4_SIZE 0x01000000 | |
38 | ||
39 | #define IMX_CS5_PHYS 0x16000000 | |
40 | #define IMX_CS5_SIZE 0x01000000 | |
41 | ||
42 | /* | |
43 | * Register BASEs, based on OFFSETs | |
44 | */ | |
45 | #define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) | |
46 | #define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) | |
47 | #define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) | |
48 | #define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) | |
49 | #define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) | |
50 | #define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) | |
51 | #define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) | |
52 | #define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) | |
53 | #define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) | |
54 | #define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) | |
55 | #define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) | |
56 | #define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) | |
57 | #define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) | |
58 | #define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) | |
59 | #define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) | |
60 | #define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) | |
61 | #define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) | |
62 | #define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) | |
63 | #define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) | |
64 | #define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) | |
65 | #define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) | |
66 | #define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) | |
67 | #define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) | |
68 | #define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) | |
69 | #define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) | |
70 | #define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) | |
71 | #define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) | |
72 | #define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) | |
73 | #define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) | |
74 | ||
75 | /* macro to get at IO space when running virtually */ | |
76 | #define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) | |
77 | ||
78 | /* define macros needed for entry-macro.S */ | |
79 | #define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) | |
80 | ||
81 | /* fixed interrput numbers */ | |
82 | #define INT_SOFTINT 0 | |
83 | #define CSI_INT 6 | |
84 | #define DSPA_MAC_INT 7 | |
85 | #define DSPA_INT 8 | |
86 | #define COMP_INT 9 | |
87 | #define MSHC_XINT 10 | |
88 | #define GPIO_INT_PORTA 11 | |
89 | #define GPIO_INT_PORTB 12 | |
90 | #define GPIO_INT_PORTC 13 | |
91 | #define LCDC_INT 14 | |
92 | #define SIM_INT 15 | |
93 | #define SIM_DATA_INT 16 | |
94 | #define RTC_INT 17 | |
95 | #define RTC_SAMINT 18 | |
96 | #define UART2_MINT_PFERR 19 | |
97 | #define UART2_MINT_RTS 20 | |
98 | #define UART2_MINT_DTR 21 | |
99 | #define UART2_MINT_UARTC 22 | |
100 | #define UART2_MINT_TX 23 | |
101 | #define UART2_MINT_RX 24 | |
102 | #define UART1_MINT_PFERR 25 | |
103 | #define UART1_MINT_RTS 26 | |
104 | #define UART1_MINT_DTR 27 | |
105 | #define UART1_MINT_UARTC 28 | |
106 | #define UART1_MINT_TX 29 | |
107 | #define UART1_MINT_RX 30 | |
108 | #define VOICE_DAC_INT 31 | |
109 | #define VOICE_ADC_INT 32 | |
110 | #define PEN_DATA_INT 33 | |
111 | #define PWM_INT 34 | |
112 | #define SDHC_INT 35 | |
113 | #define I2C_INT 39 | |
114 | #define CSPI_INT 41 | |
115 | #define SSI_TX_INT 42 | |
116 | #define SSI_TX_ERR_INT 43 | |
117 | #define SSI_RX_INT 44 | |
118 | #define SSI_RX_ERR_INT 45 | |
119 | #define TOUCH_INT 46 | |
120 | #define USBD_INT0 47 | |
121 | #define USBD_INT1 48 | |
122 | #define USBD_INT2 49 | |
123 | #define USBD_INT3 50 | |
124 | #define USBD_INT4 51 | |
125 | #define USBD_INT5 52 | |
126 | #define USBD_INT6 53 | |
127 | #define BTSYS_INT 55 | |
128 | #define BTTIM_INT 56 | |
129 | #define BTWUI_INT 57 | |
130 | #define TIM2_INT 58 | |
131 | #define TIM1_INT 59 | |
132 | #define DMA_ERR 60 | |
133 | #define DMA_INT 61 | |
134 | #define GPIO_INT_PORTD 62 | |
135 | #define WDT_INT 63 | |
136 | ||
cfca8b53 PZ |
137 | /* DMA */ |
138 | #define DMA_REQ_UART3_T 2 | |
139 | #define DMA_REQ_UART3_R 3 | |
140 | #define DMA_REQ_SSI2_T 4 | |
141 | #define DMA_REQ_SSI2_R 5 | |
142 | #define DMA_REQ_CSI_STAT 6 | |
143 | #define DMA_REQ_CSI_R 7 | |
144 | #define DMA_REQ_MSHC 8 | |
145 | #define DMA_REQ_DSPA_DCT_DOUT 9 | |
146 | #define DMA_REQ_DSPA_DCT_DIN 10 | |
147 | #define DMA_REQ_DSPA_MAC 11 | |
148 | #define DMA_REQ_EXT 12 | |
149 | #define DMA_REQ_SDHC 13 | |
150 | #define DMA_REQ_SPI1_R 14 | |
151 | #define DMA_REQ_SPI1_T 15 | |
152 | #define DMA_REQ_SSI_T 16 | |
153 | #define DMA_REQ_SSI_R 17 | |
154 | #define DMA_REQ_ASP_DAC 18 | |
155 | #define DMA_REQ_ASP_ADC 19 | |
156 | #define DMA_REQ_USP_EP(x) (20 + (x)) | |
157 | #define DMA_REQ_SPI2_R 26 | |
158 | #define DMA_REQ_SPI2_T 27 | |
159 | #define DMA_REQ_UART2_T 28 | |
160 | #define DMA_REQ_UART2_R 29 | |
161 | #define DMA_REQ_UART1_T 30 | |
162 | #define DMA_REQ_UART1_R 31 | |
163 | ||
cfca8b53 | 164 | #endif /* __ASM_ARCH_MXC_MX1_H__ */ |