projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 8c25c36f SH |
1 | #ifndef __MACH_MX25_H__ |
| 2 | #define __MACH_MX25_H__ | |
| 3 | ||
| c8e5db08 UKK |
4 | #define MX25_AIPS1_BASE_ADDR 0x43f00000 |
| 5 | #define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 | |
| 8c25c36f | 6 | #define MX25_AIPS1_SIZE SZ_1M |
| c8e5db08 UKK |
7 | #define MX25_AIPS2_BASE_ADDR 0x53f00000 |
| 8 | #define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000 | |
| 8c25c36f SH |
9 | #define MX25_AIPS2_SIZE SZ_1M |
| 10 | #define MX25_AVIC_BASE_ADDR 0x68000000 | |
| c8e5db08 | 11 | #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 |
| 8c25c36f SH |
12 | #define MX25_AVIC_SIZE SZ_1M |
| 13 | ||
| 14 | #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) | |
| 15 | ||
| 16 | #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) | |
| 17 | #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) | |
| 18 | #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) | |
| 19 | ||
| 20 | #define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) | |
| 21 | #define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) | |
| 22 | #define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) | |
| 23 | #define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) | |
| 24 | ||
| df9375fa UKK |
25 | #define MX25_IO_ADDRESS(x) ( \ |
| 26 | IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \ | |
| 27 | IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ | |
| 28 | IMX_IO_ADDRESS(x, MX25_AVIC)) | |
| 8c25c36f | 29 | |
| 66ac2f28 UKK |
30 | #define MX25_UART1_BASE_ADDR 0x43f90000 |
| 31 | #define MX25_UART2_BASE_ADDR 0x43f94000 | |
| 8402ed30 | 32 | #define MX25_AUDMUX_BASE_ADDR 0x43fb0000 |
| 8c25c36f | 33 | |
| a759544f | 34 | #define MX25_FEC_BASE_ADDR 0x50038000 |
| 8402ed30 EB |
35 | #define MX25_SSI2_BASE_ADDR 0x50014000 |
| 36 | #define MX25_SSI1_BASE_ADDR 0x50034000 | |
| 27f59025 | 37 | #define MX25_NFC_BASE_ADDR 0xbb000000 |
| dcbabbc1 | 38 | #define MX25_DRYICE_BASE_ADDR 0x53ffc000 |
| 04a03e5f | 39 | #define MX25_LCDC_BASE_ADDR 0x53fbc000 |
| 49535a95 | 40 | #define MX25_KPP_BASE_ADDR 0x43fa8000 |
| 5a36c399 | 41 | #define MX25_OTG_BASE_ADDR 0x53ff4000 |
| a759544f | 42 | |
| 8402ed30 EB |
43 | #define MX25_INT_SSI2 11 |
| 44 | #define MX25_INT_SSI1 12 | |
| dcbabbc1 | 45 | #define MX25_INT_DRYICE 25 |
| 27f59025 | 46 | #define MX25_INT_NANDFC 33 |
| 04a03e5f | 47 | #define MX25_INT_LCDC 39 |
| 49535a95 | 48 | #define MX25_INT_KPP 24 |
| 8402ed30 | 49 | #define MX25_INT_FEC 57 |
| a759544f | 50 | |
| 66ac2f28 UKK |
51 | #if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) |
| 52 | #define UART1_BASE_ADDR MX25_UART1_BASE_ADDR | |
| 53 | #define UART2_BASE_ADDR MX25_UART2_BASE_ADDR | |
| 54 | #endif | |
| 55 | ||
| 3cdd5441 | 56 | #endif /* ifndef __MACH_MX25_H__ */ |