Commit | Line | Data |
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8c25c36f SH |
1 | #ifndef __MACH_MX25_H__ |
2 | #define __MACH_MX25_H__ | |
3 | ||
c8e5db08 UKK |
4 | #define MX25_AIPS1_BASE_ADDR 0x43f00000 |
5 | #define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 | |
8c25c36f | 6 | #define MX25_AIPS1_SIZE SZ_1M |
c8e5db08 UKK |
7 | #define MX25_AIPS2_BASE_ADDR 0x53f00000 |
8 | #define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000 | |
8c25c36f SH |
9 | #define MX25_AIPS2_SIZE SZ_1M |
10 | #define MX25_AVIC_BASE_ADDR 0x68000000 | |
c8e5db08 | 11 | #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 |
8c25c36f SH |
12 | #define MX25_AVIC_SIZE SZ_1M |
13 | ||
14 | #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) | |
15 | ||
16 | #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) | |
17 | #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) | |
18 | #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) | |
19 | ||
20 | #define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) | |
21 | #define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) | |
22 | #define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) | |
23 | #define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) | |
24 | ||
df9375fa UKK |
25 | #define MX25_IO_ADDRESS(x) ( \ |
26 | IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \ | |
27 | IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ | |
28 | IMX_IO_ADDRESS(x, MX25_AVIC)) | |
8c25c36f SH |
29 | |
30 | #define UART1_BASE_ADDR 0x43f90000 | |
31 | #define UART2_BASE_ADDR 0x43f94000 | |
32 | ||
a759544f | 33 | #define MX25_FEC_BASE_ADDR 0x50038000 |
27f59025 | 34 | #define MX25_NFC_BASE_ADDR 0xbb000000 |
dcbabbc1 | 35 | #define MX25_DRYICE_BASE_ADDR 0x53ffc000 |
a759544f | 36 | |
dcbabbc1 | 37 | #define MX25_INT_DRYICE 25 |
a759544f | 38 | #define MX25_INT_FEC 57 |
27f59025 | 39 | #define MX25_INT_NANDFC 33 |
a759544f | 40 | |
3cdd5441 | 41 | #endif /* ifndef __MACH_MX25_H__ */ |