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260a1fd2 HS |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
4 | * | |
5 | * This contains hardware definitions that are common between i.MX21 and | |
6 | * i.MX27. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version 2 | |
11 | * of the License, or (at your option) any later version. | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
20 | * MA 02110-1301, USA. | |
21 | */ | |
22 | ||
3cdd5441 UKK |
23 | #ifndef __MACH_MX2x_H__ |
24 | #define __MACH_MX2x_H__ | |
260a1fd2 | 25 | |
260a1fd2 HS |
26 | /* The following addresses are common between i.MX21 and i.MX27 */ |
27 | ||
fb370466 | 28 | /* Register offsets */ |
b9fc90a4 | 29 | #define MX2x_AIPI_BASE_ADDR 0x10000000 |
b9fc90a4 UKK |
30 | #define MX2x_AIPI_SIZE SZ_1M |
31 | #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) | |
32 | #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) | |
33 | #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000) | |
34 | #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000) | |
35 | #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000) | |
36 | #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000) | |
37 | #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000) | |
38 | #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000) | |
39 | #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000) | |
40 | #define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000) | |
41 | #define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000) | |
42 | #define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000) | |
43 | #define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000) | |
44 | #define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000) | |
45 | #define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000) | |
46 | #define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000) | |
47 | #define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000) | |
48 | #define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000) | |
49 | #define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000) | |
50 | #define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000) | |
51 | #define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000) | |
52 | #define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000) | |
53 | #define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000) | |
54 | #define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000) | |
55 | #define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000) | |
56 | #define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000) | |
57 | #define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000) | |
58 | #define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400) | |
59 | #define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000) | |
60 | #define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800) | |
61 | #define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000) | |
62 | #define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000) | |
63 | ||
64 | #define MX2x_AVIC_BASE_ADDR 0x10040000 | |
65 | ||
66 | #define MX2x_SAHB1_BASE_ADDR 0x80000000 | |
b9fc90a4 UKK |
67 | #define MX2x_SAHB1_SIZE SZ_1M |
68 | #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) | |
260a1fd2 | 69 | |
260a1fd2 | 70 | /* fixed interrupt numbers */ |
8842a9e2 SG |
71 | #include <asm/irq.h> |
72 | #define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6) | |
73 | #define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8) | |
74 | #define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10) | |
75 | #define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11) | |
76 | #define MX2x_INT_I2C (NR_IRQS_LEGACY + 12) | |
77 | #define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13) | |
78 | #define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14) | |
79 | #define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15) | |
80 | #define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16) | |
81 | #define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17) | |
82 | #define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18) | |
83 | #define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19) | |
84 | #define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20) | |
85 | #define MX2x_INT_KPP (NR_IRQS_LEGACY + 21) | |
86 | #define MX2x_INT_RTC (NR_IRQS_LEGACY + 22) | |
87 | #define MX2x_INT_PWM (NR_IRQS_LEGACY + 23) | |
88 | #define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24) | |
89 | #define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25) | |
90 | #define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26) | |
91 | #define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27) | |
92 | #define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28) | |
93 | #define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29) | |
94 | #define MX2x_INT_CSI (NR_IRQS_LEGACY + 31) | |
95 | #define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32) | |
96 | #define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33) | |
97 | #define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34) | |
98 | #define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35) | |
99 | #define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36) | |
100 | #define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37) | |
101 | #define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38) | |
102 | #define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39) | |
103 | #define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40) | |
104 | #define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41) | |
105 | #define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42) | |
106 | #define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43) | |
107 | #define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44) | |
108 | #define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45) | |
109 | #define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46) | |
110 | #define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47) | |
111 | #define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51) | |
112 | #define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52) | |
113 | #define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60) | |
114 | #define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61) | |
260a1fd2 | 115 | |
260a1fd2 | 116 | /* fixed DMA request numbers */ |
b9fc90a4 UKK |
117 | #define MX2x_DMA_REQ_CSPI3_RX 1 |
118 | #define MX2x_DMA_REQ_CSPI3_TX 2 | |
119 | #define MX2x_DMA_REQ_EXT 3 | |
120 | #define MX2x_DMA_REQ_SDHC2 6 | |
121 | #define MX2x_DMA_REQ_SDHC1 7 | |
122 | #define MX2x_DMA_REQ_SSI2_RX0 8 | |
123 | #define MX2x_DMA_REQ_SSI2_TX0 9 | |
124 | #define MX2x_DMA_REQ_SSI2_RX1 10 | |
125 | #define MX2x_DMA_REQ_SSI2_TX1 11 | |
126 | #define MX2x_DMA_REQ_SSI1_RX0 12 | |
127 | #define MX2x_DMA_REQ_SSI1_TX0 13 | |
128 | #define MX2x_DMA_REQ_SSI1_RX1 14 | |
129 | #define MX2x_DMA_REQ_SSI1_TX1 15 | |
130 | #define MX2x_DMA_REQ_CSPI2_RX 16 | |
131 | #define MX2x_DMA_REQ_CSPI2_TX 17 | |
132 | #define MX2x_DMA_REQ_CSPI1_RX 18 | |
133 | #define MX2x_DMA_REQ_CSPI1_TX 19 | |
134 | #define MX2x_DMA_REQ_UART4_RX 20 | |
135 | #define MX2x_DMA_REQ_UART4_TX 21 | |
136 | #define MX2x_DMA_REQ_UART3_RX 22 | |
137 | #define MX2x_DMA_REQ_UART3_TX 23 | |
138 | #define MX2x_DMA_REQ_UART2_RX 24 | |
139 | #define MX2x_DMA_REQ_UART2_TX 25 | |
140 | #define MX2x_DMA_REQ_UART1_RX 26 | |
141 | #define MX2x_DMA_REQ_UART1_TX 27 | |
142 | #define MX2x_DMA_REQ_CSI_STAT 30 | |
143 | #define MX2x_DMA_REQ_CSI_RX 31 | |
144 | ||
3cdd5441 | 145 | #endif /* ifndef __MACH_MX2x_H__ */ |