[deliverable/linux.git] / arch / arm / plat-mxc / include / mach / mx31.h

#ifndef __MACH_MX31_H__
#define __MACH_MX31_H__

#ifndef __ASSEMBLER__
#include <linux/io.h>
#endif

/*
 * IRAM
 */
#define MX31_IRAM_BASE_ADDR		0x1ffc0000	/* internal ram */
#define MX31_IRAM_SIZE			SZ_16K

#define MX31_L2CC_BASE_ADDR		0x30000000
#define MX31_L2CC_SIZE			SZ_1M

#define MX31_AIPS1_BASE_ADDR		0x43f00000
#define MX31_AIPS1_SIZE			SZ_1M
#define MX31_MAX_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x04000)
#define MX31_EVTMON_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x08000)
#define MX31_CLKCTL_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x0c000)
#define MX31_ETB_SLOT4_BASE_ADDR		(MX31_AIPS1_BASE_ADDR + 0x10000)
#define MX31_ETB_SLOT5_BASE_ADDR		(MX31_AIPS1_BASE_ADDR + 0x14000)
#define MX31_ECT_CTIO_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x18000)
#define MX31_I2C1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x80000)
#define MX31_I2C3_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x84000)
#define MX31_OTG_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x88000)
#define MX31_ATA_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x8c000)
#define MX31_UART1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x90000)
#define MX31_UART2_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x94000)
#define MX31_I2C2_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x98000)
#define MX31_OWIRE_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x9c000)
#define MX31_SSI1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xa0000)
#define MX31_CSPI1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xa4000)
#define MX31_KPP_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xa8000)
#define MX31_IOMUXC_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xac000)
#define MX31_UART4_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xb0000)
#define MX31_UART5_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xb4000)
#define MX31_ECT_IP1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xb8000)
#define MX31_ECT_IP2_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xbc000)

#define MX31_SPBA0_BASE_ADDR		0x50000000
#define MX31_SPBA0_SIZE			SZ_1M
#define MX31_SDHC1_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x04000)
#define MX31_SDHC2_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x08000)
#define MX31_UART3_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x0c000)
#define MX31_CSPI2_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x10000)
#define MX31_SSI2_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x14000)
#define MX31_SIM1_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x18000)
#define MX31_IIM_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x1c000)
#define MX31_ATA_DMA_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x20000)
#define MX31_MSHC1_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x24000)
#define MX31_SPBA_CTRL_BASE_ADDR		(MX31_SPBA0_BASE_ADDR + 0x3c000)

#define MX31_AIPS2_BASE_ADDR		0x53f00000
#define MX31_AIPS2_SIZE			SZ_1M
#define MX31_CCM_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x80000)
#define MX31_CSPI3_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x84000)
#define MX31_FIRI_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x8c000)
#define MX31_GPT1_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x90000)
#define MX31_EPIT1_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x94000)
#define MX31_EPIT2_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x98000)
#define MX31_GPIO3_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xa4000)
#define MX31_SCC_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xac000)
#define MX31_SCM_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xae000)
#define MX31_SMN_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xaf000)
#define MX31_RNGA_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xb0000)
#define MX31_IPU_CTRL_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xc0000)
#define MX31_AUDMUX_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xc4000)
#define MX31_MPEG4_ENC_BASE_ADDR		(MX31_AIPS2_BASE_ADDR + 0xc8000)
#define MX31_GPIO1_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xcc000)
#define MX31_GPIO2_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xd0000)
#define MX31_SDMA_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xd4000)
#define MX31_RTC_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xd8000)
#define MX31_WDOG_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xdc000)
#define MX31_PWM_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xe0000)
#define MX31_RTIC_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xec000)

#define MX31_ROMP_BASE_ADDR		0x60000000
#define MX31_ROMP_BASE_ADDR_VIRT	0xfc500000
#define MX31_ROMP_SIZE			SZ_1M

#define MX31_AVIC_BASE_ADDR		0x68000000
#define MX31_AVIC_SIZE			SZ_1M

#define MX31_IPU_MEM_BASE_ADDR		0x70000000
#define MX31_CSD0_BASE_ADDR		0x80000000
#define MX31_CSD1_BASE_ADDR		0x90000000

#define MX31_CS0_BASE_ADDR		0xa0000000
#define MX31_CS1_BASE_ADDR		0xa8000000
#define MX31_CS2_BASE_ADDR		0xb0000000
#define MX31_CS3_BASE_ADDR		0xb2000000

#define MX31_CS4_BASE_ADDR		0xb4000000
#define MX31_CS4_BASE_ADDR_VIRT		0xf6000000
#define MX31_CS4_SIZE			SZ_32M

#define MX31_CS5_BASE_ADDR		0xb6000000
#define MX31_CS5_BASE_ADDR_VIRT		0xf8000000
#define MX31_CS5_SIZE			SZ_32M

#define MX31_X_MEMC_BASE_ADDR		0xb8000000
#define MX31_X_MEMC_SIZE		SZ_64K
#define MX31_NFC_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x0000)
#define MX31_ESDCTL_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x1000)
#define MX31_WEIM_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x2000)
#define MX31_M3IF_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x3000)
#define MX31_EMI_CTL_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x4000)
#define MX31_PCMCIA_CTL_BASE_ADDR		MX31_EMI_CTL_BASE_ADDR

#define MX31_WEIM_CSCRx_BASE_ADDR(cs)	(MX31_WEIM_BASE_ADDR + (cs) * 0x10)
#define MX31_WEIM_CSCRxU(cs)			(MX31_WEIM_CSCRx_BASE_ADDR(cs))
#define MX31_WEIM_CSCRxL(cs)			(MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
#define MX31_WEIM_CSCRxA(cs)			(MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)

#define MX31_PCMCIA_MEM_BASE_ADDR	0xbc000000

#define MX31_IO_P2V(x)			IMX_IO_P2V(x)
#define MX31_IO_ADDRESS(x)		IOMEM(MX31_IO_P2V(x))

#ifndef __ASSEMBLER__
static inline void mx31_setup_weimcs(size_t cs,
		unsigned upper, unsigned lower, unsigned addional)
{
	__raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs)));
	__raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs)));
	__raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs)));
}
#endif

#define MX31_INT_I2C3		3
#define MX31_INT_I2C2		4
#define MX31_INT_MPEG4_ENCODER	5
#define MX31_INT_RTIC		6
#define MX31_INT_FIRI		7
#define MX31_INT_SDHC2		8
#define MX31_INT_SDHC1		9
#define MX31_INT_I2C1		10
#define MX31_INT_SSI2		11
#define MX31_INT_SSI1		12
#define MX31_INT_CSPI2		13
#define MX31_INT_CSPI1		14
#define MX31_INT_ATA		15
#define MX31_INT_MBX		16
#define MX31_INT_CSPI3		17
#define MX31_INT_UART3		18
#define MX31_INT_IIM		19
#define MX31_INT_SIM2		20
#define MX31_INT_SIM1		21
#define MX31_INT_RNGA		22
#define MX31_INT_EVTMON		23
#define MX31_INT_KPP		24
#define MX31_INT_RTC		25
#define MX31_INT_PWM		26
#define MX31_INT_EPIT2		27
#define MX31_INT_EPIT1		28
#define MX31_INT_GPT		29
#define MX31_INT_POWER_FAIL	30
#define MX31_INT_CCM_DVFS	31
#define MX31_INT_UART2		32
#define MX31_INT_NFC		33
#define MX31_INT_SDMA		34
#define MX31_INT_USB1		35
#define MX31_INT_USB2		36
#define MX31_INT_USB3		37
#define MX31_INT_USB4		38
#define MX31_INT_MSHC1		39
#define MX31_INT_MSHC2		40
#define MX31_INT_IPU_ERR	41
#define MX31_INT_IPU_SYN	42
#define MX31_INT_UART1		45
#define MX31_INT_UART4		46
#define MX31_INT_UART5		47
#define MX31_INT_ECT		48
#define MX31_INT_SCC_SCM	49
#define MX31_INT_SCC_SMN	50
#define MX31_INT_GPIO2		51
#define MX31_INT_GPIO1		52
#define MX31_INT_CCM		53
#define MX31_INT_PCMCIA		54
#define MX31_INT_WDOG		55
#define MX31_INT_GPIO3		56
#define MX31_INT_EXT_POWER	58
#define MX31_INT_EXT_TEMPER	59
#define MX31_INT_EXT_SENSOR60	60
#define MX31_INT_EXT_SENSOR61	61
#define MX31_INT_EXT_WDOG	62
#define MX31_INT_EXT_TV		63

#define MX31_DMA_REQ_SDHC1	20
#define MX31_DMA_REQ_SDHC2	21
#define MX31_DMA_REQ_SSI2_RX1	22
#define MX31_DMA_REQ_SSI2_TX1	23
#define MX31_DMA_REQ_SSI2_RX0	24
#define MX31_DMA_REQ_SSI2_TX0	25
#define MX31_DMA_REQ_SSI1_RX1	26
#define MX31_DMA_REQ_SSI1_TX1	27
#define MX31_DMA_REQ_SSI1_RX0	28
#define MX31_DMA_REQ_SSI1_TX0	29

#define MX31_PROD_SIGNATURE		0x1	/* For MX31 */

/* silicon revisions specific to i.MX31 */
#define MX31_CHIP_REV_1_0		0x10
#define MX31_CHIP_REV_1_1		0x11
#define MX31_CHIP_REV_1_2		0x12
#define MX31_CHIP_REV_1_3		0x13
#define MX31_CHIP_REV_2_0		0x20
#define MX31_CHIP_REV_2_1		0x21
#define MX31_CHIP_REV_2_2		0x22
#define MX31_CHIP_REV_2_3		0x23
#define MX31_CHIP_REV_3_0		0x30
#define MX31_CHIP_REV_3_1		0x31
#define MX31_CHIP_REV_3_2		0x32

#define MX31_SYSTEM_REV_MIN		MX31_CHIP_REV_1_0
#define MX31_SYSTEM_REV_NUM		3

#endif /* ifndef __MACH_MX31_H__ */
Commit	Line	Data
3cdd5441 UKK	1	#ifndef __MACH_MX31_H__
	2	#define __MACH_MX31_H__
	3
a8dfb646 UKK	4	#ifndef __ASSEMBLER__
	5	#include <linux/io.h>
	6	#endif
	7
52c543f9 QJ	8	/*
	9	* IRAM
	10	*/
4f683a04	11	#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
c0a5f855	12	#define MX31_IRAM_SIZE SZ_16K
52c543f9	13
ebca1a55 UKK	14	#define MX31_L2CC_BASE_ADDR 0x30000000
ebca1a55 UKK	15	#define MX31_L2CC_SIZE SZ_1M
52c543f9	16
ebca1a55	17	#define MX31_AIPS1_BASE_ADDR 0x43f00000
ebca1a55 UKK	18	#define MX31_AIPS1_SIZE SZ_1M
	19	#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
	20	#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
	21	#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
	22	#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
	23	#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
	24	#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
4a9b8b0b	25	#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
ebca1a55 UKK	26	#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
	27	#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
	28	#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
	29	#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
	30	#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
	31	#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
	32	#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
	33	#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
	34	#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
	35	#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
	36	#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
	37	#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
	38	#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
	39	#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
	40	#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
52c543f9	41
ebca1a55	42	#define MX31_SPBA0_BASE_ADDR 0x50000000
ebca1a55	43	#define MX31_SPBA0_SIZE SZ_1M
6a697e3d UKK	44	#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
6a697e3d UKK	45	#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
ebca1a55 UKK	46	#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
	47	#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
	48	#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
	49	#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
	50	#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
	51	#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
	52	#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
	53	#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
52c543f9	54
ebca1a55	55	#define MX31_AIPS2_BASE_ADDR 0x53f00000
ebca1a55 UKK	56	#define MX31_AIPS2_SIZE SZ_1M
	57	#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
	58	#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
	59	#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
	60	#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
	61	#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
	62	#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
	63	#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
	64	#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
	65	#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
	66	#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
	67	#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
	68	#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
	69	#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
	70	#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
	71	#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
	72	#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
	73	#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
	74	#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
	75	#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
	76	#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
	77	#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
52c543f9	78
ebca1a55 UKK	79	#define MX31_ROMP_BASE_ADDR 0x60000000
	80	#define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000
	81	#define MX31_ROMP_SIZE SZ_1M
	82
	83	#define MX31_AVIC_BASE_ADDR 0x68000000
ebca1a55 UKK	84	#define MX31_AVIC_SIZE SZ_1M
	85
	86	#define MX31_IPU_MEM_BASE_ADDR 0x70000000
	87	#define MX31_CSD0_BASE_ADDR 0x80000000
	88	#define MX31_CSD1_BASE_ADDR 0x90000000
	89
	90	#define MX31_CS0_BASE_ADDR 0xa0000000
	91	#define MX31_CS1_BASE_ADDR 0xa8000000
	92	#define MX31_CS2_BASE_ADDR 0xb0000000
	93	#define MX31_CS3_BASE_ADDR 0xb2000000
	94
	95	#define MX31_CS4_BASE_ADDR 0xb4000000
a9963148	96	#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000
ebca1a55 UKK	97	#define MX31_CS4_SIZE SZ_32M
	98
	99	#define MX31_CS5_BASE_ADDR 0xb6000000
a9963148	100	#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000
ebca1a55 UKK	101	#define MX31_CS5_SIZE SZ_32M
	102
	103	#define MX31_X_MEMC_BASE_ADDR 0xb8000000
ebca1a55 UKK	104	#define MX31_X_MEMC_SIZE SZ_64K
	105	#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
	106	#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
	107	#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
	108	#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
	109	#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
	110	#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
	111
a8dfb646 UKK	112	#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
	113	#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
	114	#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
	115	#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
	116
ebca1a55 UKK	117	#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
ebca1a55 UKK	118
a9963148	119	#define MX31_IO_P2V(x) IMX_IO_P2V(x)
f5d7a13b	120	#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
1273e768	121
a8dfb646 UKK	122	#ifndef __ASSEMBLER__
	123	static inline void mx31_setup_weimcs(size_t cs,
	124	unsigned upper, unsigned lower, unsigned addional)
	125	{
	126	__raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs)));
	127	__raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs)));
	128	__raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs)));
	129	}
	130	#endif
	131
ebca1a55 UKK	132	#define MX31_INT_I2C3 3
ebca1a55 UKK	133	#define MX31_INT_I2C2 4
4f683a04	134	#define MX31_INT_MPEG4_ENCODER 5
ebca1a55	135	#define MX31_INT_RTIC 6
4f683a04	136	#define MX31_INT_FIRI 7
6a697e3d UKK	137	#define MX31_INT_SDHC2 8
6a697e3d UKK	138	#define MX31_INT_SDHC1 9
4a9b8b0b	139	#define MX31_INT_I2C1 10
c0a5f855 SH	140	#define MX31_INT_SSI2 11
c0a5f855 SH	141	#define MX31_INT_SSI1 12
ebca1a55 UKK	142	#define MX31_INT_CSPI2 13
	143	#define MX31_INT_CSPI1 14
	144	#define MX31_INT_ATA 15
4f683a04 UKK	145	#define MX31_INT_MBX 16
4f683a04 UKK	146	#define MX31_INT_CSPI3 17
ebca1a55 UKK	147	#define MX31_INT_UART3 18
ebca1a55 UKK	148	#define MX31_INT_IIM 19
4f683a04 UKK	149	#define MX31_INT_SIM2 20
4f683a04 UKK	150	#define MX31_INT_SIM1 21
ebca1a55 UKK	151	#define MX31_INT_RNGA 22
	152	#define MX31_INT_EVTMON 23
	153	#define MX31_INT_KPP 24
	154	#define MX31_INT_RTC 25
	155	#define MX31_INT_PWM 26
	156	#define MX31_INT_EPIT2 27
	157	#define MX31_INT_EPIT1 28
	158	#define MX31_INT_GPT 29
	159	#define MX31_INT_POWER_FAIL 30
4f683a04	160	#define MX31_INT_CCM_DVFS 31
ebca1a55	161	#define MX31_INT_UART2 32
00b57bf9	162	#define MX31_INT_NFC 33
ebca1a55	163	#define MX31_INT_SDMA 34
4f683a04 UKK	164	#define MX31_INT_USB1 35
	165	#define MX31_INT_USB2 36
	166	#define MX31_INT_USB3 37
	167	#define MX31_INT_USB4 38
ebca1a55	168	#define MX31_INT_MSHC1 39
4f683a04	169	#define MX31_INT_MSHC2 40
ebca1a55 UKK	170	#define MX31_INT_IPU_ERR 41
	171	#define MX31_INT_IPU_SYN 42
	172	#define MX31_INT_UART1 45
4f683a04 UKK	173	#define MX31_INT_UART4 46
4f683a04 UKK	174	#define MX31_INT_UART5 47
ebca1a55 UKK	175	#define MX31_INT_ECT 48
	176	#define MX31_INT_SCC_SCM 49
	177	#define MX31_INT_SCC_SMN 50
	178	#define MX31_INT_GPIO2 51
	179	#define MX31_INT_GPIO1 52
4f683a04 UKK	180	#define MX31_INT_CCM 53
4f683a04 UKK	181	#define MX31_INT_PCMCIA 54
ebca1a55 UKK	182	#define MX31_INT_WDOG 55
	183	#define MX31_INT_GPIO3 56
	184	#define MX31_INT_EXT_POWER 58
	185	#define MX31_INT_EXT_TEMPER 59
	186	#define MX31_INT_EXT_SENSOR60 60
	187	#define MX31_INT_EXT_SENSOR61 61
	188	#define MX31_INT_EXT_WDOG 62
	189	#define MX31_INT_EXT_TV 63
	190
6a697e3d UKK	191	#define MX31_DMA_REQ_SDHC1 20
6a697e3d UKK	192	#define MX31_DMA_REQ_SDHC2 21
4697bb92 UKK	193	#define MX31_DMA_REQ_SSI2_RX1 22
	194	#define MX31_DMA_REQ_SSI2_TX1 23
	195	#define MX31_DMA_REQ_SSI2_RX0 24
	196	#define MX31_DMA_REQ_SSI2_TX0 25
	197	#define MX31_DMA_REQ_SSI1_RX1 26
	198	#define MX31_DMA_REQ_SSI1_TX1 27
	199	#define MX31_DMA_REQ_SSI1_RX0 28
	200	#define MX31_DMA_REQ_SSI1_TX0 29
	201
ebca1a55 UKK	202	#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
	203
	204	/* silicon revisions specific to i.MX31 */
	205	#define MX31_CHIP_REV_1_0 0x10
	206	#define MX31_CHIP_REV_1_1 0x11
	207	#define MX31_CHIP_REV_1_2 0x12
	208	#define MX31_CHIP_REV_1_3 0x13
	209	#define MX31_CHIP_REV_2_0 0x20
	210	#define MX31_CHIP_REV_2_1 0x21
	211	#define MX31_CHIP_REV_2_2 0x22
	212	#define MX31_CHIP_REV_2_3 0x23
	213	#define MX31_CHIP_REV_3_0 0x30
	214	#define MX31_CHIP_REV_3_1 0x31
	215	#define MX31_CHIP_REV_3_2 0x32
	216
	217	#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
	218	#define MX31_SYSTEM_REV_NUM 3
d2db9aaa	219
3cdd5441	220	#endif /* ifndef __MACH_MX31_H__ */