projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c0a5f855 SH |
1 | /* |
| 2 | * IRAM | |
| 3 | */ | |
| 4 | #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ | |
| ae55326a | 5 | #define MX35_IRAM_SIZE SZ_128K |
| c0a5f855 | 6 | |
| ae55326a UKK |
7 | #define MX35_FEC_BASE_ADDR 0x50038000 |
| 8 | #define MX35_OTG_BASE_ADDR 0x53ff4000 | |
| 9 | #define MX35_NFC_BASE_ADDR 0xbb000000 | |
| c0a5f855 SH |
10 | |
| 11 | /* | |
| 12 | * Interrupt numbers | |
| 13 | */ | |
| ae55326a | 14 | #define MX35_INT_OWIRE 2 |
| c0a5f855 | 15 | #define MX35_INT_MMC_SDHC1 7 |
| ae55326a UKK |
16 | #define MX35_INT_MMC_SDHC2 8 |
| 17 | #define MX35_INT_MMC_SDHC3 9 | |
| c0a5f855 SH |
18 | #define MX35_INT_SSI1 11 |
| 19 | #define MX35_INT_SSI2 12 | |
| ae55326a UKK |
20 | #define MX35_INT_GPU2D 16 |
| 21 | #define MX35_INT_ASRC 17 | |
| 22 | #define MX35_INT_USBHS 35 | |
| 23 | #define MX35_INT_USBOTG 37 | |
| 24 | #define MX35_INT_ESAI 40 | |
| 25 | #define MX35_INT_CAN1 43 | |
| 26 | #define MX35_INT_CAN2 44 | |
| 27 | #define MX35_INT_MLB 46 | |
| 28 | #define MX35_INT_SPDIF 47 | |
| 29 | #define MX35_INT_FEC 57 | |
| c0a5f855 | 30 | |
| ae55326a UKK |
31 | /* these should go away */ |
| 32 | #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR | |
| 33 | #define MXC_INT_OWIRE MX35_INT_OWIRE | |
| 34 | #define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2 | |
| 35 | #define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3 | |
| 36 | #define MXC_INT_GPU2D MX35_INT_GPU2D | |
| 37 | #define MXC_INT_ASRC MX35_INT_ASRC | |
| 38 | #define MXC_INT_USBHS MX35_INT_USBHS | |
| 39 | #define MXC_INT_USBOTG MX35_INT_USBOTG | |
| 40 | #define MXC_INT_ESAI MX35_INT_ESAI | |
| 41 | #define MXC_INT_CAN1 MX35_INT_CAN1 | |
| 42 | #define MXC_INT_CAN2 MX35_INT_CAN2 | |
| 43 | #define MXC_INT_MLB MX35_INT_MLB | |
| 44 | #define MXC_INT_SPDIF MX35_INT_SPDIF | |
| 45 | #define MXC_INT_FEC MX35_INT_FEC |