projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5a2db4e3 UKK |
1 | #ifndef __MACH_MX51_H__ |
| 2 | #define __MACH_MX51_H__ | |
| a329b48c | 3 | |
| 5443856c SH |
4 | /* |
| 5 | * IROM | |
| 6 | */ | |
| 7 | #define MX51_IROM_BASE_ADDR 0x0 | |
| 8 | #define MX51_IROM_SIZE SZ_64K | |
| 9 | ||
| a329b48c AK |
10 | /* |
| 11 | * IRAM | |
| 12 | */ | |
| 5a2db4e3 | 13 | #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ |
| a329b48c | 14 | #define MX51_IRAM_PARTITIONS 16 |
| a329b48c AK |
15 | #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ |
| 16 | ||
| 5a2db4e3 UKK |
17 | #define MX51_GPU_BASE_ADDR 0x20000000 |
| 18 | #define MX51_GPU_CTRL_BASE_ADDR 0x30000000 | |
| 19 | #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 | |
| 20 | ||
| a329b48c | 21 | /* |
| 5a2db4e3 | 22 | * SPBA global module enabled #0 |
| a329b48c | 23 | */ |
| 5a2db4e3 | 24 | #define MX51_SPBA0_BASE_ADDR 0x70000000 |
| 5a2db4e3 UKK |
25 | #define MX51_SPBA0_SIZE SZ_1M |
| 26 | ||
| c0745129 EB |
27 | #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) |
| 28 | #define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) | |
| 5a2db4e3 | 29 | #define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) |
| 68b5e858 | 30 | #define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) |
| 5a2db4e3 | 31 | #define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) |
| c0745129 EB |
32 | #define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) |
| 33 | #define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) | |
| 5a2db4e3 UKK |
34 | #define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000) |
| 35 | #define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000) | |
| 36 | #define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000) | |
| 37 | #define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000) | |
| 38 | #define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000) | |
| a329b48c AK |
39 | |
| 40 | /* | |
| 5a2db4e3 | 41 | * AIPS 1 |
| a329b48c | 42 | */ |
| 5a2db4e3 | 43 | #define MX51_AIPS1_BASE_ADDR 0x73f00000 |
| 5a2db4e3 UKK |
44 | #define MX51_AIPS1_SIZE SZ_1M |
| 45 | ||
| 46 | #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) | |
| 47 | #define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) | |
| 48 | #define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) | |
| 49 | #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) | |
| 50 | #define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) | |
| 51 | #define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) | |
| 8c2efec3 | 52 | #define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) |
| 5a2db4e3 UKK |
53 | #define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) |
| 54 | #define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) | |
| 55 | #define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) | |
| 56 | #define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000) | |
| 57 | #define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000) | |
| 58 | #define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000) | |
| 59 | #define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000) | |
| 60 | #define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000) | |
| 61 | #define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000) | |
| 62 | #define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000) | |
| 63 | #define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000) | |
| 64 | #define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000) | |
| 65 | #define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000) | |
| a329b48c | 66 | |
| 5a2db4e3 UKK |
67 | /* |
| 68 | * AIPS 2 | |
| 69 | */ | |
| 70 | #define MX51_AIPS2_BASE_ADDR 0x83f00000 | |
| 5a2db4e3 | 71 | #define MX51_AIPS2_SIZE SZ_1M |
| a329b48c | 72 | |
| 5a2db4e3 UKK |
73 | #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) |
| 74 | #define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000) | |
| 75 | #define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000) | |
| 76 | #define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000) | |
| 77 | #define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000) | |
| 78 | #define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000) | |
| 79 | #define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) | |
| 80 | #define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) | |
| 81 | #define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) | |
| 68b5e858 | 82 | #define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) |
| 5a2db4e3 UKK |
83 | #define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) |
| 84 | #define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) | |
| 85 | #define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) | |
| 86 | #define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) | |
| 68b5e858 | 87 | #define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) |
| 5a2db4e3 UKK |
88 | #define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) |
| 89 | #define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) | |
| 90 | #define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) | |
| 91 | #define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000) | |
| 92 | #define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000) | |
| 93 | #define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000) | |
| 94 | #define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000) | |
| 95 | #define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000) | |
| 96 | #define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00) | |
| 97 | #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) | |
| 98 | #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) | |
| 99 | #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) | |
| f2597223 | 100 | #define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) |
| 6bd96f3c | 101 | #define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) |
| 5a2db4e3 UKK |
102 | #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) |
| 103 | #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) | |
| 104 | #define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000) | |
| 105 | ||
| 106 | #define MX51_CSD0_BASE_ADDR 0x90000000 | |
| 107 | #define MX51_CSD1_BASE_ADDR 0xa0000000 | |
| 108 | #define MX51_CS0_BASE_ADDR 0xb0000000 | |
| 109 | #define MX51_CS1_BASE_ADDR 0xb8000000 | |
| 110 | #define MX51_CS2_BASE_ADDR 0xc0000000 | |
| 111 | #define MX51_CS3_BASE_ADDR 0xc8000000 | |
| 112 | #define MX51_CS4_BASE_ADDR 0xcc000000 | |
| 113 | #define MX51_CS5_BASE_ADDR 0xce000000 | |
| a329b48c AK |
114 | |
| 115 | /* | |
| 5a2db4e3 | 116 | * NFC |
| a329b48c | 117 | */ |
| 5a2db4e3 UKK |
118 | #define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */ |
| 119 | #define MX51_NFC_AXI_SIZE SZ_64K | |
| a329b48c | 120 | |
| 5a2db4e3 UKK |
121 | #define MX51_GPU2D_BASE_ADDR 0xd0000000 |
| 122 | #define MX51_TZIC_BASE_ADDR 0xe0000000 | |
| a329b48c | 123 | |
| a9963148 | 124 | #define MX51_IO_P2V(x) IMX_IO_P2V(x) |
| f5d7a13b | 125 | #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) |
| a8a05b85 | 126 | |
| a329b48c AK |
127 | /* |
| 128 | * defines for SPBA modules | |
| 129 | */ | |
| 130 | #define MX51_SPBA_SDHC1 0x04 | |
| 131 | #define MX51_SPBA_SDHC2 0x08 | |
| 5a2db4e3 | 132 | #define MX51_SPBA_UART3 0x0c |
| a329b48c AK |
133 | #define MX51_SPBA_CSPI1 0x10 |
| 134 | #define MX51_SPBA_SSI2 0x14 | |
| 135 | #define MX51_SPBA_SDHC3 0x20 | |
| 136 | #define MX51_SPBA_SDHC4 0x24 | |
| 137 | #define MX51_SPBA_SPDIF 0x28 | |
| 138 | #define MX51_SPBA_ATA 0x30 | |
| 139 | #define MX51_SPBA_SLIM 0x34 | |
| 140 | #define MX51_SPBA_HSI2C 0x38 | |
| 5a2db4e3 | 141 | #define MX51_SPBA_CTRL 0x3c |
| a329b48c AK |
142 | |
| 143 | /* | |
| 144 | * Defines for modules using static and dynamic DMA channels | |
| 145 | */ | |
| 146 | #define MX51_MXC_DMA_CHANNEL_IRAM 30 | |
| 147 | #define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL | |
| 148 | #define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL | |
| 149 | #define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL | |
| 150 | #define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL | |
| 151 | #define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL | |
| 152 | #define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL | |
| 153 | #define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL | |
| 154 | #define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL | |
| 155 | #define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL | |
| 156 | #define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL | |
| 157 | #define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL | |
| 158 | #define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL | |
| 159 | #ifdef CONFIG_SDMA_IRAM | |
| 160 | #define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1) | |
| 161 | #else /*CONFIG_SDMA_IRAM */ | |
| 162 | #define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL | |
| 163 | #endif /*CONFIG_SDMA_IRAM */ | |
| 164 | #define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL | |
| 165 | #define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL | |
| 166 | #define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL | |
| 167 | #define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL | |
| 168 | #define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL | |
| 169 | #define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL | |
| 170 | #define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL | |
| 171 | #define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL | |
| 172 | #define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL | |
| 173 | ||
| a329b48c AK |
174 | #define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 |
| 175 | ||
| 176 | /* | |
| 177 | * DMA request assignments | |
| 178 | */ | |
| 5a2db4e3 UKK |
179 | #define MX51_DMA_REQ_VPU 0 |
| 180 | #define MX51_DMA_REQ_GPC 1 | |
| 181 | #define MX51_DMA_REQ_ATA_RX 2 | |
| 182 | #define MX51_DMA_REQ_ATA_TX 3 | |
| 183 | #define MX51_DMA_REQ_ATA_TX_END 4 | |
| 184 | #define MX51_DMA_REQ_SLIM_B 5 | |
| 185 | #define MX51_DMA_REQ_CSPI1_RX 6 | |
| 186 | #define MX51_DMA_REQ_CSPI1_TX 7 | |
| 187 | #define MX51_DMA_REQ_CSPI2_RX 8 | |
| 188 | #define MX51_DMA_REQ_CSPI2_TX 9 | |
| 189 | #define MX51_DMA_REQ_HS_I2C_TX 10 | |
| 190 | #define MX51_DMA_REQ_HS_I2C_RX 11 | |
| 191 | #define MX51_DMA_REQ_FIRI_RX 12 | |
| 192 | #define MX51_DMA_REQ_FIRI_TX 13 | |
| 193 | #define MX51_DMA_REQ_EXTREQ1 14 | |
| 194 | #define MX51_DMA_REQ_GPU 15 | |
| 195 | #define MX51_DMA_REQ_UART2_RX 16 | |
| 196 | #define MX51_DMA_REQ_UART2_TX 17 | |
| 197 | #define MX51_DMA_REQ_UART1_RX 18 | |
| 198 | #define MX51_DMA_REQ_UART1_TX 19 | |
| 199 | #define MX51_DMA_REQ_SDHC1 20 | |
| 200 | #define MX51_DMA_REQ_SDHC2 21 | |
| b8618661 SH |
201 | #define MX51_DMA_REQ_SSI2_RX1 22 |
| 202 | #define MX51_DMA_REQ_SSI2_TX1 23 | |
| 203 | #define MX51_DMA_REQ_SSI2_RX0 24 | |
| 204 | #define MX51_DMA_REQ_SSI2_TX0 25 | |
| 205 | #define MX51_DMA_REQ_SSI1_RX1 26 | |
| 206 | #define MX51_DMA_REQ_SSI1_TX1 27 | |
| 207 | #define MX51_DMA_REQ_SSI1_RX0 28 | |
| 208 | #define MX51_DMA_REQ_SSI1_TX0 29 | |
| 5a2db4e3 UKK |
209 | #define MX51_DMA_REQ_EMI_RD 30 |
| 210 | #define MX51_DMA_REQ_CTI2_0 31 | |
| 211 | #define MX51_DMA_REQ_EMI_WR 32 | |
| 212 | #define MX51_DMA_REQ_CTI2_1 33 | |
| 213 | #define MX51_DMA_REQ_EPIT2 34 | |
| f2597223 | 214 | #define MX51_DMA_REQ_SSI3_RX1 35 |
| 5a2db4e3 | 215 | #define MX51_DMA_REQ_IPU 36 |
| f2597223 | 216 | #define MX51_DMA_REQ_SSI3_TX1 37 |
| 5a2db4e3 UKK |
217 | #define MX51_DMA_REQ_CSPI_RX 38 |
| 218 | #define MX51_DMA_REQ_CSPI_TX 39 | |
| 219 | #define MX51_DMA_REQ_SDHC3 40 | |
| 220 | #define MX51_DMA_REQ_SDHC4 41 | |
| 221 | #define MX51_DMA_REQ_SLIM_B_TX 42 | |
| 222 | #define MX51_DMA_REQ_UART3_RX 43 | |
| 223 | #define MX51_DMA_REQ_UART3_TX 44 | |
| 224 | #define MX51_DMA_REQ_SPDIF 45 | |
| f2597223 PH |
225 | #define MX51_DMA_REQ_SSI3_RX0 46 |
| 226 | #define MX51_DMA_REQ_SSI3_TX0 47 | |
| a329b48c AK |
227 | |
| 228 | /* | |
| 229 | * Interrupt numbers | |
| 230 | */ | |
| 5a2db4e3 UKK |
231 | #define MX51_MXC_INT_BASE 0 |
| 232 | #define MX51_MXC_INT_RESV0 0 | |
| c0745129 EB |
233 | #define MX51_INT_ESDHC1 1 |
| 234 | #define MX51_INT_ESDHC2 2 | |
| 235 | #define MX51_INT_ESDHC3 3 | |
| 236 | #define MX51_INT_ESDHC4 4 | |
| 5a2db4e3 | 237 | #define MX51_MXC_INT_RESV5 5 |
| 8a8d2060 | 238 | #define MX51_INT_SDMA 6 |
| 5a2db4e3 | 239 | #define MX51_MXC_INT_IOMUX 7 |
| 63a7c6d7 | 240 | #define MX51_INT_NFC 8 |
| 5a2db4e3 | 241 | #define MX51_MXC_INT_VPU 9 |
| 96de6d44 SH |
242 | #define MX51_INT_IPU_ERR 10 |
| 243 | #define MX51_INT_IPU_SYN 11 | |
| 5a2db4e3 UKK |
244 | #define MX51_MXC_INT_GPU 12 |
| 245 | #define MX51_MXC_INT_RESV13 13 | |
| 246 | #define MX51_MXC_INT_USB_H1 14 | |
| 247 | #define MX51_MXC_INT_EMI 15 | |
| 248 | #define MX51_MXC_INT_USB_H2 16 | |
| 249 | #define MX51_MXC_INT_USB_H3 17 | |
| 250 | #define MX51_MXC_INT_USB_OTG 18 | |
| 251 | #define MX51_MXC_INT_SAHARA_H0 19 | |
| 252 | #define MX51_MXC_INT_SAHARA_H1 20 | |
| 253 | #define MX51_MXC_INT_SCC_SMN 21 | |
| 254 | #define MX51_MXC_INT_SCC_STZ 22 | |
| 255 | #define MX51_MXC_INT_SCC_SCM 23 | |
| 256 | #define MX51_MXC_INT_SRTC_NTZ 24 | |
| 257 | #define MX51_MXC_INT_SRTC_TZ 25 | |
| 258 | #define MX51_MXC_INT_RTIC 26 | |
| 259 | #define MX51_MXC_INT_CSU 27 | |
| 260 | #define MX51_MXC_INT_SLIM_B 28 | |
| b8618661 SH |
261 | #define MX51_INT_SSI1 29 |
| 262 | #define MX51_INT_SSI2 30 | |
| 04b73b15 UKK |
263 | #define MX51_INT_UART1 31 |
| 264 | #define MX51_INT_UART2 32 | |
| 265 | #define MX51_INT_UART3 33 | |
| 5a2db4e3 UKK |
266 | #define MX51_MXC_INT_RESV34 34 |
| 267 | #define MX51_MXC_INT_RESV35 35 | |
| 68b5e858 UKK |
268 | #define MX51_INT_ECSPI1 36 |
| 269 | #define MX51_INT_ECSPI2 37 | |
| 270 | #define MX51_INT_CSPI 38 | |
| 5a2db4e3 UKK |
271 | #define MX51_MXC_INT_GPT 39 |
| 272 | #define MX51_MXC_INT_EPIT1 40 | |
| 273 | #define MX51_MXC_INT_EPIT2 41 | |
| 274 | #define MX51_MXC_INT_GPIO1_INT7 42 | |
| 275 | #define MX51_MXC_INT_GPIO1_INT6 43 | |
| 276 | #define MX51_MXC_INT_GPIO1_INT5 44 | |
| 277 | #define MX51_MXC_INT_GPIO1_INT4 45 | |
| 278 | #define MX51_MXC_INT_GPIO1_INT3 46 | |
| 279 | #define MX51_MXC_INT_GPIO1_INT2 47 | |
| 280 | #define MX51_MXC_INT_GPIO1_INT1 48 | |
| 281 | #define MX51_MXC_INT_GPIO1_INT0 49 | |
| 282 | #define MX51_MXC_INT_GPIO1_LOW 50 | |
| 283 | #define MX51_MXC_INT_GPIO1_HIGH 51 | |
| 284 | #define MX51_MXC_INT_GPIO2_LOW 52 | |
| 285 | #define MX51_MXC_INT_GPIO2_HIGH 53 | |
| 286 | #define MX51_MXC_INT_GPIO3_LOW 54 | |
| 287 | #define MX51_MXC_INT_GPIO3_HIGH 55 | |
| 288 | #define MX51_MXC_INT_GPIO4_LOW 56 | |
| 289 | #define MX51_MXC_INT_GPIO4_HIGH 57 | |
| 290 | #define MX51_MXC_INT_WDOG1 58 | |
| 291 | #define MX51_MXC_INT_WDOG2 59 | |
| a5fcfef0 | 292 | #define MX51_INT_KPP 60 |
| 076762aa | 293 | #define MX51_INT_PWM1 61 |
| 64de5ec1 UKK |
294 | #define MX51_INT_I2C1 62 |
| 295 | #define MX51_INT_I2C2 63 | |
| 5a2db4e3 UKK |
296 | #define MX51_MXC_INT_HS_I2C 64 |
| 297 | #define MX51_MXC_INT_RESV65 65 | |
| 298 | #define MX51_MXC_INT_RESV66 66 | |
| 299 | #define MX51_MXC_INT_SIM_IPB 67 | |
| 300 | #define MX51_MXC_INT_SIM_DAT 68 | |
| 301 | #define MX51_MXC_INT_IIM 69 | |
| 302 | #define MX51_MXC_INT_ATA 70 | |
| 303 | #define MX51_MXC_INT_CCM1 71 | |
| 304 | #define MX51_MXC_INT_CCM2 72 | |
| 305 | #define MX51_MXC_INT_GPC1 73 | |
| 306 | #define MX51_MXC_INT_GPC2 74 | |
| 307 | #define MX51_MXC_INT_SRC 75 | |
| 308 | #define MX51_MXC_INT_NM 76 | |
| 309 | #define MX51_MXC_INT_PMU 77 | |
| 310 | #define MX51_MXC_INT_CTI_IRQ 78 | |
| 311 | #define MX51_MXC_INT_CTI1_TG0 79 | |
| 312 | #define MX51_MXC_INT_CTI1_TG1 80 | |
| 313 | #define MX51_MXC_INT_MCG_ERR 81 | |
| 314 | #define MX51_MXC_INT_MCG_TMR 82 | |
| 315 | #define MX51_MXC_INT_MCG_FUNC 83 | |
| 316 | #define MX51_MXC_INT_GPU2_IRQ 84 | |
| 317 | #define MX51_MXC_INT_GPU2_BUSY 85 | |
| 318 | #define MX51_MXC_INT_RESV86 86 | |
| 6bd96f3c | 319 | #define MX51_INT_FEC 87 |
| 5a2db4e3 UKK |
320 | #define MX51_MXC_INT_OWIRE 88 |
| 321 | #define MX51_MXC_INT_CTI1_TG2 89 | |
| 322 | #define MX51_MXC_INT_SJC 90 | |
| 323 | #define MX51_MXC_INT_SPDIF 91 | |
| 324 | #define MX51_MXC_INT_TVE 92 | |
| 325 | #define MX51_MXC_INT_FIRI 93 | |
| 076762aa | 326 | #define MX51_INT_PWM2 94 |
| 5a2db4e3 | 327 | #define MX51_MXC_INT_SLIM_EXP 95 |
| f2597223 | 328 | #define MX51_INT_SSI3 96 |
| 5a2db4e3 UKK |
329 | #define MX51_MXC_INT_EMI_BOOT 97 |
| 330 | #define MX51_MXC_INT_CTI1_TG3 98 | |
| 331 | #define MX51_MXC_INT_SMC_RX 99 | |
| 332 | #define MX51_MXC_INT_VPU_IDLE 100 | |
| 333 | #define MX51_MXC_INT_EMI_NFC 101 | |
| 334 | #define MX51_MXC_INT_GPU_IDLE 102 | |
| a329b48c | 335 | |
| a329b48c | 336 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
| 5443856c | 337 | extern int mx51_revision(void); |
| 76422dbf | 338 | extern void mx51_display_revision(void); |
| a329b48c AK |
339 | #endif |
| 340 | ||
| 5a2db4e3 UKK |
341 | /* tape-out 1 defines */ |
| 342 | #define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000 | |
| 343 | ||
| 344 | #endif /* ifndef __MACH_MX51_H__ */ |