[deliverable/linux.git] / arch / arm / plat-mxc / include / mach / mx51.h

#ifndef __ASM_ARCH_MXC_MX51_H__
#define __ASM_ARCH_MXC_MX51_H__

/*
 * MX51 memory map:
 *
 *
 * Virt		Phys		Size	What
 * ---------------------------------------------------------------------------
 * FA3E0000	1FFE0000	128K	IRAM (SCCv2 RAM)
 *         	30000000	256M	GPU
 *         	40000000	512M	IPU
 * FA200000	60000000	1M	DEBUG
 * FB100000	70000000	1M	SPBA 0
 * FB000000	73F00000	1M	AIPS 1
 * FB200000	83F00000	1M	AIPS 2
 *		8FFFC000	16K	TZIC (interrupt controller)
 *         	90000000	256M	CSD0 SDRAM/DDR
 *         	A0000000	256M	CSD1 SDRAM/DDR
 *         	B0000000	128M	CS0 Flash
 *         	B8000000	128M	CS1 Flash
 *         	C0000000	128M	CS2 Flash
 *         	C8000000	64M	CS3 Flash
 *         	CC000000	32M	CS4 SRAM
 *         	CE000000	32M	CS5 SRAM
 *		CFFF0000	64K	NFC (NAND Flash AXI)
 *
 */

/*
 * IROM
 */
#define MX51_IROM_BASE_ADDR		0x0
#define MX51_IROM_SIZE			SZ_64K

/*
 * IRAM
 */
#define MX51_IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
#define MX51_IRAM_BASE_ADDR_VIRT	0xFA3E0000
#define MX51_IRAM_PARTITIONS		16
#define MX51_IRAM_PARTITIONS_TO1	12
#define MX51_IRAM_SIZE		(MX51_IRAM_PARTITIONS * SZ_8K)	/* 128KB */

/*
 * NFC
 */
#define MX51_NFC_AXI_BASE_ADDR		0xCFFF0000	/* NAND flash AXI */
#define MX51_NFC_AXI_SIZE		SZ_64K

/*
 * Graphics Memory of GPU
 */
#define MX51_GPU_BASE_ADDR		0x20000000
#define MX51_GPU2D_BASE_ADDR		0xD0000000

#define MX51_TZIC_BASE_ADDR_TO1		0x8FFFC000
#define MX51_TZIC_BASE_ADDR		0xE0000000

#define MX51_DEBUG_BASE_ADDR		0x60000000
#define MX51_DEBUG_BASE_ADDR_VIRT	0xFA200000
#define MX51_DEBUG_SIZE			SZ_1M
#define MX51_ETB_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00001000)
#define MX51_ETM_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00002000)
#define MX51_TPIU_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00003000)
#define MX51_CTI0_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00004000)
#define MX51_CTI1_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00005000)
#define MX51_CTI2_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00006000)
#define MX51_CTI3_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00007000)
#define MX51_CORTEX_DBG_BASE_ADDR	(MX51_DEBUG_BASE_ADDR + 0x00008000)

/*
 * SPBA global module enabled #0
 */
#define MX51_SPBA0_BASE_ADDR 		0x70000000
#define MX51_SPBA0_BASE_ADDR_VIRT	0xFB100000
#define MX51_SPBA0_SIZE			SZ_1M

#define MX51_MMC_SDHC1_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00004000)
#define MX51_MMC_SDHC2_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00008000)
#define MX51_UART3_BASE_ADDR 		(MX51_SPBA0_BASE_ADDR + 0x0000C000)
#define MX51_CSPI1_BASE_ADDR 		(MX51_SPBA0_BASE_ADDR + 0x00010000)
#define MX51_SSI2_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00014000)
#define MX51_MMC_SDHC3_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00020000)
#define MX51_MMC_SDHC4_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00024000)
#define MX51_SPDIF_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00028000)
#define MX51_ATA_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00030000)
#define MX51_SLIM_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00034000)
#define MX51_HSI2C_DMA_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00038000)
#define MX51_SPBA_CTRL_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x0003C000)

/*
 * defines for SPBA modules
 */
#define MX51_SPBA_SDHC1	0x04
#define MX51_SPBA_SDHC2	0x08
#define MX51_SPBA_UART3	0x0C
#define MX51_SPBA_CSPI1	0x10
#define MX51_SPBA_SSI2	0x14
#define MX51_SPBA_SDHC3	0x20
#define MX51_SPBA_SDHC4	0x24
#define MX51_SPBA_SPDIF	0x28
#define MX51_SPBA_ATA	0x30
#define MX51_SPBA_SLIM	0x34
#define MX51_SPBA_HSI2C	0x38
#define MX51_SPBA_CTRL	0x3C

/*
 * AIPS 1
 */
#define MX51_AIPS1_BASE_ADDR 	0x73F00000
#define MX51_AIPS1_BASE_ADDR_VIRT	0xFB000000
#define MX51_AIPS1_SIZE		SZ_1M

#define MX51_OTG_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00080000)
#define MX51_GPIO1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00084000)
#define MX51_GPIO2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00088000)
#define MX51_GPIO3_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x0008C000)
#define MX51_GPIO4_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00090000)
#define MX51_KPP_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00094000)
#define MX51_WDOG_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00098000)
#define MX51_WDOG2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x0009C000)
#define MX51_GPT1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A0000)
#define MX51_SRTC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A4000)
#define MX51_IOMUXC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A8000)
#define MX51_EPIT1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000AC000)
#define MX51_EPIT2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B0000)
#define MX51_PWM1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B4000)
#define MX51_PWM2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B8000)
#define MX51_UART1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000BC000)
#define MX51_UART2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000C0000)
#define MX51_SRC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D0000)
#define MX51_CCM_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D4000)
#define MX51_GPC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D8000)

/*
 * Defines for modules using static and dynamic DMA channels
 */
#define MX51_MXC_DMA_CHANNEL_IRAM	30
#define MX51_MXC_DMA_CHANNEL_SPDIF_TX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART1_RX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART1_TX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART2_RX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART2_TX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART3_RX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART3_TX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_MMC1	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_MMC2	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_SSI1_RX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_SSI1_TX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_SSI2_RX	MXC_DMA_DYNAMIC_CHANNEL
#ifdef CONFIG_SDMA_IRAM
#define MX51_MXC_DMA_CHANNEL_SSI2_TX	(MX51_MXC_DMA_CHANNEL_IRAM + 1)
#else				/*CONFIG_SDMA_IRAM */
#define MX51_MXC_DMA_CHANNEL_SSI2_TX	MXC_DMA_DYNAMIC_CHANNEL
#endif				/*CONFIG_SDMA_IRAM */
#define MX51_MXC_DMA_CHANNEL_CSPI1_RX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_CSPI1_TX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_CSPI2_RX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_CSPI2_TX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_CSPI3_RX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_CSPI3_TX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_ATA_RX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_ATA_TX	MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_MEMORY	MXC_DMA_DYNAMIC_CHANNEL

/*
 * AIPS 2
 */
#define MX51_AIPS2_BASE_ADDR		0x83F00000
#define MX51_AIPS2_BASE_ADDR_VIRT	0xFB200000
#define MX51_AIPS2_SIZE			SZ_1M

#define MX51_PLL1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00080000)
#define MX51_PLL2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00084000)
#define MX51_PLL3_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00088000)
#define MX51_AHBMAX_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00094000)
#define MX51_IIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00098000)
#define MX51_CSU_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x0009C000)
#define MX51_ARM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000A0000)
#define MX51_OWIRE_BASE_ADDR 	(MX51_AIPS2_BASE_ADDR + 0x000A4000)
#define MX51_FIRI_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000A8000)
#define MX51_CSPI2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000AC000)
#define MX51_SDMA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B0000)
#define MX51_SCC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B4000)
#define MX51_ROMCP_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B8000)
#define MX51_RTIC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000BC000)
#define MX51_CSPI3_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C0000)
#define MX51_I2C2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C4000)
#define MX51_I2C1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C8000)
#define MX51_SSI1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000CC000)
#define MX51_AUDMUX_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D0000)
#define MX51_M4IF_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D8000)
#define MX51_ESDCTL_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D9000)
#define MX51_WEIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DA000)
#define MX51_NFC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DB000)
#define MX51_EMI_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DBF00)
#define MX51_MIPI_HSC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DC000)
#define MX51_ATA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E0000)
#define MX51_SIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E4000)
#define MX51_SSI3BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E8000)
#define MX51_MXC_FEC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000EC000)
#define MX51_TVE_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F0000)
#define MX51_VPU_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F4000)
#define MX51_SAHARA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F8000)

/*
 * Memory regions and CS
 */
#define MX51_GPU_CTRL_BASE_ADDR		0x30000000
#define MX51_IPU_CTRL_BASE_ADDR		0x40000000
#define MX51_CSD0_BASE_ADDR		0x90000000
#define MX51_CSD1_BASE_ADDR		0xA0000000
#define MX51_CS0_BASE_ADDR		0xB0000000
#define MX51_CS1_BASE_ADDR		0xB8000000
#define MX51_CS2_BASE_ADDR		0xC0000000
#define MX51_CS3_BASE_ADDR		0xC8000000
#define MX51_CS4_BASE_ADDR		0xCC000000
#define MX51_CS5_BASE_ADDR		0xCE000000

/* Does given address belongs to the specified memory region? */
#define ADDRESS_IN_REGION(addr, start, size)			\
	(((addr) >= (start)) && ((addr) < (start)+(size)))

/* Does given address belongs to the specified named `module'? */
#define MX51_IS_MODULE(addr, module)			       \
	ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
				MX51_ ## module ## _SIZE)
/*
 * This macro defines the physical to virtual address mapping for all the
 * peripheral modules. It is used by passing in the physical address as x
 * and returning the virtual address. If the physical address is not mapped,
 * it returns 0xDEADBEEF
 */

#define MX51_IO_ADDRESS(x)					\
	(void __iomem *)					\
	(MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) :	\
	MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) :	\
	MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) :	\
	MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) :	\
	MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
	0xDEADBEEF)

/*
 * define the address mapping macros: in physical address order
 */
#define MX51_IRAM_IO_ADDRESS(x)  \
	(((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)

#define MX51_DEBUG_IO_ADDRESS(x)  \
	(((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)

#define MX51_SPBA0_IO_ADDRESS(x)  \
	(((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)

#define MX51_AIPS1_IO_ADDRESS(x)  \
	(((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)

#define MX51_AIPS2_IO_ADDRESS(x)  \
	(((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)

#define MX51_IS_MEM_DEVICE_NONSHARED(x)		0

/*
 * DMA request assignments
 */
#define MX51_DMA_REQ_SSI3_TX1	47
#define MX51_DMA_REQ_SSI3_RX1	46
#define MX51_DMA_REQ_SPDIF	45
#define MX51_DMA_REQ_UART3_TX	44
#define MX51_DMA_REQ_UART3_RX	43
#define MX51_DMA_REQ_SLIM_B_TX	42
#define MX51_DMA_REQ_SDHC4	41
#define MX51_DMA_REQ_SDHC3	40
#define MX51_DMA_REQ_CSPI_TX	39
#define MX51_DMA_REQ_CSPI_RX	38
#define MX51_DMA_REQ_SSI3_TX2	37
#define MX51_DMA_REQ_IPU	36
#define MX51_DMA_REQ_SSI3_RX2	35
#define MX51_DMA_REQ_EPIT2	34
#define MX51_DMA_REQ_CTI2_1	33
#define MX51_DMA_REQ_EMI_WR	32
#define MX51_DMA_REQ_CTI2_0	31
#define MX51_DMA_REQ_EMI_RD	30
#define MX51_DMA_REQ_SSI1_TX1	29
#define MX51_DMA_REQ_SSI1_RX1	28
#define MX51_DMA_REQ_SSI1_TX2	27
#define MX51_DMA_REQ_SSI1_RX2	26
#define MX51_DMA_REQ_SSI2_TX1	25
#define MX51_DMA_REQ_SSI2_RX1	24
#define MX51_DMA_REQ_SSI2_TX2	23
#define MX51_DMA_REQ_SSI2_RX2	22
#define MX51_DMA_REQ_SDHC2	21
#define MX51_DMA_REQ_SDHC1	20
#define MX51_DMA_REQ_UART1_TX	19
#define MX51_DMA_REQ_UART1_RX	18
#define MX51_DMA_REQ_UART2_TX	17
#define MX51_DMA_REQ_UART2_RX	16
#define MX51_DMA_REQ_GPU	15
#define MX51_DMA_REQ_EXTREQ1	14
#define MX51_DMA_REQ_FIRI_TX	13
#define MX51_DMA_REQ_FIRI_RX	12
#define MX51_DMA_REQ_HS_I2C_RX	11
#define MX51_DMA_REQ_HS_I2C_TX	10
#define MX51_DMA_REQ_CSPI2_TX	9
#define MX51_DMA_REQ_CSPI2_RX	8
#define MX51_DMA_REQ_CSPI1_TX	7
#define MX51_DMA_REQ_CSPI1_RX	6
#define MX51_DMA_REQ_SLIM_B	5
#define MX51_DMA_REQ_ATA_TX_END	4
#define MX51_DMA_REQ_ATA_TX	3
#define MX51_DMA_REQ_ATA_RX	2
#define MX51_DMA_REQ_GPC	1
#define MX51_DMA_REQ_VPU	0

/*
 * Interrupt numbers
 */
#define MX51_MXC_INT_BASE	0
#define MX51_MXC_INT_RESV0	0
#define MX51_MXC_INT_MMC_SDHC1	1
#define MX51_MXC_INT_MMC_SDHC2	2
#define MX51_MXC_INT_MMC_SDHC3	3
#define MX51_MXC_INT_MMC_SDHC4	4
#define MX51_MXC_INT_RESV5	5
#define MX51_MXC_INT_SDMA	6
#define MX51_MXC_INT_IOMUX	7
#define MX51_MXC_INT_NFC	8
#define MX51_MXC_INT_VPU	9
#define MX51_MXC_INT_IPU_ERR	10
#define MX51_MXC_INT_IPU_SYN	11
#define MX51_MXC_INT_GPU	12
#define MX51_MXC_INT_RESV13	13
#define MX51_MXC_INT_USB_H1	14
#define MX51_MXC_INT_EMI	15
#define MX51_MXC_INT_USB_H2	16
#define MX51_MXC_INT_USB_H3	17
#define MX51_MXC_INT_USB_OTG	18
#define MX51_MXC_INT_SAHARA_H0	19
#define MX51_MXC_INT_SAHARA_H1	20
#define MX51_MXC_INT_SCC_SMN	21
#define MX51_MXC_INT_SCC_STZ	22
#define MX51_MXC_INT_SCC_SCM	23
#define MX51_MXC_INT_SRTC_NTZ	24
#define MX51_MXC_INT_SRTC_TZ	25
#define MX51_MXC_INT_RTIC	26
#define MX51_MXC_INT_CSU	27
#define MX51_MXC_INT_SLIM_B	28
#define MX51_MXC_INT_SSI1	29
#define MX51_MXC_INT_SSI2	30
#define MX51_MXC_INT_UART1	31
#define MX51_MXC_INT_UART2	32
#define MX51_MXC_INT_UART3	33
#define MX51_MXC_INT_RESV34	34
#define MX51_MXC_INT_RESV35	35
#define MX51_MXC_INT_CSPI1	36
#define MX51_MXC_INT_CSPI2	37
#define MX51_MXC_INT_CSPI	38
#define MX51_MXC_INT_GPT	39
#define MX51_MXC_INT_EPIT1	40
#define MX51_MXC_INT_EPIT2	41
#define MX51_MXC_INT_GPIO1_INT7	42
#define MX51_MXC_INT_GPIO1_INT6	43
#define MX51_MXC_INT_GPIO1_INT5	44
#define MX51_MXC_INT_GPIO1_INT4	45
#define MX51_MXC_INT_GPIO1_INT3	46
#define MX51_MXC_INT_GPIO1_INT2	47
#define MX51_MXC_INT_GPIO1_INT1	48
#define MX51_MXC_INT_GPIO1_INT0	49
#define MX51_MXC_INT_GPIO1_LOW	50
#define MX51_MXC_INT_GPIO1_HIGH	51
#define MX51_MXC_INT_GPIO2_LOW	52
#define MX51_MXC_INT_GPIO2_HIGH	53
#define MX51_MXC_INT_GPIO3_LOW	54
#define MX51_MXC_INT_GPIO3_HIGH	55
#define MX51_MXC_INT_GPIO4_LOW	56
#define MX51_MXC_INT_GPIO4_HIGH	57
#define MX51_MXC_INT_WDOG1	58
#define MX51_MXC_INT_WDOG2	59
#define MX51_MXC_INT_KPP	60
#define MX51_MXC_INT_PWM1	61
#define MX51_MXC_INT_I2C1	62
#define MX51_MXC_INT_I2C2	63
#define MX51_MXC_INT_HS_I2C	64
#define MX51_MXC_INT_RESV65	65
#define MX51_MXC_INT_RESV66	66
#define MX51_MXC_INT_SIM_IPB	67
#define MX51_MXC_INT_SIM_DAT	68
#define MX51_MXC_INT_IIM	69
#define MX51_MXC_INT_ATA	70
#define MX51_MXC_INT_CCM1	71
#define MX51_MXC_INT_CCM2	72
#define MX51_MXC_INT_GPC1	73
#define MX51_MXC_INT_GPC2	74
#define MX51_MXC_INT_SRC	75
#define MX51_MXC_INT_NM		76
#define MX51_MXC_INT_PMU	77
#define MX51_MXC_INT_CTI_IRQ	78
#define MX51_MXC_INT_CTI1_TG0	79
#define MX51_MXC_INT_CTI1_TG1	80
#define MX51_MXC_INT_MCG_ERR	81
#define MX51_MXC_INT_MCG_TMR	82
#define MX51_MXC_INT_MCG_FUNC	83
#define MX51_MXC_INT_GPU2_IRQ	84
#define MX51_MXC_INT_GPU2_BUSY	85
#define MX51_MXC_INT_RESV86	86
#define MX51_MXC_INT_FEC	87
#define MX51_MXC_INT_OWIRE	88
#define MX51_MXC_INT_CTI1_TG2	89
#define MX51_MXC_INT_SJC	90
#define MX51_MXC_INT_SPDIF	91
#define MX51_MXC_INT_TVE	92
#define MX51_MXC_INT_FIRI	93
#define MX51_MXC_INT_PWM2	94
#define MX51_MXC_INT_SLIM_EXP	95
#define MX51_MXC_INT_SSI3	96
#define MX51_MXC_INT_EMI_BOOT	97
#define MX51_MXC_INT_CTI1_TG3	98
#define MX51_MXC_INT_SMC_RX	99
#define MX51_MXC_INT_VPU_IDLE	100
#define MX51_MXC_INT_EMI_NFC	101
#define MX51_MXC_INT_GPU_IDLE	102

/* silicon revisions specific to i.MX51 */
#define MX51_CHIP_REV_1_0	0x10
#define MX51_CHIP_REV_1_1	0x11
#define MX51_CHIP_REV_1_2	0x12
#define MX51_CHIP_REV_1_3	0x13
#define MX51_CHIP_REV_2_0	0x20
#define MX51_CHIP_REV_2_1	0x21
#define MX51_CHIP_REV_2_2	0x22
#define MX51_CHIP_REV_2_3	0x23
#define MX51_CHIP_REV_3_0	0x30
#define MX51_CHIP_REV_3_1	0x31
#define MX51_CHIP_REV_3_2	0x32

/* Mandatory defines used globally */

#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)

extern int mx51_revision(void);
#endif

#endif	/*  __ASM_ARCH_MXC_MX51_H__ */
Commit	Line	Data
a329b48c AK	1	#ifndef __ASM_ARCH_MXC_MX51_H__
	2	#define __ASM_ARCH_MXC_MX51_H__
	3
	4	/*
	5	* MX51 memory map:
	6	*
	7	*
	8	* Virt Phys Size What
	9	* ---------------------------------------------------------------------------
	10	* FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM)
	11	* 30000000 256M GPU
	12	* 40000000 512M IPU
	13	* FA200000 60000000 1M DEBUG
	14	* FB100000 70000000 1M SPBA 0
	15	* FB000000 73F00000 1M AIPS 1
	16	* FB200000 83F00000 1M AIPS 2
3d1bc862	17	* 8FFFC000 16K TZIC (interrupt controller)
a329b48c AK	18	* 90000000 256M CSD0 SDRAM/DDR
	19	* A0000000 256M CSD1 SDRAM/DDR
	20	* B0000000 128M CS0 Flash
	21	* B8000000 128M CS1 Flash
	22	* C0000000 128M CS2 Flash
	23	* C8000000 64M CS3 Flash
	24	* CC000000 32M CS4 SRAM
	25	* CE000000 32M CS5 SRAM
fc300206	26	* CFFF0000 64K NFC (NAND Flash AXI)
a329b48c AK	27	*
	28	*/
	29
5443856c SH	30	/*
	31	* IROM
	32	*/
	33	#define MX51_IROM_BASE_ADDR 0x0
	34	#define MX51_IROM_SIZE SZ_64K
	35
a329b48c AK	36	/*
	37	* IRAM
	38	*/
	39	#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
	40	#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000
	41	#define MX51_IRAM_PARTITIONS 16
	42	#define MX51_IRAM_PARTITIONS_TO1 12
	43	#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
	44
	45	/*
	46	* NFC
	47	*/
	48	#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */
a329b48c AK	49	#define MX51_NFC_AXI_SIZE SZ_64K
	50
	51	/*
	52	* Graphics Memory of GPU
	53	*/
	54	#define MX51_GPU_BASE_ADDR 0x20000000
	55	#define MX51_GPU2D_BASE_ADDR 0xD0000000
	56
3d1bc862 SH	57	#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000
3d1bc862 SH	58	#define MX51_TZIC_BASE_ADDR 0xE0000000
a329b48c AK	59
	60	#define MX51_DEBUG_BASE_ADDR 0x60000000
	61	#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
	62	#define MX51_DEBUG_SIZE SZ_1M
	63	#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000)
	64	#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000)
	65	#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000)
	66	#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000)
	67	#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000)
	68	#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000)
	69	#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000)
	70	#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000)
	71
	72	/*
	73	* SPBA global module enabled #0
	74	*/
	75	#define MX51_SPBA0_BASE_ADDR 0x70000000
	76	#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000
	77	#define MX51_SPBA0_SIZE SZ_1M
	78
	79	#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000)
	80	#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000)
	81	#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000)
	82	#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
	83	#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000)
	84	#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000)
	85	#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000)
	86	#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000)
	87	#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000)
	88	#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000)
	89	#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000)
	90	#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000)
	91
	92	/*
	93	* defines for SPBA modules
	94	*/
	95	#define MX51_SPBA_SDHC1 0x04
	96	#define MX51_SPBA_SDHC2 0x08
	97	#define MX51_SPBA_UART3 0x0C
	98	#define MX51_SPBA_CSPI1 0x10
	99	#define MX51_SPBA_SSI2 0x14
	100	#define MX51_SPBA_SDHC3 0x20
	101	#define MX51_SPBA_SDHC4 0x24
	102	#define MX51_SPBA_SPDIF 0x28
	103	#define MX51_SPBA_ATA 0x30
	104	#define MX51_SPBA_SLIM 0x34
	105	#define MX51_SPBA_HSI2C 0x38
	106	#define MX51_SPBA_CTRL 0x3C
	107
	108	/*
	109	* AIPS 1
	110	*/
	111	#define MX51_AIPS1_BASE_ADDR 0x73F00000
	112	#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
	113	#define MX51_AIPS1_SIZE SZ_1M
	114
	115	#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
	116	#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
	117	#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
	118	#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
	119	#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
	120	#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
	121	#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
	122	#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
123	#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
124	#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
125	#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
126	#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
127	#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
128	#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
129	#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
130	#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
131	#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
132	#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
133	#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
134	#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
135
136	/*
137	* Defines for modules using static and dynamic DMA channels
138	*/
139	#define MX51_MXC_DMA_CHANNEL_IRAM 30
140	#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
141	#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
142	#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
143	#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
144	#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
145	#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
146	#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
147	#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
148	#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
149	#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
150	#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
151	#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
152	#ifdef CONFIG_SDMA_IRAM
153	#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
154	#else /CONFIG_SDMA_IRAM /
155	#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
156	#endif /CONFIG_SDMA_IRAM /
157	#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
158	#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
159	#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
160	#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
161	#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
162	#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
163	#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
164	#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
165	#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
166
167	/*
168	* AIPS 2
169	*/
170	#define MX51_AIPS2_BASE_ADDR 0x83F00000
171	#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
172	#define MX51_AIPS2_SIZE SZ_1M
173
174	#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
175	#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
176	#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
177	#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
178	#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
179	#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
180	#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
181	#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
182	#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
183	#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
184	#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
185	#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
186	#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
187	#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
188	#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
189	#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
190	#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
191	#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
192	#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
193	#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
194	#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
195	#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
196	#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
197	#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
198	#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
199	#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
200	#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
201	#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
202	#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
203	#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
204	#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
205	#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
206
207	/*
208	* Memory regions and CS
209	*/
210	#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
211	#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
212	#define MX51_CSD0_BASE_ADDR 0x90000000
213	#define MX51_CSD1_BASE_ADDR 0xA0000000
214	#define MX51_CS0_BASE_ADDR 0xB0000000
215	#define MX51_CS1_BASE_ADDR 0xB8000000
216	#define MX51_CS2_BASE_ADDR 0xC0000000
217	#define MX51_CS3_BASE_ADDR 0xC8000000
218	#define MX51_CS4_BASE_ADDR 0xCC000000
219	#define MX51_CS5_BASE_ADDR 0xCE000000
220
221	/* Does given address belongs to the specified memory region? */
222	#define ADDRESS_IN_REGION(addr, start, size) \
223	(((addr) >= (start)) && ((addr) < (start)+(size)))
224
225	/* Does given address belongs to the specified named `module'? */
226	#define MX51_IS_MODULE(addr, module) \
227	ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
228	MX51_ ## module ## _SIZE)
229	/*
230	* This macro defines the physical to virtual address mapping for all the
231	* peripheral modules. It is used by passing in the physical address as x
232	* and returning the virtual address. If the physical address is not mapped,
233	* it returns 0xDEADBEEF
234	*/
235
236	#define MX51_IO_ADDRESS(x) \
237	(void __iomem *) \
238	(MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
a329b48c AK	239	MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
	240	MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
	241	MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
fc300206	242	MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
a329b48c AK	243	0xDEADBEEF)
	244
	245	/*
	246	* define the address mapping macros: in physical address order
	247	*/
	248	#define MX51_IRAM_IO_ADDRESS(x) \
	249	(((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
	250
a329b48c AK	251	#define MX51_DEBUG_IO_ADDRESS(x) \
	252	(((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
	253
	254	#define MX51_SPBA0_IO_ADDRESS(x) \
	255	(((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
	256
	257	#define MX51_AIPS1_IO_ADDRESS(x) \
	258	(((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
	259
	260	#define MX51_AIPS2_IO_ADDRESS(x) \
	261	(((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
	262
a329b48c AK	263	#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
	264
	265	/*
	266	* DMA request assignments
	267	*/
	268	#define MX51_DMA_REQ_SSI3_TX1 47
	269	#define MX51_DMA_REQ_SSI3_RX1 46
	270	#define MX51_DMA_REQ_SPDIF 45
	271	#define MX51_DMA_REQ_UART3_TX 44
	272	#define MX51_DMA_REQ_UART3_RX 43
	273	#define MX51_DMA_REQ_SLIM_B_TX 42
	274	#define MX51_DMA_REQ_SDHC4 41
	275	#define MX51_DMA_REQ_SDHC3 40
	276	#define MX51_DMA_REQ_CSPI_TX 39
	277	#define MX51_DMA_REQ_CSPI_RX 38
	278	#define MX51_DMA_REQ_SSI3_TX2 37
	279	#define MX51_DMA_REQ_IPU 36
	280	#define MX51_DMA_REQ_SSI3_RX2 35
	281	#define MX51_DMA_REQ_EPIT2 34
	282	#define MX51_DMA_REQ_CTI2_1 33
	283	#define MX51_DMA_REQ_EMI_WR 32
	284	#define MX51_DMA_REQ_CTI2_0 31
	285	#define MX51_DMA_REQ_EMI_RD 30
	286	#define MX51_DMA_REQ_SSI1_TX1 29
	287	#define MX51_DMA_REQ_SSI1_RX1 28
	288	#define MX51_DMA_REQ_SSI1_TX2 27
	289	#define MX51_DMA_REQ_SSI1_RX2 26
	290	#define MX51_DMA_REQ_SSI2_TX1 25
	291	#define MX51_DMA_REQ_SSI2_RX1 24
	292	#define MX51_DMA_REQ_SSI2_TX2 23
	293	#define MX51_DMA_REQ_SSI2_RX2 22
	294	#define MX51_DMA_REQ_SDHC2 21
	295	#define MX51_DMA_REQ_SDHC1 20
	296	#define MX51_DMA_REQ_UART1_TX 19
	297	#define MX51_DMA_REQ_UART1_RX 18
	298	#define MX51_DMA_REQ_UART2_TX 17
	299	#define MX51_DMA_REQ_UART2_RX 16
	300	#define MX51_DMA_REQ_GPU 15
	301	#define MX51_DMA_REQ_EXTREQ1 14
	302	#define MX51_DMA_REQ_FIRI_TX 13
	303	#define MX51_DMA_REQ_FIRI_RX 12
	304	#define MX51_DMA_REQ_HS_I2C_RX 11
	305	#define MX51_DMA_REQ_HS_I2C_TX 10
	306	#define MX51_DMA_REQ_CSPI2_TX 9
	307	#define MX51_DMA_REQ_CSPI2_RX 8
	308	#define MX51_DMA_REQ_CSPI1_TX 7
	309	#define MX51_DMA_REQ_CSPI1_RX 6
	310	#define MX51_DMA_REQ_SLIM_B 5
	311	#define MX51_DMA_REQ_ATA_TX_END 4
	312	#define MX51_DMA_REQ_ATA_TX 3
	313	#define MX51_DMA_REQ_ATA_RX 2
	314	#define MX51_DMA_REQ_GPC 1
	315	#define MX51_DMA_REQ_VPU 0
	316
	317	/*
	318	* Interrupt numbers
	319	*/
	320	#define MX51_MXC_INT_BASE 0
	321	#define MX51_MXC_INT_RESV0 0
	322	#define MX51_MXC_INT_MMC_SDHC1 1
	323	#define MX51_MXC_INT_MMC_SDHC2 2
	324	#define MX51_MXC_INT_MMC_SDHC3 3
	325	#define MX51_MXC_INT_MMC_SDHC4 4
	326	#define MX51_MXC_INT_RESV5 5
327	#define MX51_MXC_INT_SDMA 6
328	#define MX51_MXC_INT_IOMUX 7
329	#define MX51_MXC_INT_NFC 8
330	#define MX51_MXC_INT_VPU 9
331	#define MX51_MXC_INT_IPU_ERR 10
332	#define MX51_MXC_INT_IPU_SYN 11
333	#define MX51_MXC_INT_GPU 12
334	#define MX51_MXC_INT_RESV13 13
335	#define MX51_MXC_INT_USB_H1 14
336	#define MX51_MXC_INT_EMI 15
337	#define MX51_MXC_INT_USB_H2 16
338	#define MX51_MXC_INT_USB_H3 17
339	#define MX51_MXC_INT_USB_OTG 18
340	#define MX51_MXC_INT_SAHARA_H0 19
341	#define MX51_MXC_INT_SAHARA_H1 20
342	#define MX51_MXC_INT_SCC_SMN 21
343	#define MX51_MXC_INT_SCC_STZ 22
344	#define MX51_MXC_INT_SCC_SCM 23
345	#define MX51_MXC_INT_SRTC_NTZ 24
346	#define MX51_MXC_INT_SRTC_TZ 25
347	#define MX51_MXC_INT_RTIC 26
348	#define MX51_MXC_INT_CSU 27
349	#define MX51_MXC_INT_SLIM_B 28
350	#define MX51_MXC_INT_SSI1 29
351	#define MX51_MXC_INT_SSI2 30
352	#define MX51_MXC_INT_UART1 31
353	#define MX51_MXC_INT_UART2 32
354	#define MX51_MXC_INT_UART3 33
355	#define MX51_MXC_INT_RESV34 34
356	#define MX51_MXC_INT_RESV35 35
357	#define MX51_MXC_INT_CSPI1 36
358	#define MX51_MXC_INT_CSPI2 37
359	#define MX51_MXC_INT_CSPI 38
360	#define MX51_MXC_INT_GPT 39
361	#define MX51_MXC_INT_EPIT1 40
362	#define MX51_MXC_INT_EPIT2 41
363	#define MX51_MXC_INT_GPIO1_INT7 42
364	#define MX51_MXC_INT_GPIO1_INT6 43
365	#define MX51_MXC_INT_GPIO1_INT5 44
366	#define MX51_MXC_INT_GPIO1_INT4 45
367	#define MX51_MXC_INT_GPIO1_INT3 46
368	#define MX51_MXC_INT_GPIO1_INT2 47
369	#define MX51_MXC_INT_GPIO1_INT1 48
370	#define MX51_MXC_INT_GPIO1_INT0 49
371	#define MX51_MXC_INT_GPIO1_LOW 50
372	#define MX51_MXC_INT_GPIO1_HIGH 51
373	#define MX51_MXC_INT_GPIO2_LOW 52
374	#define MX51_MXC_INT_GPIO2_HIGH 53
375	#define MX51_MXC_INT_GPIO3_LOW 54
376	#define MX51_MXC_INT_GPIO3_HIGH 55
377	#define MX51_MXC_INT_GPIO4_LOW 56
378	#define MX51_MXC_INT_GPIO4_HIGH 57
379	#define MX51_MXC_INT_WDOG1 58
380	#define MX51_MXC_INT_WDOG2 59
381	#define MX51_MXC_INT_KPP 60
382	#define MX51_MXC_INT_PWM1 61
383	#define MX51_MXC_INT_I2C1 62
384	#define MX51_MXC_INT_I2C2 63
385	#define MX51_MXC_INT_HS_I2C 64
386	#define MX51_MXC_INT_RESV65 65
387	#define MX51_MXC_INT_RESV66 66
388	#define MX51_MXC_INT_SIM_IPB 67
389	#define MX51_MXC_INT_SIM_DAT 68
390	#define MX51_MXC_INT_IIM 69
391	#define MX51_MXC_INT_ATA 70
392	#define MX51_MXC_INT_CCM1 71
393	#define MX51_MXC_INT_CCM2 72
394	#define MX51_MXC_INT_GPC1 73
395	#define MX51_MXC_INT_GPC2 74
396	#define MX51_MXC_INT_SRC 75
397	#define MX51_MXC_INT_NM 76
398	#define MX51_MXC_INT_PMU 77
399	#define MX51_MXC_INT_CTI_IRQ 78
400	#define MX51_MXC_INT_CTI1_TG0 79
401	#define MX51_MXC_INT_CTI1_TG1 80
402	#define MX51_MXC_INT_MCG_ERR 81
403	#define MX51_MXC_INT_MCG_TMR 82
404	#define MX51_MXC_INT_MCG_FUNC 83
405	#define MX51_MXC_INT_GPU2_IRQ 84
406	#define MX51_MXC_INT_GPU2_BUSY 85
407	#define MX51_MXC_INT_RESV86 86
408	#define MX51_MXC_INT_FEC 87
409	#define MX51_MXC_INT_OWIRE 88
410	#define MX51_MXC_INT_CTI1_TG2 89
411	#define MX51_MXC_INT_SJC 90
412	#define MX51_MXC_INT_SPDIF 91
413	#define MX51_MXC_INT_TVE 92
414	#define MX51_MXC_INT_FIRI 93
415	#define MX51_MXC_INT_PWM2 94
416	#define MX51_MXC_INT_SLIM_EXP 95
417	#define MX51_MXC_INT_SSI3 96
418	#define MX51_MXC_INT_EMI_BOOT 97
419	#define MX51_MXC_INT_CTI1_TG3 98
420	#define MX51_MXC_INT_SMC_RX 99
421	#define MX51_MXC_INT_VPU_IDLE 100
422	#define MX51_MXC_INT_EMI_NFC 101
423	#define MX51_MXC_INT_GPU_IDLE 102
424
425	/* silicon revisions specific to i.MX51 */
426	#define MX51_CHIP_REV_1_0 0x10
427	#define MX51_CHIP_REV_1_1 0x11
428	#define MX51_CHIP_REV_1_2 0x12
429	#define MX51_CHIP_REV_1_3 0x13
430	#define MX51_CHIP_REV_2_0 0x20
431	#define MX51_CHIP_REV_2_1 0x21
432	#define MX51_CHIP_REV_2_2 0x22
433	#define MX51_CHIP_REV_2_3 0x23
434	#define MX51_CHIP_REV_3_0 0x30
435	#define MX51_CHIP_REV_3_1 0x31
436	#define MX51_CHIP_REV_3_2 0x32
437
438	/* Mandatory defines used globally */
439
440	#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
441
5443856c	442	extern int mx51_revision(void);
a329b48c AK	443	#endif
	444
	445	#endif /* __ASM_ARCH_MXC_MX51_H__ */