[deliverable/linux.git] / arch / arm / plat-mxc / include / mach / mxc.h

/*
 * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#ifndef __ASM_ARCH_MXC_H__
#define __ASM_ARCH_MXC_H__

#include <linux/types.h>

#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif

#define MXC_CPU_MX1		1
#define MXC_CPU_MX21		21
#define MXC_CPU_MX25		25
#define MXC_CPU_MX27		27
#define MXC_CPU_MX31		31
#define MXC_CPU_MX35		35
#define MXC_CPU_MX50		50
#define MXC_CPU_MX51		51
#define MXC_CPU_MX53		53

#define IMX_CHIP_REVISION_1_0		0x10
#define IMX_CHIP_REVISION_1_1		0x11
#define IMX_CHIP_REVISION_1_2		0x12
#define IMX_CHIP_REVISION_1_3		0x13
#define IMX_CHIP_REVISION_2_0		0x20
#define IMX_CHIP_REVISION_2_1		0x21
#define IMX_CHIP_REVISION_2_2		0x22
#define IMX_CHIP_REVISION_2_3		0x23
#define IMX_CHIP_REVISION_3_0		0x30
#define IMX_CHIP_REVISION_3_1		0x31
#define IMX_CHIP_REVISION_3_2		0x32
#define IMX_CHIP_REVISION_3_3		0x33
#define IMX_CHIP_REVISION_UNKNOWN	0xff

#define IMX_CHIP_REVISION_1_0_STRING		"1.0"
#define IMX_CHIP_REVISION_1_1_STRING		"1.1"
#define IMX_CHIP_REVISION_1_2_STRING		"1.2"
#define IMX_CHIP_REVISION_1_3_STRING		"1.3"
#define IMX_CHIP_REVISION_2_0_STRING		"2.0"
#define IMX_CHIP_REVISION_2_1_STRING		"2.1"
#define IMX_CHIP_REVISION_2_2_STRING		"2.2"
#define IMX_CHIP_REVISION_2_3_STRING		"2.3"
#define IMX_CHIP_REVISION_3_0_STRING		"3.0"
#define IMX_CHIP_REVISION_3_1_STRING		"3.1"
#define IMX_CHIP_REVISION_3_2_STRING		"3.2"
#define IMX_CHIP_REVISION_3_3_STRING		"3.3"
#define IMX_CHIP_REVISION_UNKNOWN_STRING	"unknown"

#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;
#endif

#ifdef CONFIG_ARCH_MX1
# ifdef mxc_cpu_type
#  undef mxc_cpu_type
#  define mxc_cpu_type __mxc_cpu_type
# else
#  define mxc_cpu_type MXC_CPU_MX1
# endif
# define cpu_is_mx1()		(mxc_cpu_type == MXC_CPU_MX1)
#else
# define cpu_is_mx1()		(0)
#endif

#ifdef CONFIG_MACH_MX21
# ifdef mxc_cpu_type
#  undef mxc_cpu_type
#  define mxc_cpu_type __mxc_cpu_type
# else
#  define mxc_cpu_type MXC_CPU_MX21
# endif
# define cpu_is_mx21()		(mxc_cpu_type == MXC_CPU_MX21)
#else
# define cpu_is_mx21()		(0)
#endif

#ifdef CONFIG_ARCH_MX25
# ifdef mxc_cpu_type
#  undef mxc_cpu_type
#  define mxc_cpu_type __mxc_cpu_type
# else
#  define mxc_cpu_type MXC_CPU_MX25
# endif
# define cpu_is_mx25()		(mxc_cpu_type == MXC_CPU_MX25)
#else
# define cpu_is_mx25()		(0)
#endif

#ifdef CONFIG_MACH_MX27
# ifdef mxc_cpu_type
#  undef mxc_cpu_type
#  define mxc_cpu_type __mxc_cpu_type
# else
#  define mxc_cpu_type MXC_CPU_MX27
# endif
# define cpu_is_mx27()		(mxc_cpu_type == MXC_CPU_MX27)
#else
# define cpu_is_mx27()		(0)
#endif

#ifdef CONFIG_SOC_IMX31
# ifdef mxc_cpu_type
#  undef mxc_cpu_type
#  define mxc_cpu_type __mxc_cpu_type
# else
#  define mxc_cpu_type MXC_CPU_MX31
# endif
# define cpu_is_mx31()		(mxc_cpu_type == MXC_CPU_MX31)
#else
# define cpu_is_mx31()		(0)
#endif

#ifdef CONFIG_SOC_IMX35
# ifdef mxc_cpu_type
#  undef mxc_cpu_type
#  define mxc_cpu_type __mxc_cpu_type
# else
#  define mxc_cpu_type MXC_CPU_MX35
# endif
# define cpu_is_mx35()		(mxc_cpu_type == MXC_CPU_MX35)
#else
# define cpu_is_mx35()		(0)
#endif

#ifdef CONFIG_SOC_IMX50
# ifdef mxc_cpu_type
#  undef mxc_cpu_type
#  define mxc_cpu_type __mxc_cpu_type
# else
#  define mxc_cpu_type MXC_CPU_MX50
# endif
# define cpu_is_mx50()		(mxc_cpu_type == MXC_CPU_MX50)
#else
# define cpu_is_mx50()		(0)
#endif

#ifdef CONFIG_SOC_IMX51
# ifdef mxc_cpu_type
#  undef mxc_cpu_type
#  define mxc_cpu_type __mxc_cpu_type
# else
#  define mxc_cpu_type MXC_CPU_MX51
# endif
# define cpu_is_mx51()		(mxc_cpu_type == MXC_CPU_MX51)
#else
# define cpu_is_mx51()		(0)
#endif

#ifdef CONFIG_SOC_IMX53
# ifdef mxc_cpu_type
#  undef mxc_cpu_type
#  define mxc_cpu_type __mxc_cpu_type
# else
#  define mxc_cpu_type MXC_CPU_MX53
# endif
# define cpu_is_mx53()		(mxc_cpu_type == MXC_CPU_MX53)
#else
# define cpu_is_mx53()		(0)
#endif

#ifndef __ASSEMBLY__

struct cpu_op {
	u32 cpu_rate;
};

int tzic_enable_wake(int is_idle);
enum mxc_cpu_pwr_mode {
	WAIT_CLOCKED,		/* wfi only */
	WAIT_UNCLOCKED,		/* WAIT */
	WAIT_UNCLOCKED_POWER_OFF,	/* WAIT + SRPG */
	STOP_POWER_ON,		/* just STOP */
	STOP_POWER_OFF,		/* STOP + SRPG */
};

extern struct cpu_op *(*get_cpu_op)(int *op);
#endif

#define cpu_is_mx3()	(cpu_is_mx31() || cpu_is_mx35())
#define cpu_is_mx2()	(cpu_is_mx21() || cpu_is_mx27())

#endif /*  __ASM_ARCH_MXC_H__ */
Commit	Line	Data
52c543f9	1	/*
64f102b6	2	* Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
d0f349fb JB	3	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	* MA 02110-1301, USA.
52c543f9 QJ	18	*/
	19
	20	#ifndef __ASM_ARCH_MXC_H__
	21	#define __ASM_ARCH_MXC_H__
	22
64f102b6 YS	23	#include <linux/types.h>
64f102b6 YS	24
52c543f9 QJ	25	#ifndef __ASM_ARCH_MXC_HARDWARE_H__
	26	#error "Do not include directly."
	27	#endif
	28
198016e1 SH	29	#define MXC_CPU_MX1 1
198016e1 SH	30	#define MXC_CPU_MX21 21
8c25c36f	31	#define MXC_CPU_MX25 25
198016e1 SH	32	#define MXC_CPU_MX27 27
	33	#define MXC_CPU_MX31 31
	34	#define MXC_CPU_MX35 35
3d5a44be	35	#define MXC_CPU_MX50 50
438caa3f	36	#define MXC_CPU_MX51 51
c0abefd3	37	#define MXC_CPU_MX53 53
198016e1	38
9ab4650f DN	39	#define IMX_CHIP_REVISION_1_0 0x10
	40	#define IMX_CHIP_REVISION_1_1 0x11
	41	#define IMX_CHIP_REVISION_1_2 0x12
	42	#define IMX_CHIP_REVISION_1_3 0x13
	43	#define IMX_CHIP_REVISION_2_0 0x20
	44	#define IMX_CHIP_REVISION_2_1 0x21
	45	#define IMX_CHIP_REVISION_2_2 0x22
	46	#define IMX_CHIP_REVISION_2_3 0x23
	47	#define IMX_CHIP_REVISION_3_0 0x30
	48	#define IMX_CHIP_REVISION_3_1 0x31
	49	#define IMX_CHIP_REVISION_3_2 0x32
	50	#define IMX_CHIP_REVISION_3_3 0x33
	51	#define IMX_CHIP_REVISION_UNKNOWN 0xff
	52
76422dbf FE	53	#define IMX_CHIP_REVISION_1_0_STRING "1.0"
	54	#define IMX_CHIP_REVISION_1_1_STRING "1.1"
	55	#define IMX_CHIP_REVISION_1_2_STRING "1.2"
	56	#define IMX_CHIP_REVISION_1_3_STRING "1.3"
	57	#define IMX_CHIP_REVISION_2_0_STRING "2.0"
	58	#define IMX_CHIP_REVISION_2_1_STRING "2.1"
	59	#define IMX_CHIP_REVISION_2_2_STRING "2.2"
	60	#define IMX_CHIP_REVISION_2_3_STRING "2.3"
	61	#define IMX_CHIP_REVISION_3_0_STRING "3.0"
	62	#define IMX_CHIP_REVISION_3_1_STRING "3.1"
	63	#define IMX_CHIP_REVISION_3_2_STRING "3.2"
	64	#define IMX_CHIP_REVISION_3_3_STRING "3.3"
	65	#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown"
	66
198016e1 SH	67	#ifndef __ASSEMBLY__
	68	extern unsigned int __mxc_cpu_type;
	69	#endif
	70
	71	#ifdef CONFIG_ARCH_MX1
	72	# ifdef mxc_cpu_type
	73	# undef mxc_cpu_type
	74	# define mxc_cpu_type __mxc_cpu_type
	75	# else
	76	# define mxc_cpu_type MXC_CPU_MX1
	77	# endif
	78	# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
	79	#else
	80	# define cpu_is_mx1() (0)
d2db9aaa RS	81	#endif
d2db9aaa RS	82
198016e1 SH	83	#ifdef CONFIG_MACH_MX21
	84	# ifdef mxc_cpu_type
	85	# undef mxc_cpu_type
	86	# define mxc_cpu_type __mxc_cpu_type
	87	# else
	88	# define mxc_cpu_type MXC_CPU_MX21
	89	# endif
	90	# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
	91	#else
	92	# define cpu_is_mx21() (0)
5512e88f HS	93	#endif
5512e88f HS	94
8c25c36f SH	95	#ifdef CONFIG_ARCH_MX25
	96	# ifdef mxc_cpu_type
	97	# undef mxc_cpu_type
	98	# define mxc_cpu_type __mxc_cpu_type
	99	# else
	100	# define mxc_cpu_type MXC_CPU_MX25
	101	# endif
	102	# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
	103	#else
	104	# define cpu_is_mx25() (0)
	105	#endif
	106
198016e1 SH	107	#ifdef CONFIG_MACH_MX27
	108	# ifdef mxc_cpu_type
	109	# undef mxc_cpu_type
	110	# define mxc_cpu_type __mxc_cpu_type
	111	# else
	112	# define mxc_cpu_type MXC_CPU_MX27
	113	# endif
	114	# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
	115	#else
	116	# define cpu_is_mx27() (0)
f31405cc JB	117	#endif
f31405cc JB	118
c23eb89e	119	#ifdef CONFIG_SOC_IMX31
198016e1 SH	120	# ifdef mxc_cpu_type
	121	# undef mxc_cpu_type
	122	# define mxc_cpu_type __mxc_cpu_type
	123	# else
	124	# define mxc_cpu_type MXC_CPU_MX31
	125	# endif
	126	# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
	127	#else
	128	# define cpu_is_mx31() (0)
	129	#endif
	130
c23eb89e	131	#ifdef CONFIG_SOC_IMX35
198016e1 SH	132	# ifdef mxc_cpu_type
	133	# undef mxc_cpu_type
	134	# define mxc_cpu_type __mxc_cpu_type
	135	# else
	136	# define mxc_cpu_type MXC_CPU_MX35
	137	# endif
	138	# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
	139	#else
	140	# define cpu_is_mx35() (0)
260a1fd2 HS	141	#endif
260a1fd2 HS	142
76851671	143	#ifdef CONFIG_SOC_IMX50
3d5a44be RZ	144	# ifdef mxc_cpu_type
	145	# undef mxc_cpu_type
	146	# define mxc_cpu_type __mxc_cpu_type
	147	# else
	148	# define mxc_cpu_type MXC_CPU_MX50
	149	# endif
	150	# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
	151	#else
	152	# define cpu_is_mx50() (0)
	153	#endif
	154
76851671	155	#ifdef CONFIG_SOC_IMX51
438caa3f AK	156	# ifdef mxc_cpu_type
	157	# undef mxc_cpu_type
	158	# define mxc_cpu_type __mxc_cpu_type
	159	# else
	160	# define mxc_cpu_type MXC_CPU_MX51
	161	# endif
	162	# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
	163	#else
	164	# define cpu_is_mx51() (0)
	165	#endif
	166
76851671	167	#ifdef CONFIG_SOC_IMX53
02226a20 RZ	168	# ifdef mxc_cpu_type
	169	# undef mxc_cpu_type
	170	# define mxc_cpu_type __mxc_cpu_type
	171	# else
	172	# define mxc_cpu_type MXC_CPU_MX53
	173	# endif
	174	# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
	175	#else
	176	# define cpu_is_mx53() (0)
	177	#endif
	178
64f102b6 YS	179	#ifndef __ASSEMBLY__
	180
	181	struct cpu_op {
	182	u32 cpu_rate;
	183	};
	184
0adf882b DN	185	int tzic_enable_wake(int is_idle);
	186	enum mxc_cpu_pwr_mode {
	187	WAIT_CLOCKED, /* wfi only */
	188	WAIT_UNCLOCKED, /* WAIT */
	189	WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
	190	STOP_POWER_ON, /* just STOP */
	191	STOP_POWER_OFF, /* STOP + SRPG */
	192	};
	193
64f102b6 YS	194	extern struct cpu_op (get_cpu_op)(int *op);
	195	#endif
	196
13cf8df9	197	#define cpu_is_mx3() (cpu_is_mx31() \|\| cpu_is_mx35())
198016e1 SH	198	#define cpu_is_mx2() (cpu_is_mx21() \|\| cpu_is_mx27())
198016e1 SH	199
f304fc42	200	#endif /* __ASM_ARCH_MXC_H__ */