Commit | Line | Data |
---|---|---|
52c543f9 | 1 | /* |
a09e64fb | 2 | * arch/arm/plat-mxc/include/mach/uncompress.h |
52c543f9 | 3 | * |
52c543f9 QJ |
4 | * Copyright (C) 1999 ARM Limited |
5 | * Copyright (C) Shane Nay (shane@minirl.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
52c543f9 QJ |
16 | */ |
17 | #ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ | |
18 | #define __ASM_ARCH_MXC_UNCOMPRESS_H__ | |
19 | ||
20 | #define __MXC_BOOT_UNCOMPRESS | |
21 | ||
d30c74a0 | 22 | #include <asm/mach-types.h> |
52c543f9 | 23 | |
d30c74a0 SH |
24 | static unsigned long uart_base; |
25 | ||
26 | #define UART(x) (*(volatile unsigned long *)(uart_base + (x))) | |
52c543f9 QJ |
27 | |
28 | #define USR2 0x98 | |
29 | #define USR2_TXFE (1<<14) | |
30 | #define TXR 0x40 | |
31 | #define UCR1 0x80 | |
32 | #define UCR1_UARTEN 1 | |
33 | ||
34 | /* | |
35 | * The following code assumes the serial port has already been | |
36 | * initialized by the bootloader. We search for the first enabled | |
37 | * port in the most probable order. If you didn't setup a port in | |
38 | * your bootloader then nothing will appear (which might be desired). | |
39 | * | |
40 | * This does not append a newline | |
41 | */ | |
42 | ||
43 | static void putc(int ch) | |
44 | { | |
d30c74a0 SH |
45 | if (!uart_base) |
46 | return; | |
47 | if (!(UART(UCR1) & UCR1_UARTEN)) | |
48 | return; | |
52c543f9 QJ |
49 | |
50 | while (!(UART(USR2) & USR2_TXFE)) | |
03e5386e | 51 | barrier(); |
52c543f9 QJ |
52 | |
53 | UART(TXR) = ch; | |
54 | } | |
55 | ||
b53e9b5e TL |
56 | static inline void flush(void) |
57 | { | |
58 | } | |
52c543f9 | 59 | |
d30c74a0 | 60 | #define MX1_UART1_BASE_ADDR 0x00206000 |
8c25c36f | 61 | #define MX25_UART1_BASE_ADDR 0x43f90000 |
d30c74a0 SH |
62 | #define MX2X_UART1_BASE_ADDR 0x1000a000 |
63 | #define MX3X_UART1_BASE_ADDR 0x43F90000 | |
fd6ac7bb | 64 | #define MX3X_UART2_BASE_ADDR 0x43F94000 |
48fae657 | 65 | #define MX51_UART1_BASE_ADDR 0x73fbc000 |
d3d4b60b | 66 | #define MX50_UART1_BASE_ADDR 0x53fbc000 |
d30c74a0 SH |
67 | |
68 | static __inline__ void __arch_decomp_setup(unsigned long arch_id) | |
69 | { | |
70 | switch (arch_id) { | |
71 | case MACH_TYPE_MX1ADS: | |
72 | case MACH_TYPE_SCB9328: | |
73 | uart_base = MX1_UART1_BASE_ADDR; | |
74 | break; | |
635baf6b SH |
75 | case MACH_TYPE_MX25_3DS: |
76 | uart_base = MX25_UART1_BASE_ADDR; | |
77 | break; | |
d30c74a0 SH |
78 | case MACH_TYPE_IMX27LITE: |
79 | case MACH_TYPE_MX27_3DS: | |
80 | case MACH_TYPE_MX27ADS: | |
81 | case MACH_TYPE_PCM038: | |
82 | case MACH_TYPE_MX21ADS: | |
34499a7c | 83 | case MACH_TYPE_PCA100: |
143a179d | 84 | case MACH_TYPE_MXT_TD60: |
d30c74a0 SH |
85 | uart_base = MX2X_UART1_BASE_ADDR; |
86 | break; | |
87 | case MACH_TYPE_MX31LITE: | |
88 | case MACH_TYPE_ARMADILLO5X0: | |
89 | case MACH_TYPE_MX31MOBOARD: | |
90 | case MACH_TYPE_QONG: | |
91 | case MACH_TYPE_MX31_3DS: | |
92 | case MACH_TYPE_PCM037: | |
93 | case MACH_TYPE_MX31ADS: | |
94 | case MACH_TYPE_MX35_3DS: | |
95 | case MACH_TYPE_PCM043: | |
115b40c3 | 96 | case MACH_TYPE_LILLY1131: |
d30c74a0 SH |
97 | uart_base = MX3X_UART1_BASE_ADDR; |
98 | break; | |
fd6ac7bb DT |
99 | case MACH_TYPE_MAGX_ZN5: |
100 | uart_base = MX3X_UART2_BASE_ADDR; | |
101 | break; | |
48fae657 | 102 | case MACH_TYPE_MX51_BABBAGE: |
70b17268 | 103 | case MACH_TYPE_EUKREA_CPUIMX51SD: |
48fae657 SH |
104 | uart_base = MX51_UART1_BASE_ADDR; |
105 | break; | |
d3d4b60b RZ |
106 | case MACH_TYPE_MX50_RDP: |
107 | uart_base = MX50_UART1_BASE_ADDR; | |
108 | break; | |
d30c74a0 SH |
109 | default: |
110 | break; | |
111 | } | |
112 | } | |
52c543f9 | 113 | |
d30c74a0 | 114 | #define arch_decomp_setup() __arch_decomp_setup(arch_id) |
52c543f9 QJ |
115 | #define arch_decomp_wdog() |
116 | ||
117 | #endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */ |