[deliverable/linux.git] / arch / arm / plat-mxc / include / mach / uncompress.h

/*
 *  arch/arm/plat-mxc/include/mach/uncompress.h
 *
 *  Copyright (C) 1999 ARM Limited
 *  Copyright (C) Shane Nay (shane@minirl.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
#define __ASM_ARCH_MXC_UNCOMPRESS_H__

#define __MXC_BOOT_UNCOMPRESS

#include <asm/mach-types.h>

static unsigned long uart_base;

#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))

#define USR2 0x98
#define USR2_TXFE (1<<14)
#define TXR  0x40
#define UCR1 0x80
#define UCR1_UARTEN 1

/*
 * The following code assumes the serial port has already been
 * initialized by the bootloader.  We search for the first enabled
 * port in the most probable order.  If you didn't setup a port in
 * your bootloader then nothing will appear (which might be desired).
 *
 * This does not append a newline
 */

static void putc(int ch)
{
	if (!uart_base)
		return;
	if (!(UART(UCR1) & UCR1_UARTEN))
		return;

	while (!(UART(USR2) & USR2_TXFE))
		barrier();

	UART(TXR) = ch;
}

static inline void flush(void)
{
}

#define MX1_UART1_BASE_ADDR	0x00206000
#define MX25_UART1_BASE_ADDR	0x43f90000
#define MX2X_UART1_BASE_ADDR	0x1000a000
#define MX3X_UART1_BASE_ADDR	0x43F90000
#define MX3X_UART2_BASE_ADDR	0x43F94000
#define MX51_UART1_BASE_ADDR	0x73fbc000
#define MX50_UART1_BASE_ADDR	0x53fbc000
#define MX53_UART1_BASE_ADDR	0x53fbc000

static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
	switch (arch_id) {
	case MACH_TYPE_MX1ADS:
	case MACH_TYPE_SCB9328:
		uart_base = MX1_UART1_BASE_ADDR;
		break;
	case MACH_TYPE_MX25_3DS:
		uart_base = MX25_UART1_BASE_ADDR;
		break;
	case MACH_TYPE_IMX27LITE:
	case MACH_TYPE_MX27_3DS:
	case MACH_TYPE_MX27ADS:
	case MACH_TYPE_PCM038:
	case MACH_TYPE_MX21ADS:
	case MACH_TYPE_PCA100:
	case MACH_TYPE_MXT_TD60:
	case MACH_TYPE_IMX27IPCAM:
		uart_base = MX2X_UART1_BASE_ADDR;
		break;
	case MACH_TYPE_MX31LITE:
	case MACH_TYPE_ARMADILLO5X0:
	case MACH_TYPE_MX31MOBOARD:
	case MACH_TYPE_QONG:
	case MACH_TYPE_MX31_3DS:
	case MACH_TYPE_PCM037:
	case MACH_TYPE_MX31ADS:
	case MACH_TYPE_MX35_3DS:
	case MACH_TYPE_PCM043:
	case MACH_TYPE_LILLY1131:
		uart_base = MX3X_UART1_BASE_ADDR;
		break;
	case MACH_TYPE_MAGX_ZN5:
		uart_base = MX3X_UART2_BASE_ADDR;
		break;
	case MACH_TYPE_MX51_BABBAGE:
	case MACH_TYPE_EUKREA_CPUIMX51SD:
		uart_base = MX51_UART1_BASE_ADDR;
		break;
	case MACH_TYPE_MX50_RDP:
		uart_base = MX50_UART1_BASE_ADDR;
		break;
	case MACH_TYPE_MX53_EVK:
		uart_base = MX53_UART1_BASE_ADDR;
		break;
	default:
		break;
	}
}

#define arch_decomp_setup()	__arch_decomp_setup(arch_id)
#define arch_decomp_wdog()

#endif				/* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
Commit	Line	Data
52c543f9	1	/*
a09e64fb	2	* arch/arm/plat-mxc/include/mach/uncompress.h
52c543f9	3	*
52c543f9 QJ	4	* Copyright (C) 1999 ARM Limited
	5	* Copyright (C) Shane Nay (shane@minirl.com)
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
52c543f9 QJ	16	*/
	17	#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
	18	#define __ASM_ARCH_MXC_UNCOMPRESS_H__
	19
	20	#define __MXC_BOOT_UNCOMPRESS
	21
d30c74a0	22	#include <asm/mach-types.h>
52c543f9	23
d30c74a0 SH	24	static unsigned long uart_base;
	25
	26	#define UART(x) ((volatile unsigned long )(uart_base + (x)))
52c543f9 QJ	27
	28	#define USR2 0x98
	29	#define USR2_TXFE (1<<14)
	30	#define TXR 0x40
	31	#define UCR1 0x80
	32	#define UCR1_UARTEN 1
	33
	34	/*
	35	* The following code assumes the serial port has already been
	36	* initialized by the bootloader. We search for the first enabled
	37	* port in the most probable order. If you didn't setup a port in
	38	* your bootloader then nothing will appear (which might be desired).
	39	*
	40	* This does not append a newline
	41	*/
	42
	43	static void putc(int ch)
	44	{
d30c74a0 SH	45	if (!uart_base)
	46	return;
	47	if (!(UART(UCR1) & UCR1_UARTEN))
	48	return;
52c543f9 QJ	49
52c543f9 QJ	50	while (!(UART(USR2) & USR2_TXFE))
03e5386e	51	barrier();
52c543f9 QJ	52
	53	UART(TXR) = ch;
	54	}
	55
b53e9b5e TL	56	static inline void flush(void)
	57	{
	58	}
52c543f9	59
d30c74a0	60	#define MX1_UART1_BASE_ADDR 0x00206000
8c25c36f	61	#define MX25_UART1_BASE_ADDR 0x43f90000
d30c74a0 SH	62	#define MX2X_UART1_BASE_ADDR 0x1000a000
d30c74a0 SH	63	#define MX3X_UART1_BASE_ADDR 0x43F90000
fd6ac7bb	64	#define MX3X_UART2_BASE_ADDR 0x43F94000
48fae657	65	#define MX51_UART1_BASE_ADDR 0x73fbc000
d3d4b60b	66	#define MX50_UART1_BASE_ADDR 0x53fbc000
a58154d1	67	#define MX53_UART1_BASE_ADDR 0x53fbc000
d30c74a0 SH	68
	69	static __inline__ void __arch_decomp_setup(unsigned long arch_id)
	70	{
	71	switch (arch_id) {
	72	case MACH_TYPE_MX1ADS:
	73	case MACH_TYPE_SCB9328:
	74	uart_base = MX1_UART1_BASE_ADDR;
	75	break;
635baf6b SH	76	case MACH_TYPE_MX25_3DS:
	77	uart_base = MX25_UART1_BASE_ADDR;
	78	break;
d30c74a0 SH	79	case MACH_TYPE_IMX27LITE:
	80	case MACH_TYPE_MX27_3DS:
	81	case MACH_TYPE_MX27ADS:
	82	case MACH_TYPE_PCM038:
	83	case MACH_TYPE_MX21ADS:
34499a7c	84	case MACH_TYPE_PCA100:
143a179d	85	case MACH_TYPE_MXT_TD60:
9c2c3584	86	case MACH_TYPE_IMX27IPCAM:
d30c74a0 SH	87	uart_base = MX2X_UART1_BASE_ADDR;
	88	break;
	89	case MACH_TYPE_MX31LITE:
	90	case MACH_TYPE_ARMADILLO5X0:
	91	case MACH_TYPE_MX31MOBOARD:
	92	case MACH_TYPE_QONG:
	93	case MACH_TYPE_MX31_3DS:
	94	case MACH_TYPE_PCM037:
	95	case MACH_TYPE_MX31ADS:
	96	case MACH_TYPE_MX35_3DS:
	97	case MACH_TYPE_PCM043:
115b40c3	98	case MACH_TYPE_LILLY1131:
d30c74a0 SH	99	uart_base = MX3X_UART1_BASE_ADDR;
d30c74a0 SH	100	break;
fd6ac7bb DT	101	case MACH_TYPE_MAGX_ZN5:
	102	uart_base = MX3X_UART2_BASE_ADDR;
	103	break;
48fae657	104	case MACH_TYPE_MX51_BABBAGE:
70b17268	105	case MACH_TYPE_EUKREA_CPUIMX51SD:
48fae657 SH	106	uart_base = MX51_UART1_BASE_ADDR;
48fae657 SH	107	break;
d3d4b60b RZ	108	case MACH_TYPE_MX50_RDP:
	109	uart_base = MX50_UART1_BASE_ADDR;
	110	break;
a58154d1 YS	111	case MACH_TYPE_MX53_EVK:
	112	uart_base = MX53_UART1_BASE_ADDR;
	113	break;
d30c74a0 SH	114	default:
	115	break;
	116	}
	117	}
52c543f9	118
d30c74a0	119	#define arch_decomp_setup() __arch_decomp_setup(arch_id)
52c543f9 QJ	120	#define arch_decomp_wdog()
	121
	122	#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */