[deliverable/linux.git] / arch / arm / plat-mxc / include / mach / uncompress.h

/*
 *  arch/arm/plat-mxc/include/mach/uncompress.h
 *
 *
 *
 *  Copyright (C) 1999 ARM Limited
 *  Copyright (C) Shane Nay (shane@minirl.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
#define __ASM_ARCH_MXC_UNCOMPRESS_H__

#define __MXC_BOOT_UNCOMPRESS

#include <mach/hardware.h>
#include <asm/mach-types.h>

static unsigned long uart_base;

#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))

#define USR2 0x98
#define USR2_TXFE (1<<14)
#define TXR  0x40
#define UCR1 0x80
#define UCR1_UARTEN 1

/*
 * The following code assumes the serial port has already been
 * initialized by the bootloader.  We search for the first enabled
 * port in the most probable order.  If you didn't setup a port in
 * your bootloader then nothing will appear (which might be desired).
 *
 * This does not append a newline
 */

static void putc(int ch)
{
	if (!uart_base)
		return;
	if (!(UART(UCR1) & UCR1_UARTEN))
		return;

	while (!(UART(USR2) & USR2_TXFE))
		barrier();

	UART(TXR) = ch;
}

#define flush() do { } while (0)

#define MX1_UART1_BASE_ADDR	0x00206000
#define MX25_UART1_BASE_ADDR	0x43f90000
#define MX2X_UART1_BASE_ADDR	0x1000a000
#define MX3X_UART1_BASE_ADDR	0x43F90000
#define MX3X_UART2_BASE_ADDR	0x43F94000

static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
	switch (arch_id) {
	case MACH_TYPE_MX1ADS:
	case MACH_TYPE_SCB9328:
		uart_base = MX1_UART1_BASE_ADDR;
		break;
	case MACH_TYPE_MX25_3DS:
		uart_base = MX25_UART1_BASE_ADDR;
		break;
	case MACH_TYPE_IMX27LITE:
	case MACH_TYPE_MX27_3DS:
	case MACH_TYPE_MX27ADS:
	case MACH_TYPE_PCM038:
	case MACH_TYPE_MX21ADS:
		uart_base = MX2X_UART1_BASE_ADDR;
		break;
	case MACH_TYPE_MX31LITE:
	case MACH_TYPE_ARMADILLO5X0:
	case MACH_TYPE_MX31MOBOARD:
	case MACH_TYPE_QONG:
	case MACH_TYPE_MX31_3DS:
	case MACH_TYPE_PCM037:
	case MACH_TYPE_MX31ADS:
	case MACH_TYPE_MX35_3DS:
	case MACH_TYPE_PCM043:
	case MACH_TYPE_LILLY1131:
		uart_base = MX3X_UART1_BASE_ADDR;
		break;
	case MACH_TYPE_MAGX_ZN5:
		uart_base = MX3X_UART2_BASE_ADDR;
		break;
	default:
		break;
	}
}

#define arch_decomp_setup()	__arch_decomp_setup(arch_id)
#define arch_decomp_wdog()

#endif				/* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
Commit	Line	Data
52c543f9	1	/*
a09e64fb	2	* arch/arm/plat-mxc/include/mach/uncompress.h
52c543f9 QJ	3	*
	4	*
	5	*
	6	* Copyright (C) 1999 ARM Limited
	7	* Copyright (C) Shane Nay (shane@minirl.com)
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23	#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
	24	#define __ASM_ARCH_MXC_UNCOMPRESS_H__
	25
	26	#define __MXC_BOOT_UNCOMPRESS
	27
a09e64fb	28	#include <mach/hardware.h>
d30c74a0	29	#include <asm/mach-types.h>
52c543f9	30
d30c74a0 SH	31	static unsigned long uart_base;
	32
	33	#define UART(x) ((volatile unsigned long )(uart_base + (x)))
52c543f9 QJ	34
	35	#define USR2 0x98
	36	#define USR2_TXFE (1<<14)
	37	#define TXR 0x40
	38	#define UCR1 0x80
	39	#define UCR1_UARTEN 1
	40
	41	/*
	42	* The following code assumes the serial port has already been
	43	* initialized by the bootloader. We search for the first enabled
	44	* port in the most probable order. If you didn't setup a port in
	45	* your bootloader then nothing will appear (which might be desired).
	46	*
	47	* This does not append a newline
	48	*/
	49
	50	static void putc(int ch)
	51	{
d30c74a0 SH	52	if (!uart_base)
	53	return;
	54	if (!(UART(UCR1) & UCR1_UARTEN))
	55	return;
52c543f9 QJ	56
52c543f9 QJ	57	while (!(UART(USR2) & USR2_TXFE))
03e5386e	58	barrier();
52c543f9 QJ	59
	60	UART(TXR) = ch;
	61	}
	62
	63	#define flush() do { } while (0)
	64
d30c74a0	65	#define MX1_UART1_BASE_ADDR 0x00206000
8c25c36f	66	#define MX25_UART1_BASE_ADDR 0x43f90000
d30c74a0 SH	67	#define MX2X_UART1_BASE_ADDR 0x1000a000
d30c74a0 SH	68	#define MX3X_UART1_BASE_ADDR 0x43F90000
fd6ac7bb	69	#define MX3X_UART2_BASE_ADDR 0x43F94000
d30c74a0 SH	70
	71	static __inline__ void __arch_decomp_setup(unsigned long arch_id)
	72	{
	73	switch (arch_id) {
	74	case MACH_TYPE_MX1ADS:
	75	case MACH_TYPE_SCB9328:
	76	uart_base = MX1_UART1_BASE_ADDR;
	77	break;
635baf6b SH	78	case MACH_TYPE_MX25_3DS:
	79	uart_base = MX25_UART1_BASE_ADDR;
	80	break;
d30c74a0 SH	81	case MACH_TYPE_IMX27LITE:
	82	case MACH_TYPE_MX27_3DS:
	83	case MACH_TYPE_MX27ADS:
	84	case MACH_TYPE_PCM038:
	85	case MACH_TYPE_MX21ADS:
	86	uart_base = MX2X_UART1_BASE_ADDR;
	87	break;
	88	case MACH_TYPE_MX31LITE:
	89	case MACH_TYPE_ARMADILLO5X0:
	90	case MACH_TYPE_MX31MOBOARD:
	91	case MACH_TYPE_QONG:
	92	case MACH_TYPE_MX31_3DS:
	93	case MACH_TYPE_PCM037:
	94	case MACH_TYPE_MX31ADS:
	95	case MACH_TYPE_MX35_3DS:
	96	case MACH_TYPE_PCM043:
115b40c3	97	case MACH_TYPE_LILLY1131:
d30c74a0 SH	98	uart_base = MX3X_UART1_BASE_ADDR;
d30c74a0 SH	99	break;
fd6ac7bb DT	100	case MACH_TYPE_MAGX_ZN5:
	101	uart_base = MX3X_UART2_BASE_ADDR;
	102	break;
d30c74a0 SH	103	default:
	104	break;
	105	}
	106	}
52c543f9	107
d30c74a0	108	#define arch_decomp_setup() __arch_decomp_setup(arch_id)
52c543f9 QJ	109	#define arch_decomp_wdog()
	110
	111	#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */