projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| eea643f7 JB |
1 | /* |
| 2 | * Copyright (C) 1999 ARM Limited | |
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
| 4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 5 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
| 74bef9a4 | 6 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com |
| eea643f7 JB |
7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License as published by | |
| 10 | * the Free Software Foundation; either version 2 of the License, or | |
| 11 | * (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| eea643f7 JB |
17 | */ |
| 18 | ||
| 19 | #include <linux/kernel.h> | |
| 20 | #include <linux/clk.h> | |
| 21 | #include <linux/io.h> | |
| 74bef9a4 IY |
22 | #include <linux/err.h> |
| 23 | #include <linux/delay.h> | |
| 807dfe70 | 24 | #include <linux/module.h> |
| eea643f7 | 25 | |
| a09e64fb | 26 | #include <mach/hardware.h> |
| fd6ac7bb | 27 | #include <mach/common.h> |
| 9f97da78 | 28 | #include <asm/system_misc.h> |
| eea643f7 | 29 | #include <asm/proc-fns.h> |
| c2932bf4 | 30 | #include <asm/mach-types.h> |
| eea643f7 | 31 | |
| f548897f | 32 | void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL; |
| 807dfe70 | 33 | EXPORT_SYMBOL_GPL(imx_ioremap); |
| 41e7daf2 | 34 | |
| be124c94 | 35 | static void __iomem *wdog_base; |
| eea643f7 JB |
36 | |
| 37 | /* | |
| 38 | * Reset the system. It is called by machine_restart(). | |
| 39 | */ | |
| 65ea7884 | 40 | void mxc_restart(char mode, const char *cmd) |
| eea643f7 | 41 | { |
| be124c94 SH |
42 | unsigned int wcr_enable; |
| 43 | ||
| 44 | if (cpu_is_mx1()) { | |
| 45 | wcr_enable = (1 << 0); | |
| 46 | } else { | |
| 74bef9a4 | 47 | struct clk *clk; |
| eea643f7 | 48 | |
| 2c1f4672 | 49 | clk = clk_get_sys("imx2-wdt.0", NULL); |
| 74bef9a4 | 50 | if (!IS_ERR(clk)) |
| bcab5010 | 51 | clk_prepare_enable(clk); |
| be124c94 | 52 | wcr_enable = (1 << 2); |
| eea643f7 JB |
53 | } |
| 54 | ||
| eea643f7 | 55 | /* Assert SRS signal */ |
| be124c94 | 56 | __raw_writew(wcr_enable, wdog_base); |
| 74bef9a4 IY |
57 | |
| 58 | /* wait for reset to assert... */ | |
| 59 | mdelay(500); | |
| 60 | ||
| 61 | printk(KERN_ERR "Watchdog reset failed to assert reset\n"); | |
| 62 | ||
| 63 | /* delay to allow the serial port to show the message */ | |
| 64 | mdelay(50); | |
| 65 | ||
| 66 | /* we'll take a jump through zero as a poor second */ | |
| e879c862 | 67 | soft_restart(0); |
| eea643f7 | 68 | } |
| be124c94 SH |
69 | |
| 70 | void mxc_arch_reset_init(void __iomem *base) | |
| 71 | { | |
| 72 | wdog_base = base; | |
| 73 | } |