projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| eea643f7 JB |
1 | /* |
| 2 | * Copyright (C) 1999 ARM Limited | |
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
| 4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 5 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
| 74bef9a4 | 6 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com |
| eea643f7 JB |
7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License as published by | |
| 10 | * the Free Software Foundation; either version 2 of the License, or | |
| 11 | * (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| eea643f7 JB |
17 | */ |
| 18 | ||
| 19 | #include <linux/kernel.h> | |
| 20 | #include <linux/clk.h> | |
| 21 | #include <linux/io.h> | |
| 74bef9a4 IY |
22 | #include <linux/err.h> |
| 23 | #include <linux/delay.h> | |
| eea643f7 | 24 | |
| a09e64fb | 25 | #include <mach/hardware.h> |
| fd6ac7bb | 26 | #include <mach/common.h> |
| eea643f7 JB |
27 | #include <asm/proc-fns.h> |
| 28 | #include <asm/system.h> | |
| c2932bf4 | 29 | #include <asm/mach-types.h> |
| eea643f7 | 30 | |
| be124c94 | 31 | static void __iomem *wdog_base; |
| eea643f7 JB |
32 | |
| 33 | /* | |
| 34 | * Reset the system. It is called by machine_restart(). | |
| 35 | */ | |
| be093beb | 36 | void arch_reset(char mode, const char *cmd) |
| eea643f7 | 37 | { |
| be124c94 SH |
38 | unsigned int wcr_enable; |
| 39 | ||
| fd6ac7bb DT |
40 | #ifdef CONFIG_ARCH_MXC91231 |
| 41 | if (cpu_is_mxc91231()) { | |
| 42 | mxc91231_arch_reset(mode, cmd); | |
| 43 | return; | |
| 44 | } | |
| 45 | #endif | |
| c2932bf4 APR |
46 | #ifdef CONFIG_MACH_MX51_EFIKAMX |
| 47 | if (machine_is_mx51_efikamx()) { | |
| 48 | mx51_efikamx_reset(); | |
| 49 | return; | |
| 50 | } | |
| 51 | #endif | |
| 52 | ||
| be124c94 SH |
53 | if (cpu_is_mx1()) { |
| 54 | wcr_enable = (1 << 0); | |
| 55 | } else { | |
| 74bef9a4 | 56 | struct clk *clk; |
| eea643f7 | 57 | |
| 2c1f4672 | 58 | clk = clk_get_sys("imx2-wdt.0", NULL); |
| 74bef9a4 IY |
59 | if (!IS_ERR(clk)) |
| 60 | clk_enable(clk); | |
| be124c94 | 61 | wcr_enable = (1 << 2); |
| eea643f7 JB |
62 | } |
| 63 | ||
| eea643f7 | 64 | /* Assert SRS signal */ |
| be124c94 | 65 | __raw_writew(wcr_enable, wdog_base); |
| 74bef9a4 IY |
66 | |
| 67 | /* wait for reset to assert... */ | |
| 68 | mdelay(500); | |
| 69 | ||
| 70 | printk(KERN_ERR "Watchdog reset failed to assert reset\n"); | |
| 71 | ||
| 72 | /* delay to allow the serial port to show the message */ | |
| 73 | mdelay(50); | |
| 74 | ||
| 75 | /* we'll take a jump through zero as a poor second */ | |
| 76 | cpu_reset(0); | |
| eea643f7 | 77 | } |
| be124c94 SH |
78 | |
| 79 | void mxc_arch_reset_init(void __iomem *base) | |
| 80 | { | |
| 81 | wdog_base = base; | |
| 82 | } |