[deliverable/linux.git] / arch / arm / plat-mxc / system.c

/*
 * Copyright (C) 1999 ARM Limited
 * Copyright (C) 2000 Deep Blue Solutions Ltd
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/delay.h>

#include <mach/hardware.h>
#include <mach/common.h>
#include <asm/proc-fns.h>
#include <asm/system.h>
#include <asm/mach-types.h>

void (*imx_idle)(void) = NULL;
void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;

static void __iomem *wdog_base;

/*
 * Reset the system. It is called by machine_restart().
 */
void arch_reset(char mode, const char *cmd)
{
	unsigned int wcr_enable;

#ifdef CONFIG_MACH_MX51_EFIKAMX
	if (machine_is_mx51_efikamx()) {
		mx51_efikamx_reset();
		return;
	}
#endif

	if (cpu_is_mx1()) {
		wcr_enable = (1 << 0);
	} else {
		struct clk *clk;

		clk = clk_get_sys("imx2-wdt.0", NULL);
		if (!IS_ERR(clk))
			clk_enable(clk);
		wcr_enable = (1 << 2);
	}

	/* Assert SRS signal */
	__raw_writew(wcr_enable, wdog_base);

	/* wait for reset to assert... */
	mdelay(500);

	printk(KERN_ERR "Watchdog reset failed to assert reset\n");

	/* delay to allow the serial port to show the message */
	mdelay(50);

	/* we'll take a jump through zero as a poor second */
	cpu_reset(0);
}

void mxc_arch_reset_init(void __iomem *base)
{
	wdog_base = base;
}
Commit	Line	Data
eea643f7 JB	1	/*
	2	* Copyright (C) 1999 ARM Limited
	3	* Copyright (C) 2000 Deep Blue Solutions Ltd
	4	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
74bef9a4	6	* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
eea643f7 JB	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
eea643f7 JB	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/clk.h>
	21	#include <linux/io.h>
74bef9a4 IY	22	#include <linux/err.h>
74bef9a4 IY	23	#include <linux/delay.h>
eea643f7	24
a09e64fb	25	#include <mach/hardware.h>
fd6ac7bb	26	#include <mach/common.h>
eea643f7 JB	27	#include <asm/proc-fns.h>
eea643f7 JB	28	#include <asm/system.h>
c2932bf4	29	#include <asm/mach-types.h>
eea643f7	30
41e7daf2	31	void (*imx_idle)(void) = NULL;
f548897f	32	void __iomem (imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
41e7daf2	33
be124c94	34	static void __iomem *wdog_base;
eea643f7 JB	35
	36	/*
	37	* Reset the system. It is called by machine_restart().
	38	*/
be093beb	39	void arch_reset(char mode, const char *cmd)
eea643f7	40	{
be124c94 SH	41	unsigned int wcr_enable;
be124c94 SH	42
c2932bf4 APR	43	#ifdef CONFIG_MACH_MX51_EFIKAMX
	44	if (machine_is_mx51_efikamx()) {
	45	mx51_efikamx_reset();
	46	return;
	47	}
	48	#endif
	49
be124c94 SH	50	if (cpu_is_mx1()) {
	51	wcr_enable = (1 << 0);
	52	} else {
74bef9a4	53	struct clk *clk;
eea643f7	54
2c1f4672	55	clk = clk_get_sys("imx2-wdt.0", NULL);
74bef9a4 IY	56	if (!IS_ERR(clk))
74bef9a4 IY	57	clk_enable(clk);
be124c94	58	wcr_enable = (1 << 2);
eea643f7 JB	59	}
eea643f7 JB	60
eea643f7	61	/* Assert SRS signal */
be124c94	62	__raw_writew(wcr_enable, wdog_base);
74bef9a4 IY	63
	64	/* wait for reset to assert... */
	65	mdelay(500);
	66
	67	printk(KERN_ERR "Watchdog reset failed to assert reset\n");
	68
	69	/* delay to allow the serial port to show the message */
	70	mdelay(50);
	71
	72	/* we'll take a jump through zero as a poor second */
	73	cpu_reset(0);
eea643f7	74	}
be124c94 SH	75
	76	void mxc_arch_reset_init(void __iomem *base)
	77	{
	78	wdog_base = base;
	79	}