[deliverable/linux.git] / arch / arm / plat-mxc / time.c

/*
 *  linux/arch/arm/plat-mxc/time.c
 *
 *  Copyright (C) 2000-2001 Deep Blue Solutions
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
 *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/err.h>

#include <mach/hardware.h>
#include <asm/sched_clock.h>
#include <asm/mach/time.h>
#include <mach/common.h>

/*
 * There are 2 versions of the timer hardware on Freescale MXC hardware.
 * Version 1: MX1/MXL, MX21, MX27.
 * Version 2: MX25, MX31, MX35, MX37, MX51
 */

/* defines common for all i.MX */
#define MXC_TCTL		0x00
#define MXC_TCTL_TEN		(1 << 0) /* Enable module */
#define MXC_TPRER		0x04

/* MX1, MX21, MX27 */
#define MX1_2_TCTL_CLK_PCLK1	(1 << 1)
#define MX1_2_TCTL_IRQEN	(1 << 4)
#define MX1_2_TCTL_FRR		(1 << 8)
#define MX1_2_TCMP		0x08
#define MX1_2_TCN		0x10
#define MX1_2_TSTAT		0x14

/* MX21, MX27 */
#define MX2_TSTAT_CAPT		(1 << 1)
#define MX2_TSTAT_COMP		(1 << 0)

/* MX31, MX35, MX25, MX5 */
#define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG		(1 << 6)
#define V2_TCTL_CLK_PER		(2 << 6)
#define V2_TCTL_FRR		(1 << 9)
#define V2_IR			0x0c
#define V2_TSTAT		0x08
#define V2_TSTAT_OF1		(1 << 0)
#define V2_TCN			0x24
#define V2_TCMP			0x10

#define timer_is_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
#define timer_is_v2()	(!timer_is_v1())

static struct clock_event_device clockevent_mxc;
static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;

static void __iomem *timer_base;

static inline void gpt_irq_disable(void)
{
	unsigned int tmp;

	if (timer_is_v2())
		__raw_writel(0, timer_base + V2_IR);
	else {
		tmp = __raw_readl(timer_base + MXC_TCTL);
		__raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
	}
}

static inline void gpt_irq_enable(void)
{
	if (timer_is_v2())
		__raw_writel(1<<0, timer_base + V2_IR);
	else {
		__raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
			timer_base + MXC_TCTL);
	}
}

static void gpt_irq_acknowledge(void)
{
	if (timer_is_v1()) {
		if (cpu_is_mx1())
			__raw_writel(0, timer_base + MX1_2_TSTAT);
		else
			__raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
				timer_base + MX1_2_TSTAT);
	} else if (timer_is_v2())
		__raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
}

static void __iomem *sched_clock_reg;

static u32 notrace mxc_read_sched_clock(void)
{
	return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
}

static int __init mxc_clocksource_init(struct clk *timer_clk)
{
	unsigned int c = clk_get_rate(timer_clk);
	void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);

	sched_clock_reg = reg;

	setup_sched_clock(mxc_read_sched_clock, 32, c);
	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
			clocksource_mmio_readl_up);
}

/* clock event */

static int mx1_2_set_next_event(unsigned long evt,
			      struct clock_event_device *unused)
{
	unsigned long tcmp;

	tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;

	__raw_writel(tcmp, timer_base + MX1_2_TCMP);

	return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
				-ETIME : 0;
}

static int v2_set_next_event(unsigned long evt,
			      struct clock_event_device *unused)
{
	unsigned long tcmp;

	tcmp = __raw_readl(timer_base + V2_TCN) + evt;

	__raw_writel(tcmp, timer_base + V2_TCMP);

	return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
				-ETIME : 0;
}

#ifdef DEBUG
static const char *clock_event_mode_label[] = {
	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	[CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
	[CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED",
	[CLOCK_EVT_MODE_RESUME]   = "CLOCK_EVT_MODE_RESUME",
};
#endif /* DEBUG */

static void mxc_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	unsigned long flags;

	/*
	 * The timer interrupt generation is disabled at least
	 * for enough time to call mxc_set_next_event()
	 */
	local_irq_save(flags);

	/* Disable interrupt in GPT module */
	gpt_irq_disable();

	if (mode != clockevent_mode) {
		/* Set event time into far-far future */
		if (timer_is_v2())
			__raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
					timer_base + V2_TCMP);
		else
			__raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
					timer_base + MX1_2_TCMP);

		/* Clear pending interrupt */
		gpt_irq_acknowledge();
	}

#ifdef DEBUG
	printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
		clock_event_mode_label[clockevent_mode],
		clock_event_mode_label[mode]);
#endif /* DEBUG */

	/* Remember timer mode */
	clockevent_mode = mode;
	local_irq_restore(flags);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
				"supported for i.MX\n");
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	/*
	 * Do not put overhead of interrupt enable/disable into
	 * mxc_set_next_event(), the core has about 4 minutes
	 * to call mxc_set_next_event() or shutdown clock after
	 * mode switching
	 */
		local_irq_save(flags);
		gpt_irq_enable();
		local_irq_restore(flags);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_RESUME:
		/* Left event sources disabled, no more interrupts appear */
		break;
	}
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_mxc;
	uint32_t tstat;

	if (timer_is_v2())
		tstat = __raw_readl(timer_base + V2_TSTAT);
	else
		tstat = __raw_readl(timer_base + MX1_2_TSTAT);

	gpt_irq_acknowledge();

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mxc_timer_irq = {
	.name		= "i.MX Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= mxc_timer_interrupt,
};

static struct clock_event_device clockevent_mxc = {
	.name		= "mxc_timer1",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.set_mode	= mxc_set_mode,
	.set_next_event	= mx1_2_set_next_event,
	.rating		= 200,
};

static int __init mxc_clockevent_init(struct clk *timer_clk)
{
	unsigned int c = clk_get_rate(timer_clk);

	if (timer_is_v2())
		clockevent_mxc.set_next_event = v2_set_next_event;

	clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
					clockevent_mxc.shift);
	clockevent_mxc.max_delta_ns =
			clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
	clockevent_mxc.min_delta_ns =
			clockevent_delta2ns(0xff, &clockevent_mxc);

	clockevent_mxc.cpumask = cpumask_of(0);

	clockevents_register_device(&clockevent_mxc);

	return 0;
}

void __init mxc_timer_init(void __iomem *base, int irq)
{
	uint32_t tctl_val;
	struct clk *timer_clk;
	struct clk *timer_ipg_clk;

	timer_clk = clk_get_sys("imx-gpt.0", "per");
	if (IS_ERR(timer_clk)) {
		pr_err("i.MX timer: unable to get clk\n");
		return;
	}

	timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
	if (!IS_ERR(timer_ipg_clk))
		clk_prepare_enable(timer_ipg_clk);

	clk_prepare_enable(timer_clk);

	timer_base = base;

	/*
	 * Initialise to a known state (all timers off, and timing reset)
	 */

	__raw_writel(0, timer_base + MXC_TCTL);
	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */

	if (timer_is_v2())
		tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	else
		tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;

	__raw_writel(tctl_val, timer_base + MXC_TCTL);

	/* init and register the timer to the framework */
	mxc_clocksource_init(timer_clk);
	mxc_clockevent_init(timer_clk);

	/* Make irqs happen */
	setup_irq(irq, &mxc_timer_irq);
}
Commit	Line	Data
d0f349fb JB	1	/*
	2	* linux/arch/arm/plat-mxc/time.c
	3	*
	4	* Copyright (C) 2000-2001 Deep Blue Solutions
	5	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	6	* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	7	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version 2
	12	* of the License, or (at your option) any later version.
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	21	* MA 02110-1301, USA.
	22	*/
	23
	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/clk.h>
821dc4df	28	#include <linux/err.h>
d0f349fb	29
a09e64fb	30	#include <mach/hardware.h>
c124befc	31	#include <asm/sched_clock.h>
d0f349fb	32	#include <asm/mach/time.h>
a09e64fb	33	#include <mach/common.h>
ec996ba9	34
0f3332c4 SH	35	/*
	36	* There are 2 versions of the timer hardware on Freescale MXC hardware.
	37	* Version 1: MX1/MXL, MX21, MX27.
	38	* Version 2: MX25, MX31, MX35, MX37, MX51
	39	*/
	40
ec996ba9 SH	41	/* defines common for all i.MX */
ec996ba9 SH	42	#define MXC_TCTL 0x00
0f3332c4	43	#define MXC_TCTL_TEN (1 << 0) /* Enable module */
ec996ba9 SH	44	#define MXC_TPRER 0x04
	45
	46	/* MX1, MX21, MX27 */
	47	#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
	48	#define MX1_2_TCTL_IRQEN (1 << 4)
	49	#define MX1_2_TCTL_FRR (1 << 8)
	50	#define MX1_2_TCMP 0x08
	51	#define MX1_2_TCN 0x10
	52	#define MX1_2_TSTAT 0x14
	53
	54	/* MX21, MX27 */
	55	#define MX2_TSTAT_CAPT (1 << 1)
	56	#define MX2_TSTAT_COMP (1 << 0)
	57
13cf8df9	58	/* MX31, MX35, MX25, MX5 */
38a66f51 AK	59	#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
38a66f51 AK	60	#define V2_TCTL_CLK_IPG (1 << 6)
1f152b48	61	#define V2_TCTL_CLK_PER (2 << 6)
38a66f51 AK	62	#define V2_TCTL_FRR (1 << 9)
	63	#define V2_IR 0x0c
	64	#define V2_TSTAT 0x08
	65	#define V2_TSTAT_OF1 (1 << 0)
	66	#define V2_TCN 0x24
	67	#define V2_TCMP 0x10
d0f349fb	68
0f3332c4 SH	69	#define timer_is_v1() (cpu_is_mx1() \|\| cpu_is_mx21() \|\| cpu_is_mx27())
	70	#define timer_is_v2() (!timer_is_v1())
	71
d0f349fb JB	72	static struct clock_event_device clockevent_mxc;
	73	static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
	74
ec996ba9	75	static void __iomem *timer_base;
d0f349fb	76
ec996ba9	77	static inline void gpt_irq_disable(void)
d0f349fb	78	{
ec996ba9 SH	79	unsigned int tmp;
ec996ba9 SH	80
0f3332c4	81	if (timer_is_v2())
38a66f51	82	__raw_writel(0, timer_base + V2_IR);
ec996ba9 SH	83	else {
	84	tmp = __raw_readl(timer_base + MXC_TCTL);
	85	__raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
	86	}
	87	}
	88
	89	static inline void gpt_irq_enable(void)
	90	{
0f3332c4	91	if (timer_is_v2())
38a66f51	92	__raw_writel(1<<0, timer_base + V2_IR);
ec996ba9 SH	93	else {
	94	__raw_writel(__raw_readl(timer_base + MXC_TCTL) \| MX1_2_TCTL_IRQEN,
	95	timer_base + MXC_TCTL);
	96	}
	97	}
	98
	99	static void gpt_irq_acknowledge(void)
	100	{
0f3332c4 SH	101	if (timer_is_v1()) {
	102	if (cpu_is_mx1())
	103	__raw_writel(0, timer_base + MX1_2_TSTAT);
	104	else
	105	__raw_writel(MX2_TSTAT_CAPT \| MX2_TSTAT_COMP,
	106	timer_base + MX1_2_TSTAT);
	107	} else if (timer_is_v2())
d943f2c8	108	__raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
ec996ba9 SH	109	}
ec996ba9 SH	110
234b6ced	111	static void __iomem *sched_clock_reg;
d0f349fb	112
2f0778af	113	static u32 notrace mxc_read_sched_clock(void)
c124befc	114	{
2f0778af	115	return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
c124befc JW	116	}
c124befc JW	117
30c730f8	118	static int __init mxc_clocksource_init(struct clk *timer_clk)
d0f349fb	119	{
058b7a6f	120	unsigned int c = clk_get_rate(timer_clk);
234b6ced	121	void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
d0f349fb	122
234b6ced	123	sched_clock_reg = reg;
ec996ba9	124
2f0778af	125	setup_sched_clock(mxc_read_sched_clock, 32, c);
234b6ced RK	126	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
234b6ced RK	127	clocksource_mmio_readl_up);
d0f349fb JB	128	}
	129
	130	/* clock event */
	131
ec996ba9	132	static int mx1_2_set_next_event(unsigned long evt,
d0f349fb JB	133	struct clock_event_device *unused)
	134	{
	135	unsigned long tcmp;
	136
ec996ba9	137	tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
d0f349fb	138
ec996ba9 SH	139	__raw_writel(tcmp, timer_base + MX1_2_TCMP);
	140
	141	return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
	142	-ETIME : 0;
	143	}
	144
38a66f51	145	static int v2_set_next_event(unsigned long evt,
ec996ba9 SH	146	struct clock_event_device *unused)
	147	{
	148	unsigned long tcmp;
	149
38a66f51	150	tcmp = __raw_readl(timer_base + V2_TCN) + evt;
ec996ba9	151
38a66f51	152	__raw_writel(tcmp, timer_base + V2_TCMP);
ec996ba9	153
38a66f51	154	return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
d0f349fb JB	155	-ETIME : 0;
	156	}
	157
	158	#ifdef DEBUG
	159	static const char *clock_event_mode_label[] = {
	160	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	161	[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
	162	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
de9c5159 UKK	163	[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
de9c5159 UKK	164	[CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
d0f349fb JB	165	};
	166	#endif /* DEBUG */
	167
	168	static void mxc_set_mode(enum clock_event_mode mode,
	169	struct clock_event_device *evt)
	170	{
	171	unsigned long flags;
	172
	173	/*
	174	* The timer interrupt generation is disabled at least
	175	* for enough time to call mxc_set_next_event()
	176	*/
	177	local_irq_save(flags);
	178
	179	/* Disable interrupt in GPT module */
	180	gpt_irq_disable();
	181
	182	if (mode != clockevent_mode) {
	183	/* Set event time into far-far future */
0f3332c4	184	if (timer_is_v2())
38a66f51 AK	185	__raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
38a66f51 AK	186	timer_base + V2_TCMP);
ec996ba9 SH	187	else
	188	__raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
	189	timer_base + MX1_2_TCMP);
	190
d0f349fb JB	191	/* Clear pending interrupt */
	192	gpt_irq_acknowledge();
	193	}
	194
	195	#ifdef DEBUG
	196	printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
	197	clock_event_mode_label[clockevent_mode],
	198	clock_event_mode_label[mode]);
	199	#endif /* DEBUG */
	200
	201	/* Remember timer mode */
	202	clockevent_mode = mode;
	203	local_irq_restore(flags);
	204
	205	switch (mode) {
	206	case CLOCK_EVT_MODE_PERIODIC:
	207	printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
	208	"supported for i.MX\n");
	209	break;
	210	case CLOCK_EVT_MODE_ONESHOT:
	211	/*
	212	* Do not put overhead of interrupt enable/disable into
	213	* mxc_set_next_event(), the core has about 4 minutes
	214	* to call mxc_set_next_event() or shutdown clock after
	215	* mode switching
	216	*/
	217	local_irq_save(flags);
	218	gpt_irq_enable();
	219	local_irq_restore(flags);
	220	break;
	221	case CLOCK_EVT_MODE_SHUTDOWN:
	222	case CLOCK_EVT_MODE_UNUSED:
	223	case CLOCK_EVT_MODE_RESUME:
	224	/* Left event sources disabled, no more interrupts appear */
	225	break;
	226	}
	227	}
	228
	229	/*
	230	* IRQ handler for the timer
	231	*/
	232	static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
	233	{
	234	struct clock_event_device *evt = &clockevent_mxc;
	235	uint32_t tstat;
	236
0f3332c4	237	if (timer_is_v2())
38a66f51	238	tstat = __raw_readl(timer_base + V2_TSTAT);
81ec1f92 SH	239	else
81ec1f92 SH	240	tstat = __raw_readl(timer_base + MX1_2_TSTAT);
d0f349fb JB	241
	242	gpt_irq_acknowledge();
	243
	244	evt->event_handler(evt);
	245
	246	return IRQ_HANDLED;
	247	}
	248
	249	static struct irqaction mxc_timer_irq = {
	250	.name = "i.MX Timer Tick",
	251	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	252	.handler = mxc_timer_interrupt,
	253	};
	254
	255	static struct clock_event_device clockevent_mxc = {
	256	.name = "mxc_timer1",
	257	.features = CLOCK_EVT_FEAT_ONESHOT,
	258	.shift = 32,
	259	.set_mode = mxc_set_mode,
ec996ba9	260	.set_next_event = mx1_2_set_next_event,
d0f349fb JB	261	.rating = 200,
	262	};
	263
30c730f8	264	static int __init mxc_clockevent_init(struct clk *timer_clk)
d0f349fb	265	{
058b7a6f	266	unsigned int c = clk_get_rate(timer_clk);
d0f349fb	267
0f3332c4	268	if (timer_is_v2())
38a66f51	269	clockevent_mxc.set_next_event = v2_set_next_event;
ec996ba9	270
058b7a6f	271	clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
d0f349fb JB	272	clockevent_mxc.shift);
	273	clockevent_mxc.max_delta_ns =
	274	clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
	275	clockevent_mxc.min_delta_ns =
	276	clockevent_delta2ns(0xff, &clockevent_mxc);
	277
320ab2b0	278	clockevent_mxc.cpumask = cpumask_of(0);
d0f349fb JB	279
	280	clockevents_register_device(&clockevent_mxc);
	281
	282	return 0;
	283	}
	284
2cfb4518	285	void __init mxc_timer_init(void __iomem *base, int irq)
d0f349fb	286	{
ec996ba9	287	uint32_t tctl_val;
2cfb4518	288	struct clk *timer_clk;
821dc4df SH	289	struct clk *timer_ipg_clk;
821dc4df SH	290
2cfb4518 SH	291	timer_clk = clk_get_sys("imx-gpt.0", "per");
	292	if (IS_ERR(timer_clk)) {
	293	pr_err("i.MX timer: unable to get clk\n");
	294	return;
821dc4df	295	}
ec996ba9	296
2cfb4518 SH	297	timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
	298	if (!IS_ERR(timer_ipg_clk))
	299	clk_prepare_enable(timer_ipg_clk);
	300
46f417de	301	clk_prepare_enable(timer_clk);
d0f349fb	302
8db5d1a6	303	timer_base = base;
ec996ba9	304
d0f349fb JB	305	/*
	306	* Initialise to a known state (all timers off, and timing reset)
	307	*/
d0f349fb	308
ec996ba9 SH	309	__raw_writel(0, timer_base + MXC_TCTL);
	310	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
	311
0f3332c4	312	if (timer_is_v2())
1f152b48	313	tctl_val = V2_TCTL_CLK_PER \| V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
ec996ba9 SH	314	else
	315	tctl_val = MX1_2_TCTL_FRR \| MX1_2_TCTL_CLK_PCLK1 \| MXC_TCTL_TEN;
	316
	317	__raw_writel(tctl_val, timer_base + MXC_TCTL);
d0f349fb JB	318
d0f349fb JB	319	/* init and register the timer to the framework */
30c730f8 SH	320	mxc_clocksource_init(timer_clk);
30c730f8 SH	321	mxc_clockevent_init(timer_clk);
d0f349fb JB	322
d0f349fb JB	323	/* Make irqs happen */
ec996ba9	324	setup_irq(irq, &mxc_timer_irq);
d0f349fb	325	}