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a003708a | 1 | /* |
e24798e6 | 2 | * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
a003708a AK |
3 | * |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/io.h> | |
18 | ||
19 | #include <asm/mach/irq.h> | |
98de0cbb | 20 | #include <asm/exception.h> |
a003708a AK |
21 | |
22 | #include <mach/hardware.h> | |
e24798e6 | 23 | #include <mach/common.h> |
a003708a | 24 | |
cdc3f106 PH |
25 | #include "irq-common.h" |
26 | ||
a003708a AK |
27 | /* |
28 | ***************************************** | |
29 | * TZIC Registers * | |
30 | ***************************************** | |
31 | */ | |
32 | ||
33 | #define TZIC_INTCNTL 0x0000 /* Control register */ | |
34 | #define TZIC_INTTYPE 0x0004 /* Controller Type register */ | |
35 | #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ | |
36 | #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ | |
37 | #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ | |
38 | #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ | |
39 | #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */ | |
40 | #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ | |
41 | #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */ | |
42 | #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ | |
43 | #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ | |
44 | #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ | |
45 | #define TZIC_PND0 0x0D00 /* Pending Register 0 */ | |
58a92600 | 46 | #define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */ |
a003708a AK |
47 | #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ |
48 | #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ | |
49 | #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ | |
50 | ||
51 | void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ | |
52 | ||
fe31ad41 SH |
53 | #define TZIC_NUM_IRQS 128 |
54 | ||
cdc3f106 PH |
55 | #ifdef CONFIG_FIQ |
56 | static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) | |
57 | { | |
58 | unsigned int index, mask, value; | |
59 | ||
60 | index = irq >> 5; | |
61 | if (unlikely(index >= 4)) | |
62 | return -EINVAL; | |
63 | mask = 1U << (irq & 0x1F); | |
64 | ||
65 | value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; | |
66 | if (type) | |
67 | value &= ~mask; | |
68 | __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); | |
69 | ||
70 | return 0; | |
71 | } | |
8b6c44f1 SG |
72 | #else |
73 | #define tzic_set_irq_fiq NULL | |
cdc3f106 PH |
74 | #endif |
75 | ||
010dc8af HW |
76 | #ifdef CONFIG_PM |
77 | static void tzic_irq_suspend(struct irq_data *d) | |
78 | { | |
79 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
80 | int idx = gc->irq_base >> 5; | |
81 | ||
82 | __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); | |
83 | } | |
84 | ||
85 | static void tzic_irq_resume(struct irq_data *d) | |
86 | { | |
87 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
88 | int idx = gc->irq_base >> 5; | |
89 | ||
90 | __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), | |
91 | tzic_base + TZIC_WAKEUP0(idx)); | |
92 | } | |
93 | ||
94 | #else | |
95 | #define tzic_irq_suspend NULL | |
96 | #define tzic_irq_resume NULL | |
97 | #endif | |
a003708a | 98 | |
3439a397 HW |
99 | static struct mxc_extra_irq tzic_extra_irq = { |
100 | #ifdef CONFIG_FIQ | |
101 | .set_irq_fiq = tzic_set_irq_fiq, | |
102 | #endif | |
103 | }; | |
104 | ||
8b6c44f1 | 105 | static __init void tzic_init_gc(unsigned int irq_start) |
a003708a | 106 | { |
8b6c44f1 SG |
107 | struct irq_chip_generic *gc; |
108 | struct irq_chip_type *ct; | |
109 | int idx = irq_start >> 5; | |
110 | ||
111 | gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, | |
112 | handle_level_irq); | |
3439a397 | 113 | gc->private = &tzic_extra_irq; |
8b6c44f1 | 114 | gc->wake_enabled = IRQ_MSK(32); |
8b6c44f1 SG |
115 | |
116 | ct = gc->chip_types; | |
117 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
118 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
119 | ct->chip.irq_set_wake = irq_gc_set_wake; | |
010dc8af HW |
120 | ct->chip.irq_suspend = tzic_irq_suspend; |
121 | ct->chip.irq_resume = tzic_irq_resume; | |
8b6c44f1 SG |
122 | ct->regs.disable = TZIC_ENCLEAR0(idx); |
123 | ct->regs.enable = TZIC_ENSET0(idx); | |
124 | ||
125 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); | |
a003708a AK |
126 | } |
127 | ||
58a92600 SH |
128 | asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) |
129 | { | |
130 | u32 stat; | |
131 | int i, irqofs, handled; | |
132 | ||
133 | do { | |
134 | handled = 0; | |
135 | ||
136 | for (i = 0; i < 4; i++) { | |
137 | stat = __raw_readl(tzic_base + TZIC_HIPND(i)) & | |
138 | __raw_readl(tzic_base + TZIC_INTSEC0(i)); | |
139 | ||
140 | while (stat) { | |
141 | handled = 1; | |
142 | irqofs = fls(stat) - 1; | |
143 | handle_IRQ(irqofs + i * 32, regs); | |
144 | stat &= ~(1 << irqofs); | |
145 | } | |
146 | } | |
147 | } while (handled); | |
148 | } | |
149 | ||
a003708a AK |
150 | /* |
151 | * This function initializes the TZIC hardware and disables all the | |
152 | * interrupts. It registers the interrupt enable and disable functions | |
153 | * to the kernel for each interrupt source. | |
154 | */ | |
155 | void __init tzic_init_irq(void __iomem *irqbase) | |
156 | { | |
157 | int i; | |
158 | ||
159 | tzic_base = irqbase; | |
160 | /* put the TZIC into the reset value with | |
161 | * all interrupts disabled | |
162 | */ | |
163 | i = __raw_readl(tzic_base + TZIC_INTCNTL); | |
164 | ||
165 | __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); | |
166 | __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); | |
167 | __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); | |
168 | ||
169 | for (i = 0; i < 4; i++) | |
170 | __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); | |
171 | ||
172 | /* disable all interrupts */ | |
173 | for (i = 0; i < 4; i++) | |
174 | __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); | |
175 | ||
176 | /* all IRQ no FIQ Warning :: No selection */ | |
177 | ||
8b6c44f1 SG |
178 | for (i = 0; i < TZIC_NUM_IRQS; i += 32) |
179 | tzic_init_gc(i); | |
cdc3f106 PH |
180 | |
181 | #ifdef CONFIG_FIQ | |
182 | /* Initialize FIQ */ | |
183 | init_FIQ(); | |
184 | #endif | |
185 | ||
a003708a AK |
186 | pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); |
187 | } | |
188 | ||
189 | /** | |
190 | * tzic_enable_wake() - enable wakeup interrupt | |
191 | * | |
a003708a AK |
192 | * @return 0 if successful; non-zero otherwise |
193 | */ | |
010dc8af | 194 | int tzic_enable_wake(void) |
a003708a | 195 | { |
010dc8af | 196 | unsigned int i; |
a003708a AK |
197 | |
198 | __raw_writel(1, tzic_base + TZIC_DSMINT); | |
199 | if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) | |
200 | return -EAGAIN; | |
201 | ||
010dc8af HW |
202 | for (i = 0; i < 4; i++) |
203 | __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), | |
204 | tzic_base + TZIC_WAKEUP0(i)); | |
a003708a AK |
205 | |
206 | return 0; | |
207 | } |